CN109473448A - Array substrate and preparation method thereof, liquid crystal display panel, and display device - Google Patents
Array substrate and preparation method thereof, liquid crystal display panel, and display device Download PDFInfo
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/021—Manufacture or treatment of multiple TFTs
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- H—ELECTRICITY
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- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
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Abstract
本发明实施例公开了一种阵列基板及其制备方法、液晶显示面板、显示装置。该方法包括：在玻璃基板之上依次沉积缓冲层、栅极金属层、栅极绝缘层和半导体层，半导体层包括第一半导体区和第二半导体区；定义栅极绝缘层需要开孔的位置，同时暴露出第二半导体区；对玻璃基板及玻璃基板之上沉积的各层进行干法蚀刻制程，蚀刻完成后进行等离子处理，使得第二半导体区变得导体化，第一半导体区被光阻保护；依次进行源漏金属层、钝化层和像素电极层的制作，分别形成阵列基板的TFT区、栅极走线区和透明电容区。本发明实施例提高了阵列基板的透光率，增大了通过阵列基板制备的液晶显示面板或显示装置的开口率。
Embodiments of the present invention disclose an array substrate and a preparation method thereof, a liquid crystal display panel, and a display device. The method includes: sequentially depositing a buffer layer, a gate metal layer, a gate insulating layer and a semiconductor layer on a glass substrate, wherein the semiconductor layer includes a first semiconductor region and a second semiconductor region; defining the position where the gate insulating layer needs to be opened At the same time, the second semiconductor region is exposed; the dry etching process is performed on the glass substrate and the layers deposited on the glass substrate, and plasma treatment is performed after the etching is completed, so that the second semiconductor region becomes conductive, and the first semiconductor region is exposed to light. resistance protection; the source-drain metal layer, the passivation layer and the pixel electrode layer are sequentially fabricated to form the TFT area, the gate wiring area and the transparent capacitor area of the array substrate respectively. The embodiments of the present invention improve the light transmittance of the array substrate, and increase the aperture ratio of the liquid crystal display panel or display device prepared by using the array substrate.
Description
Technical field
The present invention relates to technical field of semiconductor, and in particular to a kind of array substrate and preparation method thereof, liquid crystal
Show panel, display device.
Background technique
Liquid crystal display panel (Liquid Crystal Display, LCD) have fuselage it is thin, it is low in energy consumption, radiation it is small and
Picture shows the advantages that soft equal, has a wide range of applications.Penetrance (transmittance ratio) is liquid crystal display panel
One important indicator of display quality, improves the penetrance of liquid crystal display, can reduce backlight power, reduce cost.In phase
In the case where with backlight, bigger brightness may be implemented, grayscale level is adjustable clearly more demarcated.Usually influence LCD display
A few bulk elements of plate penetrance include: polaroid, liquid crystal efficiency, the film layer absorption of array substrate and color membrane substrates and liquid crystal
The aperture opening ratio of display panel.Liquid crystal efficiency refers to the penetrance under the identical aperture opening ratio of liquid crystal display panel.
Large scale transparent display panel, main problem first is that solve the problems, such as aperture opening ratio, i.e. thin film transistor (TFT) (Thin-
Film transistor, TFT) and capacitor regions accounting as far as possible it is few, to increase the area of penetrating region, but capacitor and TFT
Certain Assurance of Size function is needed, so reduced limited extent.
Summary of the invention
The embodiment of the present invention provides a kind of array substrate and preparation method thereof, liquid crystal display panel, display device, improves
The light transmittance of array substrate increases the aperture opening ratio by the array substrate liquid crystal display panel prepared or display device.
In a first aspect, the application provides a kind of preparation method of array substrate, which comprises
Buffer layer, gate metal layer, gate insulating layer and semiconductor layer are sequentially depositing on glass substrate, it is described partly to lead
Body layer includes the first semiconductor region and the second semiconductor region；
It defines the gate insulating layer and needs the position of aperture, while exposing second semiconductor region；
Dry etching process is carried out to each layer deposited on the glass substrate and the glass substrate, after the completion of etching
Plasma treatment is carried out, so that second semiconductor region becomes conductor, first semiconductor region is protected by photoresist；
Successively carry out Source and drain metal level, passivation layer and pixel electrode layer production, be respectively formed array substrate the area TFT,
Grid cabling area and transparent capacitive area；
Wherein, the pixel electrode layer includes the first pixel electrode area and the second pixel electrode area, the transparent capacitive area
Including second semiconductor region and second pixel electrode area, second semiconductor region and second pixel electrode area
It is prepared for transparent conductive material.
Further, described to be sequentially depositing buffer layer, gate metal layer, gate insulating layer on glass substrate and partly lead
The step of body layer, comprising:
To cleaning glass substrate, and the buffer layer on the glass substrate；
Gate metal layer, and etched figure are deposited on the buffer layer；
Gate insulating layer is deposited on the gate metal layer；
The deposited semiconductor layer on the gate insulating layer, and be patterned.
It is further, described on the glass substrate the step of buffer layer, comprising:
The mixed layer that SiO layer, SiN layer or SiO layer and SiN are deposited on the glass substrate, as buffer layer.
Further, the step of gate metal layer is deposited on the buffer layer, comprising:
The deposited metal material on the buffer layer forms first grid polar region and second on the buffer layer respectively
Gate regions.
Further, the metal material be the single metal of Mo, Al, Cu or Ti or the metal material be Mo,
At least two alloying metal layer is constituted in Al, Cu and Ti.
Further, described the step of gate insulating layer is deposited on the gate metal layer, comprising:
Deposited on the gate metal layer one layer of SiOx or SiNx or film as gate insulating layer, or in institute
Deposition SiOx and SiNx multilayer films on gate metal layer are stated, as gate insulating layer.
Further, 1000-5000 angstroms of the thickness of the gate insulating layer.
It is further, described on the gate insulating layer the step of deposited semiconductor layer, comprising:
One layer of metal oxide semiconductor material is deposited on the gate insulating layer, forms first semiconductor region
With second semiconductor region；
Wherein, first semiconductor region is above the first grid polar region, and second semiconductor region is described second
On the right side of gate regions.
Further, the metal oxide semiconductor material is indium gallium zinc oxide IGZO, indium zinc tin oxide IZTO
Or indium gallium zinc tin oxide IGZTO.
Further, the semiconductor layer with a thickness of 100-1000 angstroms.
Further, the production for successively carrying out Source and drain metal level, passivation layer and pixel electrode layer, is respectively formed array
The step of area TFT of substrate, grid cabling area and transparent capacitive area, comprising:
Deposit Source and drain metal level, and etched figure；
Passivation layer is made on the Source and drain metal level；
Make pixel electrode layer on the passivation layer, and define figure, be respectively formed array substrate the area TFT,
Grid cabling area and transparent capacitive area.
Further, the step of deposition Source and drain metal level, comprising:
Deposited metal layer, so that deposition forms source metal area and drain electrode respectively at left and right sides of first semiconductor region
Metal area forms source and drain metal area above the second gate polar region.
Further, the source metal area, the drain metal area and the source and drain metal area are Mo, Al, Cu or Ti
Single metal layer, alternatively, the source metal area, the drain metal area and the source and drain metal area be Mo, Al, Cu and Ti
In at least two alloying metal layer.
Further, pixel electrode layer is made on the passivation layer, and defines figure, is respectively formed array substrate
The area TFT, grid cabling area and transparent capacitive area, comprising:
The first pixel electrode area is made on the passivation layer, and defines figure, and first pixel electrode area is covered
Cover the source metal area, the drain metal area and the source and drain metal area；
The second pixel electrode area, second pixel electrode area are made on the passivation layer using transparent conductive material
Above second semiconductor region；
Wherein, the corresponding region in the first grid polar region forms the area TFT of array substrate, and the second gate polar region is corresponding
Region forms the grid cabling area of array substrate, and the corresponding region of second semiconductor region forms the transparent capacitive of array substrate
Area.
Further, the transparent conductive material is tin indium oxide ITO or indium zinc oxide IZO.
Second aspect, the application provide a kind of array substrate, and the array substrate from left to right successively includes the area TFT, grid
The transparent capacitive area in pole cabling area and light-permeable.
Further, the array substrate successively includes: from top to bottom
Glass substrate；
Gate metal layer is prepared in the glass baseplate surface, including first grid polar region and second gate polar region；
Gate insulating layer is prepared in the glass baseplate surface, and covers the gate metal layer；
Semiconductor layer is prepared in the gate insulator layer surface, including the first semiconductor region and the second semiconductor region；
Source and drain metal level is prepared in the gate insulating layer and the semiconductor layer surface, including source metal area, drain electrode
Metal area and source and drain metal area；
Passivation layer surrounds the Source and drain metal level；
Pixel electrode layer is prepared in passivation layer layer surface, including the first pixel electrode area and the second pixel electrode area；
Wherein, channel region, the source metal area are formed between the source metal area and the drain metal area
With drain metal area at left and right sides of first semiconductor region, the source and drain metal area is above the second gate polar region, institute
The first semiconductor region is stated above the first grid polar region, second semiconductor region is described on the right side of the second gate polar region
Transparent capacitive area includes second semiconductor region and second pixel electrode area, second semiconductor region and described second
Pixel electrode area is prepared for transparent conductive material.
Further, the glass substrate, the first grid polar region, the gate insulating layer, first semiconductor region,
The source metal area, the drain metal area, the passivation layer and the first pixel electrode district's groups at array the area TFT,
The glass substrate, the second gate polar region, the gate insulating layer, the source and drain metal area, the passivation layer and described
One pixel electrode district's groups are at grid cabling area, the glass substrate, second semiconductor region, the passivation layer and and described
Two pixel electrode district's groups are at transparent capacitive area.
The third aspect, the application provide a kind of liquid crystal display panel, including such as the described in any item array bases of second aspect
Plate.
Fourth aspect, the application provide a kind of display device, including the LCD display as described in any in the third aspect
Plate.
Present invention method on glass substrate by being sequentially depositing buffer layer, gate metal layer, gate insulator
Layer and semiconductor layer, semiconductor layer include the first semiconductor region and the second semiconductor region；It defines gate insulating layer and needs aperture
Position, while exposing the second semiconductor region；Dry etching system is carried out to each layer deposited on glass substrate and glass substrate
Journey carries out plasma treatment after the completion of etching, so that the second semiconductor region becomes conductor, the first semiconductor region is protected by photoresist
Shield；The production for successively carrying out Source and drain metal level, passivation layer and pixel electrode layer, is respectively formed the area TFT of array substrate, grid is walked
Line area and transparent capacitive area.Since transparent capacitive area includes the second semiconductor region and second pixel electrode area, the second half are led
Body area and second pixel electrode area are prepared for transparent conductive material, so that the capacitive region of array substrate inherently can be with
Light transmission, nontransparent capacitive region originally become transparent capacitive area, improve the light transmittance of array substrate, increase through array base
The liquid crystal display panel of plate preparation or the aperture opening ratio of display device.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those skilled in the art, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is a kind of one embodiment flow diagram for the preparation method that the embodiment of the present invention provides array substrate；
Fig. 2 is one embodiment flow diagram of step S101 in embodiment illustrated in fig. 1；
Fig. 3 is one embodiment flow diagram of step S104 in embodiment illustrated in fig. 1；
Fig. 4 is to be sequentially depositing buffer layer, gate metal layer, gate insulating layer in the embodiment of the present invention on glass substrate
With the structural schematic diagram after semiconductor layer；
Fig. 5 is to need the position of aperture defining gate insulating layer in the embodiment of the present invention, while exposing the second half and leading
Structural schematic diagram after body area；
Fig. 6 is that each layer deposited on to glass substrate and glass substrate in the embodiment of the present invention carries out dry etching system
Journey carries out the structural schematic diagram after plasma treatment after the completion of etching；
Fig. 7 is one embodiment structural schematic diagram of array substrate in the embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those skilled in the art's every other implementation obtained without creative efforts
Example, shall fall within the protection scope of the present invention.
As shown in Figure 1, for one embodiment schematic diagram of the preparation method of array substrate in the embodiment of the present invention, this method
Include:
S101, buffer layer, gate metal layer, gate insulating layer and semiconductor layer are sequentially depositing on glass substrate.
Wherein, which includes the first semiconductor region and the second semiconductor region.As shown in Fig. 2, should be in glass substrate
On the step of being sequentially depositing buffer layer, gate metal layer, gate insulating layer and semiconductor layer may further include:
S1011, to cleaning glass substrate, and the buffer layer on glass substrate.
Specifically, the step of buffer layer may include: to deposit SiO on glass substrate on glass substrate
The mixed layer of layer, SiN layer or SiO layer and SiN, as buffer layer, which can be 500-5000 angstroms.
S1012, gate metal layer, and etched figure are deposited on buffer layer.
Specifically, the step of depositing gate metal layer on buffer layer may include: the deposited metal on buffer layer
Material forms first grid polar region and second gate polar region on buffer layer respectively.Wherein, which can be Mo, Al, Cu
Or Ti single metal or the metal material be Mo, Al, Cu and Ti at least two alloying metal layer constitute.Further
, the gate metal layer with a thickness of 2000-10000 angstroms.
S1013, gate insulating layer is deposited on gate metal layer.
Gate insulating layer refers to GI layers, and GI layers, by the technique in a LTPS, are GI Deposition i.e. GI
Layer deposition is formed.GI is the insulating layer in TFT, between gate metal and semiconductor layer, usually SiNx/SiOx, referred to as
Gate Insulator (gate insulating layer).In the embodiment of the present invention, gate insulating layer is deposited on the gate metal layer
The step of, may include: deposited on the gate metal layer one layer of SiOx or SiNx or film as gate insulating layer,
Or SiOx and SiNx multilayer films are deposited on gate metal layer, as gate insulating layer.The thickness of gate insulating layer
Degree is 1000-5000 angstroms.
S1014, the deposited semiconductor layer on gate insulating layer, and be patterned.
Specifically, the step of deposited semiconductor layer including: to deposit one on gate insulating layer on gate insulating layer
Layer metal oxide semiconductor material, forms the first semiconductor region and the second semiconductor region；Wherein, the first semiconductor region is first
Above gate regions, the second semiconductor region is on the right side of second gate polar region.Further, which can be
Indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), indium zinc tin oxide (Indium Zinc Tin
Oxide, IZTO) or indium gallium zinc tin oxide ((Indium Gallium Zinc Tin Oxide, IGZTO).
Wherein, layer semiconductor thickness can be 100-1000 angstroms, and the thickness of the first semiconductor region and the second semiconductor region can
To be consistent, for example, thickness is 500 angstroms.
As shown in figure 4, to be sequentially depositing buffer layer, gate metal layer, gate insulating layer on glass substrate and partly leading
Structural schematic diagram after body layer, wherein deposited buffer layer (not shown), gate metal on glass substrate 401 respectively
Layer (including first grid polar region 4021 and second gate polar region 4022), gate insulating layer 403 and semiconductor layer (including the first semiconductor
Area 4041 and the second semiconductor region 4042).
S102, definition gate insulating layer need the position of aperture, while exposing the second semiconductor region.
In the embodiment of the present invention, defines gate insulating layer and need the position of aperture, while exposing the second semiconductor region
Step, which specifically may is that, carries out one of yellow light technique, defines gate insulating layer and needs the position of aperture, while exposing second
Semiconductor region.Specifically, photoresist 408 is by the first semiconductor region as shown in figure 5, coating photoresist 408 on the semiconductor layer
4041 are covered, meanwhile, the position of aperture is needed in definition gate insulating layer, photoresist overlay region avoids covering the aperture
Position (such as in Fig. 5 between the two panels photoresist of left side opening area), furthermore it is ensured that photoresist 408 do not cover this second half
Conductor region 4042 exposes the second semiconductor region 4042.
S103, dry etching process is carried out to each layer deposited on glass substrate and glass substrate, etching is completed laggard
Row plasma treatment, so that the second semiconductor region becomes conductor, the first semiconductor region is protected by photoresist.
Specifically, carrying out dry etching process to each layer deposited on glass substrate and the glass substrate, etch
At rear carry out plasma treatment, so that the step of the second semiconductor region becomes conductor, and the first semiconductor region is protected by photoresist can
To include: carry out dry etching process, some plasma treatments are added after the completion of dry etching, the second semiconductor can be made
Area becomes conductor, and resistance value is greatly lowered, and is more suitable for capacitor plate, and the first semiconductor region of channel region is protected by photoresist
Shield, still maintains characteristic of semiconductor, to be subsequently formed the area thin film transistor (TFT) (Thin-film transistor, TFT).Such as figure
Photoresist shown in 6, after carrying out dry etching process and plasma treatment, above gate insulating layer 403 and semiconductor layer
It is removed, since in dry etching process, the first semiconductor region 4041 has photoresist protection, the second semiconductor region 4042 does not have
Photoresist (also known as photoresist) protection, can make the second semiconductor region 4042 become conductor, resistance value is greatly lowered, and is more suitable for
As capacitor plate, and the first semiconductor region 4041 is protected by photoresist, still maintains characteristic of semiconductor.Meanwhile gate insulating layer
Need the position of aperture due to there is no photoresist protection to be etched.
S104, the production for successively carrying out Source and drain metal level, passivation layer and pixel electrode layer, are respectively formed array substrate
The area TFT, grid cabling area and transparent capacitive area.
Wherein, the first semiconductor region can be located at the area TFT of array substrate, and the second semiconductor region can be located at array substrate
Transparent capacitive area.
Present invention method on glass substrate by being sequentially depositing buffer layer, gate metal layer, gate insulator
Layer and semiconductor layer, semiconductor layer include the first semiconductor region and the second semiconductor region；It defines gate insulating layer and needs aperture
Position, while exposing the second semiconductor region；Dry etching system is carried out to each layer deposited on glass substrate and glass substrate
Journey carries out plasma treatment after the completion of etching, so that the second semiconductor region becomes conductor, the first semiconductor region is protected by photoresist
Shield；The production for successively carrying out Source and drain metal level, passivation layer and pixel electrode layer, is respectively formed the area TFT of array substrate, grid is walked
Line area and transparent capacitive area.Since transparent capacitive area includes the second semiconductor region and second pixel electrode area, the second half are led
Body area and second pixel electrode area are prepared for transparent conductive material, so that the capacitive region of array substrate inherently can be with
Light transmission, nontransparent capacitive region originally become transparent capacitive area, improve the light transmittance of array substrate, increase through array base
The liquid crystal display panel of plate preparation or the aperture opening ratio of display device.
In some embodiment of the invention, as shown in figure 3, this successively carries out Source and drain metal level, passivation layer and pixel electrode
The production of layer, can further include the step of being respectively formed the area TFT, grid cabling area and transparent capacitive area of array substrate:
S1041, deposition Source and drain metal level, and etched figure.
Specifically, deposition Source and drain metal level, and etched figure can further include: deposited metal layer, so that
Deposition forms source metal area and drain metal area respectively at left and right sides of first semiconductor region, forms source above second gate polar region
Leak metal area.Wherein, the source metal area, drain metal area and source and drain metal area are the single metal layer of Mo, Al, Cu or Ti,
Or the alloying metal floor that source metal area, drain metal area and source and drain metal area are in Mo, Al, Cu and Ti at least two.
S1042, passivation layer is made on Source and drain metal level.
S1043, pixel electrode layer is made on passivation layer, and define figure, be respectively formed the TFT of array substrate
Area, grid cabling area and transparent capacitive area.
Pixel electrode layer is made on passivation layer, and defines figure, is respectively formed the area TFT, the grid of array substrate
Cabling area and transparent capacitive area, comprising: the first pixel electrode area is made on passivation layer, and defines figure, first picture
Plain electrode district covering source metal area, drain metal area and source and drain metal area；It is made on passivation layer using transparent conductive material
Make the second pixel electrode area, the second pixel electrode area is above the second semiconductor region；Wherein, the corresponding region in first grid polar region
Forming the area TFT of array substrate, the corresponding region in the second gate polar region forms the grid cabling area of array substrate, and described the second half
The corresponding region in conductor region forms the transparent capacitive area of array substrate.Further, transparent conductive material be tin indium oxide ITO or
Person's indium zinc oxide IZO.
As shown in fig. 7, at this point, the glass substrate 401, first grid polar region 4021, gate insulating layer 403, the first semiconductor
Area 4041, source metal area 4051, drain metal area 4052, passivation layer 406 and the first pixel electrode area 4071 form array
The area TFT 410, glass substrate 401, second gate polar region 4022, gate insulating layer 403, source and drain metal area 4053,406 and of passivation layer
First pixel electrode area 4071 forms grid cabling area 420, glass substrate 401, the second semiconductor region 4042,406 and of passivation layer
Transparent capacitive area 430 is formed with the second pixel electrode area 4072.
A kind of array substrate was also provided in the embodiment of the present invention, as shown in fig. 7, the array substrate is from left to right successively wrapped
Include the transparent capacitive area 430 in the area TFT 410, grid cabling area 420 and light-permeable.Since the capacitive region of array substrate inherently may be used
With light transmission, nontransparent capacitive region originally becomes transparent capacitive area, increases the display of array substrate preparation or opening for device
Mouth rate.
Specifically, as shown in fig. 7, the array substrate successively may include: from top to bottom
Glass substrate 401；
Gate metal layer is prepared in 401 surface of glass substrate, including first grid polar region 4021 and second gate polar region 4022；
Gate insulating layer 403 is prepared in 401 surface of glass substrate, and covers gate metal layer；
Semiconductor layer is prepared in 403 surface of gate insulating layer, including the first semiconductor region 4041 and the second semiconductor region
4042；
Source and drain metal level is prepared in gate insulating layer 403 and semiconductor layer surface, including source metal area 4051, drain electrode
Metal area 4052 and source and drain metal area 4053；
Passivation layer 406 surrounds Source and drain metal level；
Pixel electrode layer is prepared in 406 surface of passivation layer, including the first pixel electrode area 4071 and the second pixel electrode area
4072；
Wherein, channel region, source metal area 4051 are formed between source metal area 4051 and drain metal area 4052
With drain metal area 4052 in 4041 left and right sides of the first semiconductor region, source and drain metal area 4053 is on second gate polar region 4022
Side, the first semiconductor region 4041 first grid polar region 4021 above, the second semiconductor region 4042 on the right side of second gate polar region 4022,
Transparent capacitive area 430 includes the second semiconductor region 4042 and the second pixel electrode area 4072, the second semiconductor region 4042 and second
Pixel electrode area 4072 is prepared for transparent conductive material.Further, the transparent conductive material be tin indium oxide ITO or
Indium zinc oxide IZO.
Further, the glass substrate 401, first grid polar region 4021, gate insulating layer 403, the first semiconductor region 4041,
Source metal area 4051, drain metal area 4052, passivation layer 406 and the first pixel electrode area 4071 form the area TFT of array
410, glass substrate 401, second gate polar region 4022, gate insulating layer 403, source and drain metal area 4053, passivation layer 406 and the first picture
Plain electrode district 4071 forms grid cabling area 420, glass substrate 401, the second semiconductor region 4042, passivation layer 406 and with second
Pixel electrode area 4072 forms transparent capacitive area 430.
A kind of liquid crystal display panel is also provided in the embodiment of the present invention, including array described in any embodiment as above
Substrate.
A kind of display device is also provided in the embodiment of the present invention, including array base described in any embodiment as above
Plate.
When it is implemented, above each unit can be used as independent entity to realize, any combination can also be carried out, is made
It is realized for same or several entities, the specific embodiment of above each unit can be found in the embodiment of the method for front, example
The thickness of such as each layer, details are not described herein.
It is provided for the embodiments of the invention a kind of array substrate and preparation method thereof, liquid crystal display panel, display above
Device is described in detail, and used herein a specific example illustrates the principle and implementation of the invention, with
The explanation of upper embodiment is merely used to help understand method and its core concept of the invention；Meanwhile for the technology of this field
Personnel, according to the thought of the present invention, there will be changes in the specific implementation manner and application range, in conclusion this theory
Bright book content should not be construed as limiting the invention.
Claims (20)
1. a kind of preparation method of array substrate, which is characterized in that the described method includes:
Buffer layer, gate metal layer, gate insulating layer and semiconductor layer, the semiconductor layer are sequentially depositing on glass substrate
Including the first semiconductor region and the second semiconductor region；
It defines the gate insulating layer and needs the position of aperture, while exposing second semiconductor region；
Dry etching process is carried out to each layer deposited on the glass substrate and the glass substrate, is carried out after the completion of etching
Plasma treatment, so that second semiconductor region becomes conductor, first semiconductor region is protected by photoresist；
The production for successively carrying out Source and drain metal level, passivation layer and pixel electrode layer, is respectively formed the area TFT, the grid of array substrate
Cabling area and transparent capacitive area；
Wherein, the pixel electrode layer includes the first pixel electrode area and the second pixel electrode area, and the transparent capacitive area includes
Second semiconductor region and second pixel electrode area, second semiconductor region and second pixel electrode area are
Bright conductive material is prepared.
2. the preparation method of array substrate according to claim 1, which is characterized in that it is described on glass substrate successively
The step of buffer layer, gate metal layer, gate insulating layer and semiconductor layer, comprising:
To cleaning glass substrate, and the buffer layer on the glass substrate；
Gate metal layer, and etched figure are deposited on the buffer layer；
Gate insulating layer is deposited on the gate metal layer；
The deposited semiconductor layer on the gate insulating layer, and be patterned.
3. the preparation method of array substrate according to claim 2, which is characterized in that described on the glass substrate
The step of buffer layer, comprising:
The mixed layer that SiO layer, SiN layer or SiO layer and SiN are deposited on the glass substrate, as buffer layer.
4. the preparation method of array substrate according to claim 2, which is characterized in that deposit grid on the buffer layer
The step of pole metal layer, comprising:
The deposited metal material on the buffer layer forms first grid polar region and second grid on the buffer layer respectively
Area.
5. the preparation method of array substrate according to claim 4, which is characterized in that the metal material is Mo, Al, Cu
Or Ti single metal or the metal material be Mo, Al, Cu and Ti at least two alloying metal layer constitute.
6. the preparation method of array substrate according to claim 2, which is characterized in that it is described the gate metal layer it
The step of upper deposition gate insulating layer, comprising:
Deposited on the gate metal layer one layer of SiOx or SiNx or film as gate insulating layer, or in the grid
SiOx and SiNx multilayer films are deposited on the metal layer of pole, as gate insulating layer.
7. the preparation method of array substrate according to claim 6, which is characterized in that the thickness of the gate insulating layer
1000-5000 angstroms.
8. the preparation method of array substrate according to claim 4, which is characterized in that it is described the gate insulating layer it
The step of upper deposited semiconductor layer, comprising:
One layer of metal oxide semiconductor material is deposited on the gate insulating layer, forms first semiconductor region and institute
State the second semiconductor region；
Wherein, first semiconductor region is above the first grid polar region, and second semiconductor region is in the second grid
On the right side of area.
9. the preparation method of array substrate according to claim 8, which is characterized in that the metal-oxide semiconductor (MOS) material
Material is indium gallium zinc oxide IGZO, indium zinc tin oxide IZTO or indium gallium zinc tin oxide IGZTO.
10. the preparation method of array substrate according to claim 9, which is characterized in that the semiconductor layer with a thickness of
100-1000 angstroms.
11. the preparation method of array substrate according to claim 8, which is characterized in that described successively to carry out source and drain metal
The production of layer, passivation layer and pixel electrode layer is respectively formed the area TFT of array substrate, grid cabling area and transparent capacitive area
Step, comprising:
Deposit Source and drain metal level, and etched figure；
Passivation layer is made on the Source and drain metal level；
Pixel electrode layer is made on the passivation layer, and defines figure, is respectively formed the area TFT, the grid of array substrate
Cabling area and transparent capacitive area.
12. the preparation method of array substrate according to claim 11, which is characterized in that the deposition Source and drain metal level
Step, comprising:
Deposited metal layer, so that deposition forms source metal area and drain metal respectively at left and right sides of first semiconductor region
Area forms source and drain metal area above the second gate polar region.
13. the preparation method of array substrate according to claim 12, which is characterized in that the source metal area, described
Drain metal area and the source and drain metal area are the single metal layer of Mo, Al, Cu or Ti, alternatively, the source metal area, described
The alloying metal floor that drain metal area and the source and drain metal area are in Mo, Al, Cu and Ti at least two.
14. the preparation method of array substrate according to claim 11, which is characterized in that made on the passivation layer
Pixel electrode layer, and figure is defined, it is respectively formed the area TFT, grid cabling area and transparent capacitive area of array substrate, comprising:
The first pixel electrode area is made on the passivation layer, and defines figure, and first pixel electrode area covers institute
State source metal area, the drain metal area and the source and drain metal area；
The second pixel electrode area is made on the passivation layer using transparent conductive material, second pixel electrode area is in institute
It states above the second semiconductor region；
Wherein, the corresponding region in the first grid polar region forms the area TFT of array substrate, the corresponding region in the second gate polar region
The grid cabling area of array substrate is formed, the corresponding region of second semiconductor region forms the transparent capacitive area of array substrate.
15. the preparation method of array substrate according to claim 14, which is characterized in that the transparent conductive material is oxygen
Change indium tin ITO or indium zinc oxide IZO.
16. a kind of array substrate, which is characterized in that the array substrate from left to right successively include the area TFT, grid cabling area and
The transparent capacitive area of light-permeable.
17. array substrate according to claim 16, which is characterized in that the array substrate successively includes: from top to bottom
Glass substrate；
Gate metal layer is prepared in the glass baseplate surface, including first grid polar region and second gate polar region；
Gate insulating layer is prepared in the glass baseplate surface, and covers the gate metal layer；
Semiconductor layer is prepared in the gate insulator layer surface, including the first semiconductor region and the second semiconductor region；
Source and drain metal level is prepared in the gate insulating layer and the semiconductor layer surface, including source metal area, drain metal
Area and source and drain metal area；
Passivation layer surrounds the Source and drain metal level；
Pixel electrode layer is prepared in passivation layer layer surface, including the first pixel electrode area and the second pixel electrode area；
Wherein, channel region, the source metal area and leakage are formed between the source metal area and the drain metal area
Pole metal area is at left and right sides of first semiconductor region, and the source and drain metal area is above the second gate polar region, and described
Above the first grid polar region, second semiconductor region is described transparent on the right side of the second gate polar region in semiconductor area
Capacitive region includes second semiconductor region and second pixel electrode area, second semiconductor region and second pixel
Electrode district is prepared for transparent conductive material.
18. array substrate according to claim 17, which is characterized in that the glass substrate, the first grid polar region, institute
State gate insulating layer, first semiconductor region, the source metal area, the drain metal area, the passivation layer and described
First pixel electrode district's groups at array the area TFT, it is the glass substrate, the second gate polar region, the gate insulating layer, described
Source and drain metal area, the passivation layer and the first pixel electrode district's groups are at grid cabling area, the glass substrate, described second
Semiconductor region, the passivation layer and and the second pixel electrode district's groups at transparent capacitive area.
19. a kind of liquid crystal display panel, which is characterized in that including the array base as described in any one of claim 16 to 18
Plate.
20. a kind of display device, which is characterized in that including liquid crystal display panel as claimed in claim 19.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201811315137.0A CN109473448A (en) | 2018-11-06 | 2018-11-06 | Array substrate and preparation method thereof, liquid crystal display panel, and display device |
| PCT/CN2018/116840 WO2020093458A1 (en) | 2018-11-06 | 2018-11-22 | Array substrate and preparation method therefor, liquid crystal display panel, and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811315137.0A CN109473448A (en) | 2018-11-06 | 2018-11-06 | Array substrate and preparation method thereof, liquid crystal display panel, and display device |
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| CN201811315137.0A Pending CN109473448A (en) | 2018-11-06 | 2018-11-06 | Array substrate and preparation method thereof, liquid crystal display panel, and display device |
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| WO (1) | WO2020093458A1 (en) |
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| WO2020093458A1 (en) | 2020-05-14 |
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