CN109461811B - A hybrid reconfigurable method for CRS resistive memory - Google Patents

Abstract

The invention discloses a hybrid reconfigurable method of a CRS resistive memory, belonging to the technical field of information storage. The invention belongs to the technical field of information storage. The method of the present invention includes: in the cross point array of the CRS resistive memory, each word line contains only one MEM unit, or each bit line contains only one MEM unit; adopting the direct mapping method to store the mode flag bit of the MEM unit, constructing Unit mode record table; CRS resistive memory adopts 1TnR structure; dynamically switch the working mode of storage unit to ensure that the most frequently accessed unit is in MEM mode. The method of the invention combines the two working modes of the CRS unit, complements the shortcomings of the other party, and realizes that the array unit can be reconfigured with less overhead under the condition of being transparent to the operating system. Therefore, while suppressing the sneak current of the storage array, improving the reliability and reducing the power consumption, the recovery write operation of the CRS unit is minimized, so as to obtain a lower delay and a longer service life.

Description

A hybrid reconfigurable method for CRS resistive memory

technical field

The invention belongs to the technical field of information storage, and more particularly, relates to a hybrid reconfigurable method of CRS resistive memory.

Background technique

A new type of non-volatile memory - Resistive Random-Access Memory (ReRAM, Resistive Random-Access Memory) is a passive two-terminal memory device composed of specific resistive materials (for example, some metal oxides), with a unit resistance value. to indicate the stored information. Generally, a high-impedance state of a cell represents a logic 0, and a low-impedance state of the cell represents a logic 1. The transition of the cell state from logic 0 to logic 1 is called a set operation (SET), and the transition of the cell state from logic 1 to logic 0 is called a reset operation (RESET).

As shown in Figure 1a, ReRAM can be organized in a cross-point array to construct a memory array, in which ReRAM devices are directly sandwiched between word lines and bit lines. Its ReRAM cell area can reach the theoretical minimum value of 4F ² (F is the feature size), which is an effective way to build high-capacity, high-density storage.

As shown in Figure 1b, a voltage half-biasing scheme is generally used to write to the target cells of the cross-point array. However, the write operation to the target cell will cause the cells in the same row and the same column to be in a semi-selected state. These semi-selected cells bring about a great waste of power consumption and occupy a major part of the total power consumption of the operation. At the same time, the sneak current in the array causes the voltage drop problem through the wires, which reduces the effective voltage across the target cell, especially when there are many low-resistance cells in the array, the voltage drop is more serious, which brings reliability problems.

As shown in Figure 1c, the traditional double-ended floating read strategy is used for the cross-point array, that is, the word lines and bit lines in different rows and columns of the target cell are all floating, and the current on the bit line of the target cell is judged by the size of V _o The resistance state of the target cell is distinguished by the size (the figure shows the judgment method using the voltage V _o ). This read strategy has the advantage of low energy consumption, but is greatly affected by the sneak current. In the worst case, except for the target cell to be read, other cells in the array are in a low resistance state, such as the low resistance cells (white cells) that form a 3-length sneak path with the target cell as shown in the figure. These low-resistance units and the target unit are in a parallel relationship. Regardless of whether the target unit is in a low-resistance state or a high-resistance state, the paralleled resistances are all low resistances, which may cause misreading of the information stored in the target unit.

As shown in Figure 1d, a complementary resistive switch (CRS, Complementary Resistive Switch) is a special resistive memory device. Logically, it can be seen that two ReRAM cells are connected relative to each other. Each logic cell has two states: high-impedance state (off state) and low-impedance state (on state), so a CRS unit has 4 states 'off/off', 'on/off', 'off/on' and 'on/on'. The 'off/off' state exists only when the CRS unit is just prepared, and this state is not used in the storage process. While 'on/off' and 'off/on' are high-impedance states, and 'on/on' are low-impedance states. The CRS unit represents logic 1 and logic 0 through two high-impedance states 'on/off' and 'off/on', respectively. Since the cells are all in a high-impedance state, sneak current can be effectively suppressed in the cross-point array. The problem with CRS cells is that their read operations are destructive in order to correctly determine the logical value stored in the cell. The 'on/off' state of logic 1 is changed to 'on/on' state (high impedance to low impedance) during the read process (using the right read window), while the 'off/on' state of logic 0 Then there is no change (maintaining a high-impedance state), from which it can be discerned that the cell stores a logic value. If the left read window is used, the 'off/on' state of logic 0 becomes the 'on/on' state (high-impedance state becomes low-impedance state) during the reading process, while the 'on/off' state of logic 1 No change occurs (maintains a high-impedance state). Due to the destructive read operation of the CRS unit, an additional write operation is required to restore the original state, which is called a recovery write operation. That is, the read operation of the CRS unit is actually a special write operation, which requires a half-bias voltage scheme and an additional write recovery operation, which brings additional operation delay and energy consumption. Applying different ranges of voltages to the CRS cell, such as only using the 'off/on' and 'on/on' states to represent logic 0 and logic 1, can form a normal ReRAM cell with non-destructive read operations. That is, the CRS unit can work in two different modes: the high-impedance state is used to represent both logic 0 and logic 1, which we call the CRS mode; the other is the same as the ordinary ReRAM unit, which uses the high-impedance state to represent logic 0, and the low-impedance state. The state represents a logic 1, which we call the MEM mode. The two modes have different properties. The CRS mode can effectively suppress the sneak current but its read operation is destructive, while the MEM mode provides a non-destructive read operation but suffers from a larger sneak current. In addition, it can be found that if the read operation of the CRS mode does not add a recovery write operation, the working mode of the CRS mode is automatically changed to the MEM mode. Hereinafter, the read and write operations in the CRS mode are referred to as CRSModeWR and CRSModeRD, and the read and write operations in the MEM mode are referred to as MEMModeWR and MEMModeRD. It should be noted that MEMModeRD is a double-ended floating read strategy, while CRSModeWR, CRSModeRD, and MEMModeWR need to use half-bias voltage schemes with different voltages. Existing CRS cell hybrid arrays, which require the participation of the operating system, add additional record information to the page table to track cell patterns. And regular detection is required to switch the infrequently accessed units to CRS mode. This method requires operating system co-optimization and has a large overhead.

SUMMARY OF THE INVENTION

In view of the above defects or improvement requirements of the prior art, the present invention provides a hybrid reconfigurable method of CRS resistive memory, the purpose of which is to combine the two working modes of the CRS unit, complement the shortcomings of the other party, and be transparent to the operating system. In the case of , the array unit can be reconfigured with less overhead. Therefore, while suppressing the sneak current of the storage array, improving the reliability and reducing the power consumption, the recovery write operation of the CRS unit is minimized, so as to obtain a lower delay and a longer service life.

In order to achieve the above object, the present invention provides a hybrid reconfigurable method of CRS resistive memory, the method comprises the following steps:

In the cross-point array of the CRS resistive memory, each word line contains only one MEM cell (OWOM), or each bit line contains only one MEM cell (OBOM);

The mode flag bit of the MEM unit is stored by the direct mapping method, and the unit mode record table is constructed;

CRS resistive memory adopts 1TnR structure;

Dynamically switch the working mode of the storage unit to ensure that the most frequently accessed unit is in MEM mode.

Further, the working mode of the dynamic switching storage unit to ensure that the most frequently accessed unit is in the MEM mode includes:

The recovery write operation of the delayed CRS mode unit specifically includes the following sub-steps:

(1) Judging whether it is a write operation or a read operation, if the write operation enters step (2); otherwise, enter step (3);

(2) query the target unit mode, if it is the MEM mode, then the target unit adopts the MEM write operation MEMModeWR; otherwise, adopts the CRS write operation CRSModeWR, and ends;

(3) query target unit mode, if it is MEM mode, then target unit adopts MEM read operation MEMModeRD; Otherwise, enter step (4);

(4) query the MEM unit on the sub-line where the target unit is located, carry out MEM read operation MEMModeRD to this MEM unit, and restore this MEM unit to CRS mode by restoring write operation CRSModeWR;

(5) The CRS read operation CRSModeRD is performed on the target unit, but the recovery write operation is not performed, so that the target unit is converted into the MEM mode, the unit mode record table is updated, and the end is ended.

Further, in the step (2) and step (3), the query target unit mode is specifically:

Query the unit mode record table and compare it with the flag bit of the target unit address. If they are consistent, the target unit is in MEM mode; otherwise, the target unit is in CRS mode.

Further, the working mode of the dynamic switching storage unit to ensure that the most frequently accessed unit is in the MEM mode also includes:

If each word line in the cross point array of the CRS resistive memory contains only one MEM cell, column priority addressing is used;

If each bit line contains only one MEM cell, conventional row-first addressing is used.

In general, compared with the prior art, the above technical solutions conceived by the present invention have the following technical features and beneficial effects:

(1) The OWOM or OBOM structure in the method of the present invention can effectively suppress the sneak current, and a low-energy double-ended floating read strategy can be used to read the array MEM cells; at the same time, because the array half-selected cells are basically in the CRS mode In a high-impedance state, lower power consumption is also required when writing to the array. The vast majority of cells in the array are in a high-impedance state, which improves the overall array reliability;

(2) Since the method of the present invention adopts the OWOM or OBOM structure, the MEM mode unit is less, and the mode flag bit of the MEM unit is stored by the direct mapping method, and the unit mode record table is constructed, only a small record table overhead is required, and the Operating system transparency;

(3) The method of the present invention greatly reduces the recovery write operation of the CRS mode unit by delaying the recovery write operation of the CRS mode unit, under the guarantee of the OWOM or OBOM rule, in conjunction with the column priority addressing and utilizing the program locality, and improves the system performance and overall array life.

Description of drawings

1a is a schematic diagram of a cross-point array of a resistive memory;

Figure 1b is a schematic diagram of a half-bias write strategy of a resistive memory;

FIG. 1c is a schematic diagram of a fully floating read strategy of a resistive memory;

Figure 1d is a schematic diagram of the complementary resistive cell structure and I-V curve of the CRS resistive memory;

Fig. 2 is the overall flow schematic diagram of the method of the present invention;

3 is a schematic diagram of a full-float reading strategy using OWOM rules in the method of the present invention;

Fig. 4 is the flow chart of the lazy cell mode switching strategy in the method of the present invention;

Figure 5 shows the record table structure and overhead in the implementation of the method of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

As shown in Figure 2, the present invention includes:

(1) CRS cell mode mixed organization rules, that is, each word line in the cross point array can only contain one MEM mode cell (OWOM, One Wordline One MEM); or each bit line can only contain one MEM mode cell ( OBOM, One Bitline One MEM); OBOW and OWOM are symmetrical in form, and the following only takes OWOM as an example; OWOM limits the number of MEM mode cells on each word line to one, so that in the process of reading MEM mode cells, The sneak current is effectively suppressed, and a low-energy double-ended floating read strategy can be used;

个CRS模式单元，它们均处于CRS模式即高阻态，有效抑制了潜行路径上的潜行电流，同时在对单元进行写入的过程中，由于大部分半选择单元处于CRS模式为高阻态，阵列所需能耗极少；As shown in Figure 3, a sneak path with a length of 3 units is formed to the target unit through the current paths of x, y, and z. Since the OWOM rule is adopted, MEMModeRD is used for the target unit, that is, the target unit is in MEM mode, so the x unit It must be in CRS mode, that is, at the same time, one of the two units y and z must be in CRS mode, so there must be two units in the high-impedance state on the sneak path with length 3. In Figure 3, through a, b, c, d, The e current path forms a sneak path with a length of 5 units to the target unit, and a similar conclusion can also be obtained, that is, there are 3 units on the path in a high-resistance state; more generally, on a sneak path with a length of n, at least there are

CRS mode cells, they are all in CRS mode, that is, high-impedance state, which effectively suppresses the sneak current on the sneak path. The array requires very little power consumption;

(2) Build the unit mode record table, and store the flag bits of the MEM unit mode by means of a direct mapping table; you can compare the flag bits of the memory access address with the flag bits queried in the unit mode record table, if they are consistent, the The unit working mode is MEM mode; since the access to the memory is based on the cache line (64B) as the basic unit, that is, 512 storage units with the same relative positions in the array are combined into one 64B, so the 512 units can pass the same The flag bit is used to judge, which greatly reduces the storage overhead of the unit mode record table;

(3) Using 1TnR structure (one transistor n resistor), in the case of large array scale, the number of MEM mode cells is increased at the same time without violating the OWOM rule;

Large-scale arrays can better improve storage density, but at the same time, in order to ensure OWOM, the proportion of MEM mode cells will be reduced; we propose to use 1TnR structure, because the transistors in the 1TnR cross-point array separate the large array word lines to form A number of small arrays that do not interfere with each other are provided, which can increase the number of MEM mode units while ensuring the rules of OWOM; as shown in Figure 5, under the 1T64R crosspoint array structure, 4GB of memory requires 6*220/8=768KB of memory The tag table is used to track the unit mode; because the direct mapping mode is used for recording, the lower 20 bits of the address are the index bits (index), the upper 6 bits are the flag bits (tag), and the address is 64-byte aligned;

(4) CRS unit mode switching strategy, by dynamically switching the working mode of the CRS unit, under the rule of ensuring OWOM, the frequently accessed unit is in the MEM mode without resuming the write operation; the infrequently accessed unit is in the CRS mode, more Good suppression of sneak current; specifically includes:

(41) Lazy recovery write strategy, in the case of ensuring the rules of OWOM, delay the recovery write operation of the CRS mode unit as much as possible; its process is shown in Figure 4, and the more specific steps include:

(411) determine whether it is a write operation or a read operation, if the write operation enters step (412); otherwise, enter step (413);

(412) query target unit mode, if it is MEM mode, then target unit adopts MEM write operation MEMModeWR; Otherwise, adopts CRS write operation CRSModeWR, finishes;

(413) query the target unit mode, if it is the MEM mode, then the target unit adopts the MEM read operation MEMModeRD; otherwise, enter step (414);

(414) query the MEM unit on the sub-line where the target unit is located, carry out the MEM read operation MEMModeRD to the MEM unit, and restore the MEM unit to the CRS mode by the recovery write operation CRSModeWR;

(415) CRS read operation CRSModeRD is carried out to target unit, but do not carry out recovery write operation, make target unit be converted into MEM mode, update unit mode record table, finish;

(42) Column priority addressing, so that the memory addresses of adjacent cells on the array word line are as far as possible; if OBOW is used, traditional row priority addressing can be used; only OWOM is discussed here, and the basic idea is to make the above recovery write The operation is reduced, so the principle of program locality is used to address the adjacent cells on the same word line as far as possible; for the four logical arrays shown on the left of Figure 5, the cells on the bit line are first addressed before addressing For cells on the same word line, the memory addresses of adjacent cells on the word line are as far away as possible.

Those skilled in the art can easily understand the above content, the above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, any modification, equivalent replacement and improvement made within the spirit and principle of the present invention etc., should be included within the protection scope of the present invention.

Claims (3)

1. A hybrid reconfigurable method of a CRS resistive random access memory is characterized by comprising the following steps:

in a cross point array of the CRS resistive random access memory, each word line only comprises one MEM unit, or each bit line only comprises one MEM unit;

storing the mode flag bit of the MEM unit by adopting a direct mapping method, and constructing a unit mode recording table;

the CRS resistive random access memory adopts a 1TnR structure;

dynamically switching the working mode of the storage unit to ensure that the most frequently accessed unit is in an MEM mode;

the dynamically switching the operating mode of the storage unit to ensure that the most frequently accessed unit is in the MEM mode comprises:

delaying the recovery writing operation of the CRS mode unit specifically comprises the following sub-steps:

(1) judging whether the operation is writing operation or reading operation, and entering the step (2) if the operation is writing operation; otherwise, entering the step (3);

(2) inquiring the mode of the target unit, and if the mode is the MEM mode, adopting MEM write operation MEMModeWR by the target unit; otherwise, CRS write operation CRSModeWR is adopted, and the operation is finished;

(3) inquiring the mode of the target unit, and if the mode is the MEM mode, adopting MEM read operation MEMModeRD by the target unit; otherwise, entering the step (4);

(4) inquiring an MEM unit on a sub-line where a target unit is located, performing MEM reading operation MEMModeRD on the MEM unit, and performing recovery writing operation CRSModeWR to restore the MEM unit to a CRS mode;

(5) CRS read operation CRSModeRD is carried out on the target unit, but recovery write operation is not carried out, so that the target unit is converted into an MEM mode, the unit mode record table is updated, and the operation is finished.

2. The hybrid reconfigurable method for CRS Resistive Random Access Memory (RRAM) according to claim 1, wherein the query target unit patterns in the steps (2) and (3) are specifically:

inquiring a unit mode recording table, comparing with a zone bit of a target unit address, and if the zone bit is consistent with the zone bit, determining that the target unit is in an MEM mode; otherwise, the target unit is in CRS mode.

3. The hybrid reconfigurable method for CRS resistive random access memory according to claim 1, wherein the dynamically switching the operating mode of the storage unit to ensure that the most frequently accessed unit is in the MEM mode further comprises:

if each word line only comprises one MEM unit in the cross point array of the CRS resistive random access memory, adopting row-first addressing;

if each bit line contains only one MEM cell, conventional row-first addressing is used.

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