CN109448631B - a display device - Google Patents
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- CN109448631B CN109448631B CN201910070511.3A CN201910070511A CN109448631B CN 109448631 B CN109448631 B CN 109448631B CN 201910070511 A CN201910070511 A CN 201910070511A CN 109448631 B CN109448631 B CN 109448631B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
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- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses multi-purpose point of one kind to use circuit and display device, belongs to field of display technology；Demultiplexing circuitry includes: the first data line of n item, n switching group connecting respectively with the first data line of n item, switch driving circuit, m thread switching control of connection switch driving circuit, compensation drive circuit and m-1 compensating line for connecting compensation drive circuit, and n, m are the integer greater than 1；Gating feed-trough voltage caused by m-1 compensating line respectively closes m-1 non-last bit gating switches compensates, and gating feed-trough voltage caused by last bit gating switch is closed according to circumstances selects uncompensation or uniformly uses common voltage to adjust with offset voltage difference caused by m-1 thermal compensation signal to compensate；It only adds m-1 compensating line i.e. and can reach the uniform effect of the feed-trough voltage for being subject to each column pixel, can solve the bad problem of display caused by gating switch is closed, and circuit space can be saved, reduce compensation bring extra power consumption.
Description
Technical field
The invention belongs to field of display technology, and in particular to a kind of display device.
Background technique
Demultiplexing circuitry (Demux technology) is widely used in display device, it can be by data drive circuit (Source
IC) data voltage exported is passed with the form timesharing of 1:m (such as 1:2,1:3, m are the integer greater than 1, and 1:m is referred to as Mux ratio)
Corresponding the second data line of m item is given, connects the first data line quantity of data drive circuit relative to connection pixel unit
Second data line quantity can at least reduce half, can reduce IC quantity, and then reduce panel design cost and save arrangement space,
The lower frame for reducing panel, makes panel reach the requirement of more narrow frame.
Due to using Demux technology, need between the first data line and corresponding a plurality of second data line using multiple
Thin film transistor (TFT) (TFT) is used as gating switch, and needs to introduce a plurality of thread switching control of control gating switch.Especially for
For TFT using oxide semiconductor (such as indium gallium zinc oxide, abbreviation IGZO), because of the special nature of TFT, in grid and
There can be a biggish parasitic capacitance Cgd(such as Fig. 1 between drain electrode).As shown in Fig. 2, due to above-mentioned parasitic capacitance effect, multichannel
Point between the grid and drain electrode of gating switch in circuit, there are biggish gating parasitic capacitance Ckd.
As shown in figure 3, due to the presence for gating parasitic capacitance Ckd, when switch control signal is in failing edge (by high level
Jump to low level) when, corresponding gating switch shutdown is controlled, the second data line current potential which is connected is gated
The influence of parasitic capacitance Ckd also will appear certain downward jump, which can regard as gating switch shutdown to the second data
Line current potential bring gates feed-trough voltage (Vfeedthrough_CKVoltage), feed-trough voltage (Vfeedthrough) it further include in pixel unit
Pixel feed-trough voltage (the V of thin film transistor (TFT) shutdownfeedthrough_Gk).Since the connection of different lines pixel and Demultiplexing circuitry is closed
System is different, and the meeting that adjacent pixel has is strobed feed-trough voltage influence, and what is had may not be strobed feed-trough voltage influence, Huo Zhexiang
Adjacent pixel by gating feed-trough voltage it is variant, cause display on will appear colour cast, vertical and horizontal striped, flashing etc. show it is bad.
To solve the above problems, Fig. 4 show a kind of Demultiplexing circuitry and corresponding compensation circuit, compensation circuit with open
The equal compensating line of control line quantity is closed, compensating line overlaps with corresponding second data line and forms compensating electric capacity (as shown in Figure 5).
As shown in fig. 6, m compensating line is corresponded with m thread switching control respectively, compensating line and corresponding switch control
On the contrary, switch control si anal waveforms decline, the current potential on the second data line connected to gating switch generates downward line current potential
While pulling, corresponding thermal compensation signal waveform, which rises, pulls up the current potential generation on second data line, makes the second number
According to the current potential stability maintenance of line, it is bad that colour cast, vertical and horizontal striped, flashing etc. occurs in avoidable display device.
However, the above-mentioned Demultiplexing circuitry compensated when Mux ratio is 1:m, needs m compensating line and m benefit
Signal is repaid, biggish panel space can be occupied, and the overall power of circuit is larger.
Summary of the invention
In order to solve the above technical problems, the present invention provides a kind of display device, demultiplexing in display device can solve
The bad problem of picture caused by circuit, and circuit space can be saved, reduce compensation bring extra power consumption.
Technical solution provided by the invention is as follows:
The invention discloses a kind of display devices, the data drive circuit including display panel, connection the first data line of n item
And Demultiplexing circuitry；The display panel includes criss-cross multi-strip scanning line and a plurality of second data line；Second number
It is divided into n the second data line groups according to line, each second data line group includes the second data line of m item；Wherein n, m are whole greater than 1
Number；
The m thread switching control that the Demultiplexing circuitry includes switch driving circuit, connect with switch driving circuit with
And n switching group corresponding with the first data line of n item；Switch driving circuit generates m switching signal and is separately input into m item switch
Control line；
Each switching group includes m gating switch, and m gating switch is corresponding with m thread switching control respectively；It is same
The control terminal of m gating switch in a switching group is separately connected its corresponding thread switching control, and the m in the same switching group
One path terminal of gating switch is connected and is connected with first data line, m gating switch in the same switching group
Another path terminal be respectively connected to m articles in display panel in the second data line group corresponding with first data line
Two data lines；
The display device further include: compensation drive circuit and m-1 compensating line for connecting compensation drive circuit；Compensation is driven
Dynamic circuit generates m-1 thermal compensation signal and is separately input into m-1 compensating line, m-1 compensating line respectively with each the second data
The second data line of m-1 item in line group in addition to the second data line of last bit forms compensating electric capacity in the position overlapped mutually；
Within a high level stage of scanning signal, any thermal compensation signal has a rising edge.
Preferably, the switching signal in addition to last bit switching signal is by thermal compensation signal, and m-1 by thermal compensation signal and m-1
A thermal compensation signal corresponds；
The rising edge of each thermal compensation signal is no earlier than the corresponding failing edge by thermal compensation signal, and each thermal compensation signal is upper
It rises along the failing edge for being not later than the high level stage.
Preferably, the rising edge of thermal compensation signal occurs simultaneously with the corresponding failing edge by thermal compensation signal.
Preferably, the failing edge of last bit switching signal is later than the failing edge in high level stage in the locating period, m-1 compensation
The failing edge of signal was arranged in the low level stage after the high level stage.
Preferably, the failing edge of each thermal compensation signal is no earlier than the failing edge of last bit switching signal in the locating period, and every
The failing edge of a thermal compensation signal is not later than the corresponding failing edge by thermal compensation signal in next period.
Preferably, the failing edge of thermal compensation signal and the failing edge of last bit switching signal occur simultaneously.
Preferably, the failing edge of last bit switching signal is not later than the failing edge in high level stage in the locating period, m-1 benefit
The failing edge for repaying signal and the failing edge of last bit switching signal occur simultaneously.
Preferably, m-1 compensating line is arranged in parallel with m thread switching control.
Compared with prior art, the present invention can bring it is at least one of following the utility model has the advantages that
1, the Demultiplexing circuitry that Mux ratio is 1:m can be compensated by only adding m-1 compensating line, can solve
The bad problem of the display such as colour cast, flashing, vertical and horizontal striped caused by parasitic capacitance is gated in display device；
2, circuit space can be saved, compensation bring extra power consumption is reduced.
Detailed description of the invention
Below by clearly understandable mode, preferred embodiment is described with reference to the drawings, the present invention is given furtherly
It is bright.
Fig. 1 is the schematic diagram of parasitic capacitance between grid and drain electrode in thin-film transistor structure；
Fig. 2 is a kind of structural schematic diagram of Demultiplexing circuitry of the prior art；
Fig. 3 is the waveform diagram of multi-signal in Demultiplexing circuitry shown in Fig. 2；
Fig. 4 is the structural schematic diagram of a kind of Demultiplexing circuitry of the prior art and compensation circuit；
Fig. 5 is the partial structural diagram of compensation circuit shown in Fig. 4；
Fig. 6 is the waveform diagram of multi-signal in Demultiplexing circuitry shown in Fig. 4；
Fig. 7 is a kind of structural schematic diagram of display device of the present invention；
Fig. 8 is a kind of partial structural diagram of display device one embodiment of the present invention；
Fig. 9 is the partial structural diagram of compensation circuit in display device shown in Fig. 8；
Figure 10 is the waveform diagram of multi-signal in a kind of display device one embodiment of the present invention；
Figure 11 is the waveform diagram of multi-signal in a kind of another embodiment of display device of the present invention；
Figure 12 is the waveform diagram of multi-signal in a kind of display device further embodiment of the present invention；
Figure 13 is the waveform diagram of multi-signal in a kind of another embodiment of display device of the present invention.
Specific embodiment
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, Detailed description of the invention will be compareed below
A specific embodiment of the invention.It should be evident that drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing, and obtain other embodiments.
To make simplified form, part related to the present invention is only schematically shown in each figure, they are not represented
Its practical structures as product.In addition, there is identical structure or function in some figures so that simplified form is easy to understand
Component only symbolically depicts one of those, or has only marked one of those.Herein, "one" is not only indicated
" only this ", can also indicate the situation of " more than one ".
As shown in fig. 7, display device of the invention includes display panel, the data-driven electricity for exporting the first data line of n item
Road, Demultiplexing circuitry and compensation circuit.
Display panel includes criss-cross multi-strip scanning line and a plurality of second data line, by scan line and the second data line
Intersect the multiple pixel units limited.Every scan line exports scanning signal to pixel unit, and scanning signal has periodic
High level stage and low level stage.Second data line is divided into n the second data line groups, and each second data line group includes m item
Second data line；Wherein n, m are the integer greater than 1.
Data drive circuit distinguishes output data voltage to Demultiplexing circuitry, demultiplexing by the first data line of n item
The data voltage timesharing that one article of first data line exports is input in display panel corresponding with first data line by circuit
The second data line of m item in two data line groups.
Including thin film transistor (TFT) and the pixel electrode being connect with thin film transistor (TFT) in pixel unit, when input pixel unit
When scanning signal is in the high level stage, thin film transistor (TFT) is opened, and corresponding second data line is electric by data-signal input pixel
Pole.Display device further includes public electrode and liquid crystal layer, and the current potential of pixel electrode is referred to as the current potential of pixel voltage Vp, public electrode
For common voltage Vcom, the rotation of the voltage difference control liquid crystal layer in pixel unit between pixel voltage Vp and common voltage Vcom,
And then control the display of the pixel unit.
Demultiplexing circuitry includes switch driving circuit, the m thread switching control and and n that connect with switch driving circuit
The corresponding n switching group of the first data line of item.
Each switching group includes m gating switch, and gating switch can be N-shaped or p-type thin film transistor, and each film is brilliant
Body Guan Jun includes control terminal, the first path terminal and alternate path end, and below in an example, control terminal is grid, wherein one
A path terminal is source electrode, another path terminal is drain electrode.Below by taking n-type thin film transistor as an example, when giving control terminal high level,
Source electrode and drain electrode is electrically connected by semiconductor layer, and gating switch is in the open state at this time.M gating in each switching group
It switchs corresponding with m thread switching control respectively and corresponding with the second data line that respective switch control line is connected；It is same to open
The control terminal of m gating switch in the group of pass is separately connected its corresponding thread switching control, m gating in the same switching group
First path terminal of switch is connected and is connected with first data line, and the of m gating switch in the same switching group
Two path terminals are respectively connected to the second data of m item in display panel in the second data line group corresponding with first data line
Line.
Switch driving circuit generates m switching signal and is separately input into m thread switching control, and m switching signal is scanning
A rising edge (high level is risen to by low level) is sequentially generated in one high level stage of signal, and in previous switch
After signal generation failing edge (dropping to low level by high level) or simultaneously, the latter switching signal generates rising edge.That is m item
Thread switching control controls m gating switch in each switching group respectively and successively beats within a high level stage of scanning signal
It opens, and only one gating switch is in the open state in same clock switch group.
M gating switch in same switching group is successively closed in a cycle of scanning signal, the last one is claimed to beat
It opens and the gating switch of the last one closing is last bit gating switch, rest switch is non-last bit gating switch, control last bit choosing
The switching signal for opening up pass is last bit switching signal, and the second data line that the alternate path end of last bit gating switch is connected is end
The second data line of position.In a cycle of scanning signal, the failing edge of last bit switching signal may earlier than or be later than scanning letter
Number the high level stage failing edge, the failing edge of last bit switching signal may also be with the decline in the high level stage of scanning signal
Edge occurs simultaneously.
Compensation circuit includes a plurality of compensating line of compensation drive circuit and connection compensation drive circuit, is for Mux ratio
The display device of 1:m, the present invention only need m-1 compensating line.Compensation drive circuit generates m-1 thermal compensation signal and is separately input into m-
1 compensating line, m-1 articles of compensating line respectively with m-1 articles in each second data line group in addition to the second data line of last bit
Two data lines form compensating electric capacity in the position overlapped mutually, which is respectively used to compensate non-last bit gating switch
The m-1 gating parasitic capacitance formed between grid and drain electrode.
Switching signal in addition to last bit switching signal is by thermal compensation signal, and m-1 are believed by thermal compensation signal and m-1 compensation
Number correspond.Within a high level stage of scanning signal, any thermal compensation signal has a rising edge.
For non-last bit gating switch:
When any one non-last bit gating switch is closed, gating parasitic capacitance lead to that non-last bit gating switch connected the
Data voltage waveform decline on two data lines；Due to the film in the scanning signal control pixel unit in the high level stage
Transistor is opened, and then is pulled downward on to the voltage for the pixel electrode that the second data line is connected.Within the high level stage, with
Thermal compensation signal on the corresponding compensating line of above-mentioned second data line has a rising edge, compensating line to pixel voltage Vp to
Upper pulling counteracts gating switch closing and pulls downward on to pixel voltage Vp.
For last bit gating switch:
When the failing edge of last bit switching signal is later than the failing edge in high level stage in the locating period, since last bit gates
While switch is closed, the thin film transistor (TFT) in pixel unit that the second data line of last bit is connected is had been switched off, last bit gating
The closing of switch will not have an impact the pixel voltage Vp in the pixel unit.Therefore, by the failing edge of m-1 thermal compensation signal
It is arranged in the low level stage after the high level stage, makes the failing edge of m-1 thermal compensation signal also not to pixel electricity
Pressure Vp has an impact.
When the failing edge of last bit switching signal is not later than the failing edge in high level stage of scanning signal, since last bit is selected
While opening up pass closing, the thin film transistor (TFT) in pixel unit that the second data line of last bit is connected is not off, last bit
The closing of gating switch can still have an impact the pixel voltage Vp in the pixel unit.The failing edge of m-1 thermal compensation signal with
The failing edge of last bit switching signal occurs simultaneously, and the failing edge of m-1 thermal compensation signal causes the second data line current potential to reduce institute
Offset voltage difference and last bit the gating switch closing of generation cause the second data line current potential to reduce generated gating feedthrough electricity
Press (Vfeedthrough_CK) in the same size, offset voltage difference and gating feed-trough voltage can be united by the adjustment to common voltage Vcom
One compensates.
The present invention can compensate the Demultiplexing circuitry that Mux ratio is 1:m by m-1 compensating line, can solve
The bad problem of the display such as colour cast, flashing, vertical and horizontal striped caused by parasitic capacitance is certainly gated in display device；And in the prior art
On the basis of further save circuit space, reduce compensation bring extra power consumption.
Embodiment 1:
Fig. 8 is the partial structural diagram of display device in one embodiment of the invention, Demultiplexing circuitry in the present embodiment
Mux ratio be 1:3.
By taking the first data line S1 switching group connected and corresponding a plurality of second data line D1, D2, D3 as an example, switching group
Inside include 3 gating switches M1, M2, M3, the first path terminal of 3 gating switches M1, M2, M3 be connected and with the first data line
S1 is connected, and the alternate path end of gating switch M1, M2, M3 are separately connected 3 the second data lines in same second data line group
D1, D2, D3, the control terminal of gating switch M1, M2, M3 are separately connected thread switching control LCK1, LCK2, LCK3, gating switch M1,
Gating parasitic capacitance Ckd1, Ckd2, Ckd3 are generated between the control terminal and alternate path end of M2, M3 respectively
Compensation circuit includes compensation drive circuit and 2 compensating line LCK1 ', LCK2 ', as shown in figure 9, compensating line LCK1 '
At least there is overlapping, overlapping place's generation compensating electric capacity C1 ' with the second data line D1；Compensating line LCK2 ' at least with the second data line
There is overlapping, overlapping place's generation compensating electric capacity C2 ' in D2.
By taking certain one-row pixels unit as an example, scanning signal Gk inputs the row pixel unit and controls film crystalline substance in pixel unit
The opening and closing of body pipe, second data line D1, D2, D3 are separately connected three pixel units p1, p2, p3 of the row.
As a preferred embodiment, scanning signal Gk, Gk+1, switch control signal CK1, CK2, CK3 and compensation
Signal CK1 ', the waveform of CK2 ' are as shown in Figure 10.The rising edge of thermal compensation signal CK1 ' is with corresponding by thermal compensation signal (i.e. switch control
Signal CK1 processed) failing edge be located at the same time, compensating line LCK1 ' closes the pull-up compensation gating switch M1 of pixel voltage Vp1
Close the drop-down to pixel voltage Vp1.The rising edge of thermal compensation signal CK1 ' is with corresponding by thermal compensation signal (i.e. switch control signal
CK2 failing edge) is located at the same time, and compensating line LCK2 ' closes to picture the pull-up compensation gating switch M1 of pixel voltage Vp2
The drop-down of plain voltage Vp2.
Further, the rising edge of thermal compensation signal is not necessarily to and is located at the same time by the failing edge of thermal compensation signal,
Thermal compensation signal slightly postpones also have certain compensation effect.As shown in figure 11, the rising edge of each thermal compensation signal is no earlier than correspondence
The failing edge by thermal compensation signal, and the rising edge of each thermal compensation signal is not later than the decline in high level stage in the locating period
Edge.
Since the opening and closing of gating switch M3 are later than gating switch M1 and M2, gating switch M3 is that last bit gating is opened
It closes.In the present embodiment, the failing edge of last bit switching signal (i.e. switching signal CK3) is later than the high level stage of scanning signal Gk
Failing edge, the closing of gating switch M3 is only to the current potential V of the second data line D3D3 have an impact, without to pixel voltage Vp3
It has an impact, therefore the failing edge of thermal compensation signal CK1 ', CK2 ' is arranged to the low level stage after the high level stage
It is interior.As shown in Figure 10, the feed-trough voltage (V of pixel voltage Vp1, Vp2, Vp3feedthrough) it only include film crystal in pixel unit
Pipe closes generated pixel feed-trough voltage (Vfeedthrough_Gk).
Further, the failing edge of thermal compensation signal is not necessarily to be located at the failing edge of last bit switching signal with for the moment
Between, as shown in figure 12, the failing edge of each thermal compensation signal is no earlier than the failing edge of last bit switching signal in the locating period, and each
The failing edge of thermal compensation signal is not later than the corresponding failing edge by thermal compensation signal in next period.
Embodiment 2:
Embodiment 2 the difference from embodiment 1 is that: the failing edge of last bit switching signal (i.e. switching signal CK3) is not later than
The failing edge in the high level stage of scanning signal Gk.
Scanning signal Gk, Gk+1, switch control signal CK1, CK2, CK3 and thermal compensation signal CK1 ', CK2 ' in embodiment 2
Waveform it is as shown in figure 13.Since the closing of gating switch M3 not only can be to the current potential V of the second data line D3D3 have an impact, also
Pixel voltage Vp3 can be had an impact, while last bit gating switch is closed, thermal compensation signal CK1 ', the failing edge of CK2 ' are same
Shi Fasheng, and thermal compensation signal CK1 ', CK2 ' cause the offset voltage difference of pixel voltage Vp1, Vp2 generation and last bit gating switch to be closed
Close the gating feed-trough voltage (V for causing pixel voltage vp3 to generatefeedthrough_CK) size is consistent with positive negativity, offset voltage difference and
Gating feed-trough voltage can compensate by the way that the adjustment to common voltage Vcom is unified.
As shown in figure 12, the feed-trough voltage (V of pixel voltage Vp1, Vp2, Vp3 of 3 pixel unitsfeedthrough) not only
Generated pixel feed-trough voltage (V is closed including thin film transistor (TFT) in pixel unitfeedthrough_Gk), it further include that gating switch closes
Feed-trough voltage (V is gated caused by closingfeedthrough_CK).
Choosing caused by m-1 compensating line of Demultiplexing circuitry of the invention respectively closes m-1 non-last bit gating switches
Logical feed-trough voltage compensates, last bit gating switch close caused by gating feed-trough voltage according to circumstances select uncompensation or with
The caused offset voltage difference of m-1 thermal compensation signal uniformly uses common voltage Vcom adjustment to compensate；Only add the compensation of m-1 item
Line is that can reach the uniform effect of the feed-trough voltage for being subject to each column pixel, can solve gating switch in Demux technology and closes
Caused colour cast, flashing, vertical and horizontal striped etc. show bad problem, and can save circuit space, reduce compensation bring extra power
Consumption.
It should be noted that the above is only a preferred embodiment of the present invention, but the present invention is not limited to above-mentioned
Detail in embodiment, it is noted that for those skilled in the art, in technology of the invention
In conception range, various improvements and modifications may be made without departing from the principle of the present invention, to technology of the invention
Scheme carries out a variety of equivalents, these are improved, retouching and equivalents also should be regarded as protection scope of the present invention.
Claims (8)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910070511.3A CN109448631B (en) | 2019-01-25 | 2019-01-25 | a display device |
| PCT/CN2019/103415 WO2020151227A1 (en) | 2019-01-25 | 2019-08-29 | Display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910070511.3A CN109448631B (en) | 2019-01-25 | 2019-01-25 | a display device |
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| CN109448631B true CN109448631B (en) | 2019-04-19 |
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| CN109448631B (en) * | 2019-01-25 | 2019-04-19 | 南京中电熊猫平板显示科技有限公司 | a display device |
| CN109884833B (en) * | 2019-05-09 | 2019-09-03 | 南京中电熊猫平板显示科技有限公司 | A kind of Demultiplexing circuitry, liquid crystal display device and pixel compensation method |
| CN110264970A (en) * | 2019-06-14 | 2019-09-20 | 武汉华星光电技术有限公司 | Display panel |
| CN113168803B (en) * | 2019-11-05 | 2022-12-16 | 京东方科技集团股份有限公司 | Driving method, driving device and display device of display panel |
| CN111862814A (en) * | 2020-07-23 | 2020-10-30 | 福建华佳彩有限公司 | Demux display screen |
| TWI729907B (en) * | 2020-08-14 | 2021-06-01 | 凌巨科技股份有限公司 | Display and multiplexer for display |
| CN114550669A (en) * | 2022-03-01 | 2022-05-27 | 福建华佳彩有限公司 | Driving method for compensating Data signal to improve panel ghost |
| CN114530134B (en) * | 2022-03-04 | 2023-08-22 | 广州华星光电半导体显示技术有限公司 | Display panel and display terminal |
| CN115035836A (en) | 2022-06-23 | 2022-09-09 | 广州华星光电半导体显示技术有限公司 | Demultiplexer and its driving method, and display panel with the demultiplexer |
| CN115035873B (en) * | 2022-06-30 | 2023-09-19 | 厦门天马微电子有限公司 | Display panel and display device |
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| CN104112432B (en) * | 2013-04-17 | 2016-10-26 | 瀚宇彩晶股份有限公司 | monitor |
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| KR102284430B1 (en) * | 2014-12-15 | 2021-08-04 | 삼성디스플레이 주식회사 | Display apparatus |
| CN104900201B (en) * | 2015-05-20 | 2017-04-19 | 昆山龙腾光电有限公司 | Liquid crystal display device and common voltage compensating method thereof |
| WO2017010286A1 (en) * | 2015-07-10 | 2017-01-19 | シャープ株式会社 | Pixel circuit, display device, and method for driving same |
| CN105489154B (en) * | 2015-12-31 | 2018-10-23 | 上海天马微电子有限公司 | Display device and driving method thereof |
| CN107301850B (en) * | 2017-07-27 | 2019-10-29 | 南京中电熊猫平板显示科技有限公司 | Demultiplexing circuitry, liquid crystal display device and capacitance compensation method |
| CN109448631B (en) * | 2019-01-25 | 2019-04-19 | 南京中电熊猫平板显示科技有限公司 | a display device |
-
2019
- 2019-01-25 CN CN201910070511.3A patent/CN109448631B/en not_active Expired - Fee Related
- 2019-08-29 WO PCT/CN2019/103415 patent/WO2020151227A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020151227A1 (en) | 2020-07-30 |
| CN109448631A (en) | 2019-03-08 |
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Effective date of registration: 20200902 Address after: No.7 Tianyou Road, Qixia District, Nanjing City, Jiangsu Province Patentee after: NANJING CEC PANDA LCD TECHNOLOGY Co.,Ltd. Address before: Nanjing Crystal Valley Road in Qixia District of Nanjing City Tianyou 210033 Jiangsu province No. 7 Co-patentee before: NANJING CEC PANDA LCD TECHNOLOGY Co.,Ltd. Patentee before: NANJING CEC PANDA FPD TECHNOLOGY Co.,Ltd. Co-patentee before: NANJING HUADONG ELECTRONICS INFORMATION & TECHNOLOGY Co.,Ltd. |
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