CN109446126A - DSP and FPGA high-speed communication system and method based on EMIF bus - Google Patents
DSP and FPGA high-speed communication system and method based on EMIF bus Download PDFInfo
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Abstract
The present invention relates to a kind of DSP based on EMIF bus and FPGA high-speed communication system and method, belong to field of communication technology between DSP and FPGA.A kind of DSP based on EMIF bus disclosed by the invention and FPGA high-speed communication system and method, support is written and read data memory module simultaneously, also data memory module once need not be all written in communication data, only need little data storage resource, realize the high speed and real time communication of DSP and FPGA bi-directional data, it can satisfy the demand of mass data parallel processing, be suitable for low cost low-power consumption digital information processing system.
Description
Technical field
The invention belongs to fields of communication technology between DSP and FPGA, and in particular to a kind of DSP based on EMIF bus with
FPGA high-speed communication system and method.
Background technique
As electronic functionalities are increasingly complicated, with the digital information processing system of DSP+FPGA framework in function, volume
Clear superiority is shown with precision aspect, becomes main flow direction and development trend.EMIF bus communication is used between DSP and FPGA
Scheme, which has, to be designed the advantages such as simple, versatile, hardware cost is low and low in energy consumption and is widely applied.The prior art is used and is based on
After first data are written to dual port RAM in FPGA in EMIF interface and dual port RAM method, DSP passes through EMIF for the number in dual port RAM again
According to reading, encounter following problem when carrying out big data quantity communication, 1) transmitted data amount is bigger, and data transmission delay is longer, shadow
Ring real-time；2) data volume once transmitted is bigger, and required dual port RAM capacity is bigger, expends hardware resource；3) do not increasing
In the case where adding piece external storage, it cannot achieve the big data quantity (the RAM resource more than FPGA) of FPGA parallel processing generation and connect
The high-speed data communication of continuous data flow.
Summary of the invention
(1) technical problems to be solved
The technical problem to be solved by the present invention is how to design a kind of DSP based on EMIF bus and FPGA high-speed communication
System and method realizes mass data between DSP and FPGA in the case where not increasing high-speed bus and FPGA chip external memory
High speed, real-time Transmission.
(2) technical solution
In order to solve the above-mentioned technical problems, the present invention provides a kind of DSP based on EMIF bus and FPGA high-speed communication
System, comprising: 1) the innernal CPU module and EMIF module of DSP, the CPU module inside DSP pass through outside EMIF module accesses
The memory space of the total built-in unit of EMIF；2) EMIF bus；3) local bus inside FPGA, internal logic, lower line number
According to memory module, downlink data receiving module, upstream data memory module and upstream data sending module, configured inside FPGA
Local bus is used to internal logic being mounted to external EMIF bus；The internal logic includes upstream data shape
Morphotype block, downlink data block of state, the downlink data block of state are used for write-in data manipulation and lower line number according to DSP
According to the read data operation of receiving module, downlink data memory module residual memory space size is calculated；The upstream data shape
Morphotype block is used to calculate upstream data according to the read data operation of DSP and the write-in data manipulation of upstream data sending module
Memory module storage size.
Preferably, the EMIF bus is the EMIF bus that data bit width is 32.
Preferably, there is single dual port RAM of 2 data bit widths 32, address space 512 inside FPGA, include a reading
Port and a write port are respectively used to realize the upstream data memory module and downlink data memory module.
The present invention also provides a kind of method for realizing DSP and FPGA high-speed communication using system described in 3, data flow from
Process of the DSP through EMIF bus to FPGA downlink data transmission is as follows:
DSP operation with FPGA operation carries out simultaneously, DSP realization downlink data transmission the specific steps are,
1) downlink data block of state is read, downlink data memory module residual memory space size is obtained, is denoted as a；
If 2) a > 0, i.e., downlink data memory module has residual memory space, then carries out step 3, otherwise return step 1；
3) downlink will send total length of data and be denoted as b, and the data to be sent, length note is written to downlink data memory module
C=b is write, otherwise c=a if b < a for c, write address circulation is incremented by；
4) it updates the remaining data length to be sent and is denoted as b=b-c, if b=0, that is, the data to be sent have been sent
At then terminating, otherwise return step 1；
FPGA operation carries out simultaneously with DSP operation, and FPGA realizes that downlink data transmission operation includes,
1) downlink data memory module writes data, write address, writes enabled connection local bus, for data behaviour to be written
Make；The reading data of downlink data memory module, read enabled connection downlink data receiving module at read address, for reading data behaviour
Make；The write-in data manipulation of downlink data memory module and read data operation can carry out simultaneously；
2) at the same time, data manipulation is written according to DSP in downlink data block of state and downlink data receiving module is read
Data manipulation calculates downlink data memory module residual memory space size；
3) at the same time, downlink data receiving module read address circulation is incremented by, and reads downlink data memory module, the company of generation
Continuous parallel data stream.
Preferably, process of the data flow from FPGA through EMIF bus to DSP transmitting uplink data is as follows:
FPGA operation carries out simultaneously with DSP operation, and FPGA realizes that transmitting uplink data operation includes,
1) upstream data memory module writes data, write address, writes enabled connection upstream data sending module, for being written
Data manipulation；The reading data of upstream data memory module, read enabled connection local bus at read address, are used for read data operation；
The write-in data manipulation of upstream data memory module and read data operation can carry out simultaneously；
2) at the same time, upstream data sending module parallel data stream to be sent, is successively written upstream data
Memory module, write address circulation are incremented by；
3) at the same time, upstream data block of state is according to the read data operation of DSP and upstream data sending module
Data manipulation is written, calculates upstream data memory module storage size；
DSP starts transmitting uplink data operation, carries out simultaneously with FPGA operation, the specific steps are,
1) upstream data block of state is read, upstream data memory module storage size is obtained, is denoted as d；
If 2) d > 0, i.e., upstream data memory module, which has, has used memory space, then carries out step 3, otherwise terminate；
3) data for having used memory space are read from upstream data memory module, length is denoted as e, e=d, read address circulation
It is incremented by；
4) uplink receiving total length of data is updated, f, f=f+e, return step 1 are denoted as.
Preferably, DSP starts transmitting uplink data operation according to the method for interruption.
Preferably, DSP starts transmitting uplink data operation according to the method for inquiry.
(3) beneficial effect
A kind of DSP based on EMIF bus disclosed by the invention and FPGA high-speed communication system and method are supported to data
Memory module is written and read simultaneously, also data memory module once all need not be written in communication data, it is only necessary to less
Data storage resource realizes the high speed and real time communication of DSP and FPGA bi-directional data, can satisfy mass data parallel processing
Demand is suitable for low cost low-power consumption digital information processing system.
Detailed description of the invention
Fig. 1 is system construction drawing designed in method of the invention；
Fig. 2 is the DSP operational flowchart that method of the invention realizes downlink data transmission；
Fig. 3 is the DSP operational flowchart that method of the invention realizes transmitting uplink data.
Specific embodiment
To keep the purpose of the present invention, content and advantage clearer, with reference to the accompanying drawings and examples, to of the invention
Specific embodiment is described in further detail.
As shown in Figure 1, a kind of DSP based on EMIF bus proposed by the present invention and FPGA high-speed communication method are based on one kind
DSP and FPGA high-speed communication system based on EMIF bus realize that the system includes: the innernal CPU module and EMIF mould of 1) DSP
Block；2) EMIF bus；3) local bus inside FPGA, internal logic, downlink data memory module, downlink data receive
Module, upstream data memory module and upstream data sending module.The internal logic include upstream data block of state,
Downlink data block of state, the downlink data block of state are used to be received according to the write-in data manipulation of DSP and downlink data
The read data operation of module calculates downlink data memory module residual memory space size；The upstream data block of state
For calculating upstream data and storing mould according to the read data operation of DSP and the write-in data manipulation of upstream data sending module
Block storage size.
The present invention uses the dsp chip of TI company, the fpga chip of Xilinx company and data bit width for 32 EMIF
Bus.The memory space that CPU module inside DSP passes through the total built-in unit of EMIF outside EMIF module accesses.Match inside FPGA
The local bus set is used to internal logic being mounted to external EMIF bus.There are 2 data bit widths 32 inside FPGA
Position, address space 512 single dual port RAM, include a read port and a write port, be respectively used to realize the upstream data
Memory module and downlink data memory module.
As shown in Fig. 2, data flow is embodied from DSP through EMIF bus to the detailed of FPGA downlink data transmission in the present invention
Process is as follows:
DSP operation with FPGA operation carries out simultaneously, DSP realization downlink data transmission the specific steps are,
1) downlink data block of state is read, downlink data memory module residual memory space size is obtained, is denoted as a；
If 2) a > 0, i.e., downlink data memory module has residual memory space, then carries out step 3, otherwise return step 1；
3) downlink will send total length of data and be denoted as b.The data to be sent, length note is written to downlink data memory module
For c.If b < a, c=b is write, otherwise c=a, write address circulation is incremented by；
4) it updates the remaining data length to be sent and is denoted as b=b-c, if b=0, that is, the data to be sent have been sent
At then terminating, otherwise return step 1.
FPGA operation carries out simultaneously with DSP operation, and FPGA realizes that downlink data transmission operation includes,
1) downlink data memory module writes data, write address, writes enabled connection local bus, for data behaviour to be written
Make；The reading data of downlink data memory module, read enabled connection downlink data receiving module at read address, for reading data behaviour
Make；The write-in data manipulation of downlink data memory module and read data operation can carry out simultaneously；
2) at the same time, data manipulation is written according to DSP in downlink data block of state and downlink data receiving module is read
Data manipulation calculates downlink data memory module residual memory space size；
3) at the same time, downlink data receiving module read address circulation is incremented by, and reads downlink data memory module, the company of generation
Continuous parallel data stream.
In conclusion the present invention, when realizing downlink data transmission, DSP is carrying out write operation to downlink data memory module
While FPGA to downlink data memory module carry out read operation, reduce data residence time in a storage module, improve
The real-times of data.And data processing is flowing water, the downlink data storage for the 2K byte that embodiment uses in FPGA
Module, so that it may realize hundreds of Mbytes of data transmission.
As shown in figure 3, data flow is embodied from FPGA through EMIF bus to the detailed of DSP transmitting uplink data in the present invention
Process is as follows:
FPGA operation carries out simultaneously with DSP operation, and FPGA realizes that transmitting uplink data operation includes,
1) upstream data memory module writes data, write address, writes enabled connection upstream data sending module, for being written
Data manipulation；The reading data of upstream data memory module, read enabled connection local bus at read address, are used for read data operation；
The write-in data manipulation of upstream data memory module and read data operation can carry out simultaneously；
2) at the same time, upstream data sending module parallel data stream to be sent, is successively written upstream data
Memory module, write address circulation are incremented by；
3) at the same time, upstream data block of state is according to the read data operation of DSP and upstream data sending module
Data manipulation is written, calculates upstream data memory module storage size.
DSP starts transmitting uplink data operation using interrupt mode, carries out simultaneously with FPGA operation, the specific steps are,
1) upstream data block of state is read, upstream data memory module storage size is obtained, is denoted as d；
If 2) d > 0, i.e., upstream data memory module, which has, has used memory space, then carries out step 3, otherwise terminate；
3) data for having used memory space are read from upstream data memory module, length is denoted as e, e=d, read address circulation
It is incremented by；
4) uplink receiving total length of data is updated, f, f=f+e, return step 1 are denoted as.
In conclusion FPGA is carrying out upstream data memory module to write behaviour when present invention row data transmission in realization
DSP is carrying out read operation to upstream data memory module while work, reduces data residence time in a storage module, improves
The real-times of data.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, several improvement and deformations can also be made, these improvement and deformations
Also it should be regarded as protection scope of the present invention.
Claims (7)
1. a kind of DSP based on EMIF bus and FPGA high-speed communication system characterized by comprising 1) innernal CPU of DSP
Module and EMIF module, the memory space that the CPU module inside DSP passes through the total built-in unit of EMIF outside EMIF module accesses；
2) EMIF bus；3) local bus inside FPGA, internal logic, downlink data memory module, downlink data receive mould
Block, upstream data memory module and upstream data sending module, the local bus that the inside FPGA configures are used for internal logic mould
Block is mounted in external EMIF bus；The internal logic includes upstream data block of state, downlink data block of state,
The downlink data block of state is used to be grasped according to the write-in data manipulation of DSP and the reading data of downlink data receiving module
Make, calculates downlink data memory module residual memory space size；The upstream data block of state is used for the reading according to DSP
It is big with memory space to calculate upstream data memory module for the write-in data manipulation of data manipulation and upstream data sending module
It is small.
2. the system as claimed in claim 1, which is characterized in that the EMIF bus is that the EMIF that data bit width is 32 is total
Line.
3. the system as claimed in claim 1, which is characterized in that have 2 data bit widths 32, address spaces inside FPGA
512 single dual port RAM, includes a read port and a write port, be respectively used to realize the upstream data memory module and
Downlink data memory module.
4. a kind of method for realizing DSP and FPGA high-speed communication using system described in claims 1 or 22 or 3, feature exist
In process of the data flow from DSP through EMIF bus to FPGA downlink data transmission is as follows:
DSP operation with FPGA operation carries out simultaneously, DSP realization downlink data transmission the specific steps are,
1) downlink data block of state is read, downlink data memory module residual memory space size is obtained, is denoted as a；
If 2) a > 0, i.e., downlink data memory module has residual memory space, then carries out step 3, otherwise return step 1；
3) downlink will send total length of data and be denoted as b, and the data to be sent are written to downlink data memory module, and length is denoted as c,
If b < a, c=b is write, otherwise c=a, write address circulation is incremented by；
4) it updates the remaining data length to be sent and is denoted as b=b-c, if b=0, that is, the data to be sent have been sent completely, then
Terminate, otherwise return step 1；
FPGA operation carries out simultaneously with DSP operation, and FPGA realizes that downlink data transmission operation includes,
1) downlink data memory module writes data, write address, writes enabled connection local bus, for data manipulation to be written；Under
The reading data of row data memory module, read enabled connection downlink data receiving module at read address, are used for read data operation；Under
The write-in data manipulation of row data memory module and read data operation can carry out simultaneously；
2) at the same time, data manipulation is written according to DSP in downlink data block of state and downlink data receiving module reads data
Operation calculates downlink data memory module residual memory space size；
3) at the same time, downlink data receiving module read address circulation is incremented by, and reads downlink data memory module, generates continuous
Parallel data stream.
5. method as claimed in claim 4, which is characterized in that data flow is passed from FPGA through EMIF bus to DSP upstream data
Defeated process is as follows:
FPGA operation carries out simultaneously with DSP operation, and FPGA realizes that transmitting uplink data operation includes,
1) upstream data memory module writes data, write address, writes enabled connection upstream data sending module, for data to be written
Operation；The reading data of upstream data memory module, read enabled connection local bus at read address, are used for read data operation；Uplink
The write-in data manipulation of data memory module and read data operation can carry out simultaneously；
2) upstream data storage is successively written at the same time, upstream data sending module parallel data stream to be sent
Module, write address circulation are incremented by；
3) at the same time, upstream data block of state is according to the read data operation of DSP and the write-in of upstream data sending module
Data manipulation calculates upstream data memory module storage size；
DSP starts transmitting uplink data operation, carries out simultaneously with FPGA operation, the specific steps are,
1) upstream data block of state is read, upstream data memory module storage size is obtained, is denoted as d；
If 2) d > 0, i.e., upstream data memory module, which has, has used memory space, then carries out step 3, otherwise terminate；
3) data for having used memory space are read from upstream data memory module, length is denoted as e, e=d, and read address circulation is incremented by；
4) uplink receiving total length of data is updated, f, f=f+e, return step 1 are denoted as.
6. method as claimed in claim 5, which is characterized in that DSP starts transmitting uplink data according to the method for interruption and operates.
7. method as claimed in claim 5, which is characterized in that DSP starts transmitting uplink data according to the method for inquiry and operates.
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| CN113609042A (en) * | 2021-07-20 | 2021-11-05 | 天津七所精密机电技术有限公司 | System for improving data interaction speed |
| CN113760813A (en) * | 2021-08-30 | 2021-12-07 | 凯迈(洛阳)电子有限公司 | Method for starting and controlling digital signal processor |
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| CN113609042B (en) * | 2021-07-20 | 2024-04-26 | 天津七所精密机电技术有限公司 | System for improving data interaction speed |
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| CN113760813B (en) * | 2021-08-30 | 2024-05-24 | 凯迈(洛阳)电子有限公司 | Method for starting control of digital signal processor |
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