CN109445867A - A kind of data processing system of train network product - Google Patents
A kind of data processing system of train network product Download PDFInfo
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- CN109445867A CN109445867A CN201710761905.4A CN201710761905A CN109445867A CN 109445867 A CN109445867 A CN 109445867A CN 201710761905 A CN201710761905 A CN 201710761905A CN 109445867 A CN109445867 A CN 109445867A
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- 238000012545 processing Methods 0.000 title claims abstract description 12
- 230000015654 memory Effects 0.000 claims abstract description 83
- 238000003860 storage Methods 0.000 claims abstract description 28
- 230000004913 activation Effects 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 19
- 238000013459 approach Methods 0.000 claims description 3
- 238000011161 development Methods 0.000 claims description 3
- 238000012423 maintenance Methods 0.000 abstract description 7
- 230000003137 locomotive effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000006378 damage Effects 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44568—Immediately runnable code
- G06F9/44578—Preparing or optimising for loading
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1417—Boot up procedures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4406—Loading of operating system
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- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Quality & Reliability (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention discloses a kind of data processing system of train network product, the system comprises: first memory is configured to the first starting code of storage and embedded OS；Second memory is configured to storage application data；Third memory, is configured to storage the second starting code, and the second starting code is the backup of the first starting code；Data processor；Switching circuit is configured to enable the data processor accessible first memory and the second memory in the normal mode, and the switching circuit is additionally configured to enable the data processor accessible third memory under error pattern.The system according to the present invention, can system start the corrupted or lost situation of code under activation system, it does not need to return to system and reloaded by designer using emulator, to simplify the updating maintenance operation difficulty of system, reduces updating maintenance cost.
Description
Technical field
The present invention relates to field of track traffic, and in particular to a kind of data processing system of train network product.
Background technique
Flash memory (Flash) is a kind of nonvolatile storage.Compared to hard-disc storage, since flash memory has better stabilization
Property, shock resistance, therefore it is increasingly used in embedded system.Especially, in railway locomotive field, due to railway machine
The running environment (high vibration) of vehicle, Flash are very widely used in the embedded system of railway locomotive product.
In the embedded system of railway locomotive product, Flash both can be used as storage starting code (bootloader) and
The starting Flash (BootFlash) of embedded OS, it is also possible to make storage key configuration parameters and responsible consumer data
Using Flash (AppFlash).And for BootFlash, once the bootloader in BootFlash will by destruction
Cause system that can not start, user can not do any operation at this time.Therefore it needs to return to product into genuine and be thought highly of using emulation
Newly downloaded program.This process needs the long period, waste of manpower cost and reduces user experience.
Summary of the invention
The present invention provides a kind of data processing system of train network product, the system comprises:
First memory is configured to the first starting code of storage and embedded OS；
Second memory is configured to storage application data；
Third memory, is configured to storage the second starting code, and the second starting code is the first starting generation
The backup of code；
Data processor is configured to by running the first starting code or the second starting code starting system
System carries out data processing operation based on the embedded OS and the application data；
Switching circuit, be configured to enable the data processor in the normal mode the accessible first memory with
And the second memory, the switching circuit are additionally configured to enable the data processor accessible described under error pattern
Third memory.
In one embodiment:
The data processor has local bus and at least two choosings；
The switching circuit is configured to enable two pieces of the data processor to be selected in the first memory, described second
The piece of memory and the third memory chooses arbitrary switch.
In one embodiment, the first memory, the second memory and the third memory have identical
Data width.
In one embodiment, the switching circuit is formed using multiplexer and wire jumper.
In one embodiment, the first memory and the second memory are the flash memory with model.
In one embodiment, the first memory, the second memory and the third memory are homologous series
Flash memory, the capacity of the third memory is less than the first memory.
The invention also provides a kind of bare board development approaches for system of the present invention, which comprises
The first memory is programmed using emulator, the first starting code and embedded operation is written
System；
The application data is downloaded into the second memory；
The third memory is written into the second starting code using emulator.
The invention also provides a kind of exploitation adjustment methods for system of the present invention, which comprises
System access serial ports and/or network interface are enabled, the on the first memory is updated by the order that Ethernet loads
The second starting code on one starting code and third memory.
The invention also provides a kind of system start methods for system of the present invention, which is characterized in that the side
Method includes:
The data processor is enabled to read the first starting code activation system in the normal mode；
The second starting code activation system is read in the order data processor of error pattern.
In one embodiment, the second starting code activation system is read in the order processor of error pattern, also
Include:
Start code copies to the first of the first memory for the second of the third memory using copy command
Start code storage location.
The system according to the present invention, can system start the corrupted or lost situation of code under activation system, do not need
System is returned and is reloaded by designer using emulator, to simplify the updating maintenance operation difficulty of system, is dropped
Low updating maintenance cost.
Other feature or advantage of the invention will illustrate in the following description.Also, Partial Feature of the invention or
Advantage will be become apparent by specification, or be appreciated that by implementing the present invention.The purpose of the present invention and part
Advantage can be realized or be obtained by step specifically noted in the specification, claims and drawings.
Detailed description of the invention
Attached drawing is used to provide further understanding of the present invention, and constitutes part of specification, with reality of the invention
It applies example and is used together to explain the present invention, be not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is system structure diagram according to an embodiment of the invention；
Fig. 2 is System on Chip/SoC pin connection schematic diagram according to an embodiment of the invention；
Fig. 3 is switching circuit structural schematic diagram according to an embodiment of the invention.
Specific embodiment
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and examples, implementation personnel of the invention whereby
Can fully understand that how the invention applies technical means to solve technical problems, and reach technical effect realization process and according to
The present invention is embodied according to above-mentioned realization process.As long as each embodiment it should be noted that do not constitute conflict, in the present invention
And each feature in each embodiment can be combined with each other, be formed by technical solution protection scope of the present invention it
It is interior.
In the embedded system of railway locomotive product, especially in train network product, Flash both can be used as storage and open
The starting Flash (BootFlash) of dynamic code (bootloader) and embedded OS, it is also possible to make storage key configuration
Application Flash (AppFlash) of parameter and responsible consumer data.And for BootFlash, once in BootFlash
Bootloader, which will lead to system by destruction, to be started, and user can not do any operation at this time.Therefore it needs to return product
It returns genuine and program is re-downloaded using emulator.This process needs the long period, waste of manpower cost and reduces use
Family experience.
In view of the above-mentioned problems, the invention proposes a kind of data processing systems of train network product.System of the invention
Using redundancy backup scheme, a flash chip is added additional in system, with additional increased flash chip storage one
Cover spare bootloader.It is just sharp when starting Flash generation corrupted data or loss, bootloader mistake therein
With the bootloader activation system in additional increased flash chip.In this way, imitative there is no need to use system return genuine
True device load bootloader saves human cost to enormously simplify updating maintenance operating process, improves user's body
It tests.
Specifically, as shown in Figure 1, in one embodiment, system includes:
Memory 111 is configured to the first starting code of storage and embedded OS；
Memory 112 is configured to storage application data, specifically, application data includes key configuration ginseng
Several and responsible consumer data；
Memory 113, is configured to storage the second starting code, and the second starting code is the backup of the first starting code；
Data processor 120 is configured to be based on by the first starting code of operation or the second starting code activation system
Embedded OS and application data carry out data processing operation；
Switching circuit 130, is configured to enable data processor 120 in normal mode that (error in data does not occur for memory 111
Or loss of data) under accessible memory 111 and memory 112, switching circuit 130 is additionally configured to enable data processor
120 under error pattern accessible memory 113.
In this way, data processor 120 passes through memory 111 when error in data or loss of data do not occur for memory 111
In starting code activation system.When error in data or loss of data occur for memory 111, data processor 120 is by depositing
Starting code activation system in reservoir 113.The system according to the present invention can start the corrupted or lost feelings of code in system
Activation system under condition does not need to return to system and reloaded by designer using emulator, to simplify system
Updating maintenance operation difficulty reduces updating maintenance cost.
Further, in the system of the present invention, in the normal mode, data processor needs at least to call two storages
The data of device.Therefore, in one embodiment, data processor has local bus and at least two choosings.It is corresponding, switching
Circuit configuration is that the piece for enabling two pieces of data processor be selected in three memories chooses arbitrary switch.
As shown in Fig. 2, in one embodiment, FLASH1, FLASH2 and FLASH3 are respectively 3 flash chips, piece
Selecting pin is respectively CS_BOOT1, CS_APP and CS_BOOT2.Data processor (CPU) has two chip select pins, point
It Wei not CS0 and CS1.CS_BOOT1, CS_APP, CS_BOOT2 access the output end of switching circuit, CS0 and CS1 access switching electricity
The input terminal on road.
Data write-in pin (WE) of FLASH1, FLASH2 and FLASH3 and reading data pin (RE) connect respectively
Pin (WE) and reading data pin (RE) is written in the data entered to CPU.The address wire of FLASH1, FLASH2 and FLASH3
And data line is linked into the address wire and data line of CPU respectively.
The first starting code of FLASH1 storage and embedded OS；FLASH2 stores application data；
FLASH3 storage the second starting code.
In the normal mode, switching circuit enables CS0 connect FLASH1 piece CS_BOOT1, CS1 is selected to connect FLASH2 piece and selects CS_APP.
In this way, CPU, which may be selected by FLASH1 or FLASH2, carries out data read-write operation.For example, the starting code by FLASH1 opens
Dynamic system carries out data processing operation by the embedded OS of FLASH1 and the application data of FLASH2.
Under error pattern, switching circuit enables CS0 connect FLASH3 piece CS_BOOT2, CS1 is selected to connect FLASH2 piece and selects CS_
BOOT1.In this way, CPU, which may be selected by FLASH2 or FLASH1, carries out data read-write operation.For example, the starting for passing through FLASH3
The starting code write-in FLASH1 of FLASH3 is repaired the starting code error of FLASH1 by code activation system.
Further, in one embodiment, FLASH1, FLASH2 and FLASH3 data width having the same guarantees CS0
It is identical with the configuration of CS1, it just can guarantee that CS0 and CS1 are arbitrarily switched in three pieces flash chip in this way.
Further, for the ease of carrying out data processing, in one embodiment, FLASH1 and FLASH2 are the two of same model
Piece flash memory, and the enough stored target codes of capacity.
Further, in one embodiment, FLASH3 is the low capacity flash chip with FLASH1, FLASH2 homologous series
(capacity of FLASH3 is less than FLASH1), as long as capacity storage starting code bootloader enough.
Further, in one embodiment, switching circuit is formed using multiplexer and wire jumper.Specifically, real one
It applies in example, using 74CBTLV525PW chip.
Specifically, as shown in figure 3, in one embodiment, D1 is multiplexer.OE is that enabled pin low level is effective,
Multiplexer is kept to enable always after ground connection.Under normal circumstances CS_SB signal be low level, multiplexer 1A, 2A, 3A connection 1B1,
2B1,3B1；When connecting wire jumper X1, CS_SB signal is high level, multiplexer 1A, 2A, 3A connection 1B2,2B2,3B2.In this way may be used
To guarantee when not connecing wire jumper, CS0, which connects FLASH1 piece CS_BOOT1, CS1 is selected to connect FLASH2 piece, selects CS_APP；After connecting wire jumper,
CS0, which connects FLASH3 piece CS_BOOT2, CS1 is selected to connect FLASH2 piece, selects CS_BOOT2.
Further, for system of the invention, the invention also provides a kind of bare board development approaches.Specifically, one
In embodiment, method includes:
First memory is programmed using emulator, the first starting code of write-in and embedded OS；
Application data is downloaded into second memory；
Third memory is written into the second starting code using emulator.
Further, for system of the invention, the invention also provides a kind of exploitation adjustment methods, specifically, one
In embodiment, in the exploitation debugging stage, if necessary to modify the starting code in first memory or second memory
Bootloader enables system access serial ports and/or network interface, updates starting code by the order that Ethernet loads
bootloader.That is, updating the first starting code and/or the third storage on first memory by the order that Ethernet loads
The second starting code on device.
Further, for system of the invention, the invention also provides a kind of system start methods.Specifically, one
In embodiment, data processor is enabled to read the first starting code activation system in the normal mode；It orders data in error pattern
Processor reads the second starting code activation system.Further, under error pattern, when data processor utilizes the second starting
After code activation system, the second starting code copies of third memory are opened to the first of first memory using copy command
Dynamic code storage location.In this manner it is possible to normal activation system.
While it is disclosed that embodiment content as above but described only to facilitate understanding the present invention and adopting
Embodiment is not intended to limit the invention.Method of the present invention can also have other various embodiments.Without departing substantially from
In the case where essence of the present invention, those skilled in the art make various corresponding changes or change in accordance with the present invention
Shape, but these corresponding changes or deformation all should belong to scope of protection of the claims of the invention.
Claims (10)
1. a kind of data processing system of train network product, which is characterized in that the system comprises:
First memory is configured to the first starting code of storage and embedded OS；
Second memory is configured to storage application data；
Third memory, is configured to storage the second starting code, and the second starting code is the first starting code
Backup；
Data processor is configured to by running the first starting code or the second starting code activation system, base
Data processing operation is carried out in the embedded OS and the application data；
Switching circuit is configured to enable the data processor accessible first memory and institute in the normal mode
Second memory is stated, the switching circuit is additionally configured to enable the data processor accessible third under error pattern
Memory.
2. system according to claim 1, it is characterised in that:
The data processor has local bus and at least two choosings；
The switching circuit is configured to that two pieces of the data processor is enabled to be selected in the first memory, second storage
The piece of device and the third memory chooses arbitrary switch.
3. system according to claim 2, which is characterized in that the first memory, the second memory and institute
State third memory data width having the same.
4. system according to claim 2, which is characterized in that the switching circuit uses multiplexer and wire jumper group
At.
5. system according to claim 1, which is characterized in that the first memory is homotype with the second memory
Number flash memory.
6. system according to claim 1, which is characterized in that the first memory, the second memory and institute
The flash memory that third memory is homologous series is stated, the capacity of the third memory is less than the first memory.
7. a kind of bare board development approach for the system as described in any one of claim 1~6, which is characterized in that the side
Method includes:
The first memory is programmed using emulator, the first starting code and embedded operation system is written
System；
The application data is downloaded into the second memory；
The third memory is written into the second starting code using emulator.
8. a kind of exploitation adjustment method for the system as described in any one of claim 1~6, which is characterized in that the side
Method includes:
System access serial ports and/or network interface are enabled, first on the first memory is updated by the order that Ethernet loads and opens
The second starting code on dynamic code and third memory.
9. a kind of system start method for the system as described in any one of claim 1~6, which is characterized in that the side
Method includes:
The data processor is enabled to read the first starting code activation system in the normal mode；
The second starting code activation system is read in the order data processor of error pattern.
10. according to the method described in claim 9, it is characterized in that, reading described the in the order processor of error pattern
Two starting code activation systems, further includes:
The second starting code copies of the third memory are started to the first of the first memory using copy command
Code storage location.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710761905.4A CN109445867A (en) | 2017-08-30 | 2017-08-30 | A kind of data processing system of train network product |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710761905.4A CN109445867A (en) | 2017-08-30 | 2017-08-30 | A kind of data processing system of train network product |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110704114A (en) * | 2019-09-06 | 2020-01-17 | 无锡江南计算技术研究所 | Redundancy-based embedded system |
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| CN102073517A (en) * | 2009-11-23 | 2011-05-25 | 中兴通讯股份有限公司 | Upgrading and backup method and device for embedded system |
| US20160019106A1 (en) * | 2014-07-16 | 2016-01-21 | Dell Products, Lp | Seamless Method for Booting from a Degraded Software Raid Volume on a UEFI System |
| CN106557346A (en) * | 2016-11-24 | 2017-04-05 | 中国科学院国家空间科学中心 | A kind of primary particle inversion resistant star-carried data processing system and method |
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2017
- 2017-08-30 CN CN201710761905.4A patent/CN109445867A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101276297A (en) * | 2008-05-14 | 2008-10-01 | 北京星网锐捷网络技术有限公司 | Processor system, equipment as well as fault handling method |
| CN102073517A (en) * | 2009-11-23 | 2011-05-25 | 中兴通讯股份有限公司 | Upgrading and backup method and device for embedded system |
| US20160019106A1 (en) * | 2014-07-16 | 2016-01-21 | Dell Products, Lp | Seamless Method for Booting from a Degraded Software Raid Volume on a UEFI System |
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| CN110704114A (en) * | 2019-09-06 | 2020-01-17 | 无锡江南计算技术研究所 | Redundancy-based embedded system |
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Application publication date: 20190308 |