CN109428576B - Control system for multiplexing PAD of multi-path IP - Google Patents
Control system for multiplexing PAD of multi-path IP Download PDFInfo
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- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
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Abstract
The invention discloses a control system of a multi-path IP multiplexing PAD, which comprises a plurality of switches and a plurality of voltage selection modules corresponding to the switches one by one. The switch is used for controlling the connection or disconnection between the IP module and the PAD. The voltage selection module provides corresponding control voltage for the control end of the switch according to the working state of the IP module connected with the corresponding switch. The voltage selection module adjusts the voltage amplitude of the corresponding switch control end according to the working state of each IP module, thereby realizing the wide swing output control of the switch and the voltage withstand control of the power failure of the IP module.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a control system for a multi-path IP multiplexing PAD.
Background
With the development of chip production technology and the improvement of integration level, the voltage used in the chip is lower and lower, the chip integration function is more and more, and the input and output interfaces of the chip are more and more; meanwhile, the area of the chip is smaller and smaller, so that the chip area cost is limited by the number of input and output PADs, which is called PAD Limit. PAD is the input and output of the die of the chip.
In order to reduce the production cost and effectively reduce the number of interfaces without reducing the chip integration level and application scenarios, a circuit structure is generated in which a plurality of IP modules (also called IP cores, chinese is an Intellectual Property Core, and refers to a reusable module provided by a certain party and in the form of a logic unit and a chip design) share part of PADs to complete input and output functions, such as the existing structures of common output PADs of LCD and LVDS, and the number of output PADs in two scenarios can be reduced by half by multiplexing output.
At present, with the great improvement of the integration level of the chip, the chip does not meet the requirement of an input/output structure with only two IP multiplexes, but needs more IP multiplexes to input and output, and the purpose of saving the number of PADs to the maximum extent is achieved.
The input and output electrical standards of a plurality of IPs are different, so that the voltage resistance problem of low-voltage device driving is brought, and if the voltage resistance problem is not solved, the service life of a chip is seriously influenced; in addition, the input and output signal amplitude and common mode voltage of some IP are higher, which are close to or even exceed the power supply voltage of the device used in the chip, and how to drive the output with wide swing is also a difficult problem of multiplexing design; the method can not isolate IP loads, directly increases output loads when applied to a single scene, influences the driving output rate of a single IP, optimizes the output rate of the single IP to the maximum extent in the process of multiplexing the IPs, and is also a problem needing comprehensive consideration.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a control system of a multi-path IP multiplexing PAD, a voltage selection module adjusts the voltage amplitude of a corresponding switch control end according to the working state of each IP, and the problem that the system cannot realize wide-swing output and withstand voltage due to different electrical standards of input and output of a plurality of IPs is solved. (2) The bias voltage introduced by the external IP and the power supply voltage input of the IP are automatically isolated and switched through the voltage selection module, and the problem that the service life of an internal switch of the system is shortened due to exceeding the voltage endurance capacity is solved. (3) The control voltage of the wide-swing output switch is controlled by adjusting the output voltage of the voltage selection module through the boosting module, and the problem that a system cannot transmit wide-swing high-common-mode signals is solved. (4) The voltage output with different voltage values is obtained by controlling the voltage one-out-of-multiple unit through the state selection unit, and the problem that the normal transmission of signals cannot be ensured due to the change of the application state of the IP module by the internal switch of the system is solved through the conduction state of the voltage control switch.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a control system of a multi-IP multiplexing PAD comprises a plurality of switches and a plurality of voltage selection modules which are in one-to-one correspondence with each switch. The switch is used for controlling the connection or disconnection between the IP module and the PAD. The voltage selection module provides corresponding control voltage for the control end of the switch according to the working state of the IP module connected with the corresponding switch.
Further, the voltage selection module provides the power voltage VDD for the control terminal of the corresponding switch in a state that the common mode amplitude of the signal transmitted by the IP module does not exceed the limit value. And under the condition that the common mode amplitude of the signals transmitted by the IP module is higher than the limit value, the voltage selection module provides a pull-up voltage Vcm which is larger than the power supply voltage VDD for the control end of the corresponding switch. And under the condition that the IP module has no signal transmission and the corresponding switch has no voltage withstanding risk, the voltage selection module provides a ground voltage GND for the control end of the corresponding switch. And under the condition that the power supply voltage VDD of the IP module is not electrified, the voltage selection module provides a bias voltage Vbias for the control end of the corresponding switch.
Further, the voltage selection module comprises a state selection unit and a voltage one-out-of-multiple unit. The state selection unit is connected with the voltage one-out-of-more unit. The voltage one-out-of-multiple unit is connected with the switch. The state selection unit selects one more unit according to the working state control voltage of the IP module to provide corresponding control voltage for the control end of the corresponding switch.
Further, the state selection unit controls the voltage selection module to provide the power voltage VDD for the control terminal of the corresponding switch in a state that the common mode amplitude of the signal transmitted by the IP module does not exceed the limit value. Under the condition that the IP module has no signal transmission and the corresponding switch has no voltage withstanding risk, the state selection unit controls the voltage selection module to provide the ground voltage GND for the control end of the corresponding switch. And under the condition that the power supply voltage VDD of the IP module is not electrified, the state selection unit controls the voltage selection module to provide the bias voltage Vbias for the control end of the corresponding switch.
Further, the device also comprises a boosting module. The boosting module is connected with the voltage one-out-of-multiple unit. The first output end of the state selection unit is connected with the control end of the boosting module. The boosting module is used as one of input sources of the voltage one-out-of-multiple unit. And under the condition that the common mode amplitude of the signals transmitted by the IP module is higher than the limit value, the state selection unit starts the boosting module, the boosting module generates a level higher than a power supply voltage VDD, and the level acts on the one-out-of-voltage unit so as to pull up the voltage output by the one-out-of-voltage unit.
Furthermore, the voltage one-out-of-multiple unit comprises a voltage switching and isolating part, a ground voltage output isolating switch and a ground voltage switching part. The first input terminal of the voltage switching and isolating unit is connected to the supply voltage VDD, and the second input terminal of the voltage switching and isolating unit is connected to the bias voltage Vbias. The output end of the voltage switching and isolating part is connected with the control end of the switch through a ground voltage output isolating switch. The ground voltage switching part is connected with the control end of the switch. And the second output end of the state selection unit is connected with the control end of the ground voltage output isolating switch. The third output terminal of the state selection unit is connected to the control terminal of the ground voltage switching part.
Further, under the state that the signal common mode amplitude transmitted by the IP module does not exceed the limit value, the state selection unit controls the ground voltage switching part to disconnect from the ground, and controls the ground voltage output isolation switch to conduct, the voltage switching and isolation part provides the power supply voltage VDD for the control end of the corresponding switch, and the voltage switching and isolation part simultaneously isolates the bias voltage Vbias.
Under the condition that the common mode amplitude of the signals transmitted by the IP module is higher than the limit value, the state selection unit controls the ground voltage switching part to disconnect the ground, controls the ground voltage output isolating switch to be connected and controls the boosting module to start; the voltage boosting module pulls up the power supply voltage VDD output by the voltage switching and isolating part to generate a pull-up voltage Vcm larger than the power supply voltage VDD, and the voltage switching and isolating part isolates the bias voltage Vbias at the same time.
In a state that the IP module has no signal transmission and the corresponding switch has no voltage withstand risk, the state selection unit controls (1222) to be turned off and controls the ground voltage switching part to provide the ground voltage GND to the control terminal of the corresponding switch.
In the state that the power supply voltage VDD of the IP module is not electrified, the state selection unit controls the ground voltage switching part to disconnect from the ground, and controls the ground voltage output isolation switch to conduct, the voltage switching and isolation part provides the bias voltage Vbias for the control end of the corresponding switch, and the voltage switching and isolation part isolates the power supply voltage VDD at the same time.
Further, the state selection unit comprises an AND gate, an OR gate, a NOT gate and a buffer. The first state signal En _ state _0 and the second state signal En _ state _1 are transmitted to the first input terminal and the second input terminal of the or gate one by one. The second state signal En _ state _1 is transmitted to the input terminal of the buffer. The first state signal En _ state _0 is transmitted to a first input end of the AND gate; the second state signal En _ state _1 is transmitted to the second input terminal of the and gate through the not gate. The output of the and gate outputs a first control signal EN0 to the boost module. The output end of the or gate outputs a second control signal EN1 to the one-out-of-voltage unit. The output terminal of the not gate outputs a third control signal EN2 to the one-out-of-voltage unit.
Further, the voltage one-out-of-many unit comprises PMOS tubes PM0, PM1, PM2, NMOS tubes NM0, NM1, NM2 and resistors R0 and R1. The source of the NMOS transistor NM0 is connected to the power supply voltage VDD via a resistor R1; the drain electrode of the NMOS tube NM0 is connected with the drain electrode of the PMOS tube PM 2; the gate of the NMOS transistor NM0 is connected to the power supply voltage VDD through resistors R0 and R1 in this order. The input end of the boost module receives a first control signal EN0 of the state selection unit; the output end of the boosting module is connected with the grid electrode of the NMOS tube NM 0. The source electrode of the PMOS pipe PM0 is connected with a bias voltage Vbias; the drain electrode of the PMOS pipe PM0 is connected with the source electrode of the PMOS pipe PM 1; the drain electrode of the PMOS pipe PM1 is connected with the drain electrode of the PMOS pipe PM 2; the grid electrode of the PMOS pipe PM0 is connected with a power supply voltage; the gate of the PMOS transistor PM1 is connected to the power supply voltage VDD via resistors R0 and R1 in this order. The source electrode of the PMOS pipe PM2 is connected with the control end of the switch; the gate of the PMOS transistor PM2 receives the second control signal EN1 of the state selection unit. The source electrode of the PMOS pipe PM2 is also connected with the drain electrode of the NMOS pipe NM 1; the source electrode of the NMOS tube NM1 is connected with the drain electrode of the NMOS tube NM 2; the source of the NMOS tube NM2 is connected with the ground GND; the grid electrode of the NMOS tube NM1 is connected with a power supply voltage VDD; the gate of the NMOS transistor NM2 receives the third control signal EN2 of the state selection unit.
Further, in a state where the IP block has no signal transmission and the corresponding switch has no risk of withstanding voltage, the first state signal En _ state _0=0 and the second state signal En _ state _1= 1. In a state that the common mode amplitude of the signals transmitted by the IP module does not exceed the limit value, the first state signal En _ state _0=0 and the second state signal En _ state _1= 0. In a state that the common mode amplitude of the signals transmitted by the IP module is higher than the limit value, the first state signal En _ state _0=1 and the second state signal En _ state _1= 0.
The invention has the beneficial effects that:
(1) the voltage selection module adjusts the voltage amplitude of the corresponding switch control end according to the working state of each IP module, thereby realizing the wide swing output control of the switch and the voltage withstand control of the power failure of the IP module.
(2) The automatic isolation and switching of bias voltage introduced by an external IP and the power supply voltage input of the IP are realized through the voltage selection module, the voltage-withstanding function under the condition of power failure of the IP is achieved, and the influence of the external bias is isolated under the condition of normal power supply of the IP.
(3) The control voltage of the wide-swing output switch is controlled by adjusting the output voltage of the voltage selection module through the boosting module, so that the wide-swing high-common-mode signal is output through a common switch.
(4) The voltage multi-selection unit is controlled by the state selection unit to obtain voltage outputs with different voltage values, and the state outputs of IP in different application states are obtained by controlling the conduction state of the switch through the voltage, so that the normal transmission of signals is ensured.
Drawings
FIG. 1 is a block diagram of the circuit of the present invention.
Fig. 2 is a schematic diagram of an embodiment of the present invention.
Fig. 3 is a schematic circuit diagram of the voltage selection module 12 of fig. 1.
Wherein the reference numerals of figures 1 to 3 are: control system 1, IP module 2, PAD 3; the device comprises a switch 11, a voltage selection module 12 and a boosting module 13; a state selection unit 121, a voltage one-out-of-multiple unit 122; a voltage switching and isolating unit 1221, a ground voltage output isolating switch 1222, and a ground voltage switching unit 1223.
Detailed Description
The invention is further illustrated below with reference to the figures and examples.
As shown in fig. 1-2, a control system 1 for multiplexing IP PADs includes a boost module 13(Charge pump), a plurality of switches 11, and a plurality of voltage selection modules 12 corresponding to each switch 11.
The first signal transmission end of each switch 11 is respectively connected with a plurality of IP modules 2 one by one; the second signaling terminal of each switch 11 is for common connection to PAD 3. The switch 11 is used to control the on/off between the IP block 2 and the PAD 3. Each voltage selection module 12 is connected to the control terminal of each switch 11 one by one.
The power supply voltages VDD among the IP modules 2 are independent; each IP block 2 shares the same power supply voltage VDD with its corresponding voltage selection block 12.
The main application scenario of the present invention is shown in fig. 1, and by a certain control means, the situation that a plurality of IP modules with different input/output electrical standards multiplex an I/O PAD to perform signal input/output is achieved, and the time division multiplexing requirement that a plurality of IP modules work at different times at the same time is met, or the input/output requirement is configured by the same group of I/O PADs in a plurality of application scenarios of a chip. The IP module can transmit single-ended signals or differential signals. The invention is proved to be feasible when three IPs of LCD, LVDS and MIPI-DPHY multiplex a group of PAD outputs.
The voltage selection module 12 provides a corresponding control voltage for the control end of the switch 11 according to the working state of the IP module 2 connected to the corresponding switch 11:
the voltage selection module 12 provides the power voltage VDD to the control terminal of the corresponding switch 11 in a state that the common mode amplitude of the signal transmitted by the IP module 2 does not exceed a limit value. The limit = VDD — Vth, where VDD is the power supply voltage and Vth is the threshold voltage of the switch 11.
In a state that the common mode amplitude of the signal transmitted by the IP module 2 is higher than the limit value, the voltage boost module 13 boosts the voltage output by the voltage selection module 12, so that the voltage selection module 12 provides the pull-up voltage Vcm, which is greater than the power supply voltage VDD, to the control terminal of the corresponding switch 11.
In a state where the IP block 2 has no signal transmission and its corresponding switch 11 has no risk of withstanding voltage, the voltage selection block 12 supplies the ground voltage GND to the control terminal of the corresponding switch 11. The risk of withstand voltage refers to the risk of damage or reduced lifetime of the device due to an overpressure for a longer time.
In a state where the power supply voltage VDD of the IP block 2 is not powered on, the voltage selection block 12 provides the bias voltage Vbias to the control terminal of the corresponding switch 11. The bias voltage Vbias is provided by the other IP block 2. Vm-1.2 × VDD < Vbias <1.2 VDD.
The switch 11 is mostly implemented by using an NMOS transistor (or a PMOS transistor), when a specific process is selected for production, the process has a requirement on withstand voltage of the NMOS transistor (or the PMOS transistor), and if a device with a power supply voltage of 1.8V is selected under the specific process, the process generally requires that the voltage (Vgs, Vds, Vgd) at any two ends of the MOS transistor does not exceed 1.2 times the power supply voltage (i.e., 1.8 × 1.2= 2.16V), and if the voltage at the two ends exceeds a limit value, the device may be burned. NMOS requires Vgs to turn on for positive voltage and PMOS requires Vgs to turn on for negative voltage. In addition, the Switch 11 needs to be turned on to meet a certain threshold voltage Vth requirement, that is, Vgs and Vgd determined by the gate voltage of the MOS transistor are generally required to be greater than Vth (for example, 0.7V for NMOS and-0.7V for PMOS), so as to ensure effective turn-on of the Switch 11, otherwise, the Switch transistor cannot be effectively turned on, and the signal cannot be normally output through the Switch 11.
The voltage selection modules 12 may share one boost module 13, or one boost module 13 may be respectively allocated to the voltage selection modules 12 with the same requirement, depending on the voltage requirement of the multiplexing IP.
Specifically, the Voltage selection module 12 includes a State selection unit 121(State Control) and a Voltage one-out-of-multiple unit 122(Voltage Mux).
The state selection unit 121 is connected to the one-out-of-voltage unit 122. The voltage one-out-of-multiple unit 122 is connected to the switch 11.
The state selecting unit 121 generates a corresponding control signal according to the operating state of the IP block 2, and the control signal control voltage one-out-of-multiple unit 122 provides a corresponding control voltage Vswitch for the switch 11.
When the common mode amplitude of the signal transmitted by the IP module 2 does not exceed the limit value, the voltage one-out-of-multiple unit 122 outputs the power voltage VDD, and the control switch 11 is normally turned on. At this time, the switch 11 ensures normal transmission of signals between the corresponding IP module 2 and the PAD 3.
When the common mode amplitude of the signal transmitted by the IP block 2 is higher than the limit value, the signal transmitted by the IP block 2 is close to the power supply voltage VDD, and at this time, the power supply voltage VDD cannot ensure the normal conduction of the switch 11, and the voltage one-out-of-multiple unit 122 is required to output the pull-up voltage Vcm higher than the power supply voltage VDD, so as to ensure the normal transmission of the signal between the IP block 2 and the PAD 3.
In a state where the IP block 2 has no signal transmission and the corresponding switch 11 has no risk of withstanding voltage, the voltage one-out-of-multiple unit 122 outputs the ground voltage GND, and controls the switch 11 to be turned off. At this time, the switch 11 isolates the influence of the load of the IP block 2 on the output, and does not increase the load condition of other IP outputs.
In a state where the power supply voltage VDD of the IP block 2 is not powered on, the control voltage of the switch 11 is pulled up to the bias voltage Vbias provided by the other IP block 2 by the voltage one-out-of-multiple unit 122. If the highest signal output voltage of the other IP block 2 exceeds the power supply voltage VDD, the bias voltage Vbias can provide voltage-withstanding protection for the switch 11, and the voltage (Vgs, Vds, Vgd) at any two ends of the switch 11 is protected from exceeding the voltage-withstanding requirement of the power supply voltage VDD of 1.2 times.
Specifically, the switch 11 is an NMOS transistor. The source of switch 11 is connected to PAD 3; the drain electrode of the switch 11 is connected with the IP module 2; the output terminal of the one-out-of-voltage unit 122 is connected to the gate of the switch 11.
More specifically, as shown in fig. 3, the state selection unit 121 includes an and gate, an or gate, a not gate, and a buffer. The state selection unit 121 receives two control signals: a first state signal En _ state _0 and a second state signal En _ state _ 1. The first state signal En _ state _0 and the second state signal En _ state _1 are transmitted to the first input terminal and the second input terminal of the or gate one by one. The second state signal En _ state _1 is transmitted to the input terminal of the buffer. The first state signal En _ state _0 is transmitted to a first input end of the AND gate; the second state signal En _ state _1 is transmitted to the second input terminal of the and gate through the not gate.
The output terminal of the and gate is a first output terminal of the state selection unit 121, and outputs a first control signal EN0 to the voltage boost module 13. The output terminal of the or gate is a second output terminal of the state selection unit 121, and outputs a second control signal EN1 to the one-out-of-voltage unit 122. The output terminal of the not gate is a third output terminal of the state selection unit 121, and outputs a third control signal EN2 to the one-out-of-voltage unit 122.
The two paths of the first state signal En _ state _0 and the second state signal En _ state _1 received by the state selection unit 121 are logically operated to generate a first control signal En0, a second control signal En1, and a third control signal En 2. The 3 control signals respectively control the related switches 11 in the one-out-of-voltage unit 122, so that the control voltage Vswitch output by the one-out-of-voltage unit 122 generates 4 voltages.
Specifically, the voltage one-out-of-multiple unit 122 includes a voltage switching and isolating part 1221, a ground voltage output isolating switch 1222, and a ground voltage switching part 1223.
The booster module 13 is connected to the voltage switching and isolating unit 1221. The voltage switching and isolating part 1221 has a first input terminal connected to the power supply voltage VDD and a second input terminal connected to the bias voltage Vbias. The output terminal of the voltage switching and isolating unit 1221 is connected to the control terminal of the switch 11 through the ground voltage output isolating switch 1222. The ground voltage switching part 1223 is connected to a control terminal of the switch 11. A first output terminal of the state selection unit 121 is connected to a control terminal of the boost module 13. A second output terminal of the state selection unit 121 is connected to a control terminal of the ground voltage output isolation switch 1222. The third output terminal of the state selection unit 121 is connected to the control terminal of the ground voltage switching part 1223. The boost module 13 is used to generate a level higher than the local power voltage VDD, and is used as one of the input sources of the voltage switching and isolating unit 1221, so that the voltage switching and isolating unit 1221 can output a level higher than the local power voltage VDD.
In a state where the common mode amplitude of the signal transmitted by the IP block 2 does not exceed the limit value, the third control signal EN2 of the state selecting unit 121 controls the ground voltage switching unit 1223 to be disconnected from the ground, and the second control signal EN1 of the state selecting unit 121 controls the ground voltage output isolation switch 1222 to be turned on, the voltage switching and isolation unit 1221 supplies the power supply voltage VDD to the control terminal of the corresponding switch 11, and the voltage switching and isolation unit 1221 simultaneously isolates the bias voltage Vbias.
In a state that the common mode amplitude of the signal transmitted by the IP block 2 is higher than the limit value, the signal transmitted by the IP block 2 is close to the power supply voltage VDD, the third control signal EN2 of the state selection unit 121 controls the ground voltage switching part 1223 to be disconnected from the ground, the second control signal EN1 controls the ground voltage output isolation switch 1222 to be turned on, and the first control signal EN0 controls the boosting block 13 to be started; the boosting module 13 boosts the power supply voltage VDD outputted from the voltage switching and isolating unit 1221 to generate a voltage Vcm larger than the power supply voltage VDD, and the voltage switching and isolating unit 1221 isolates the bias voltage Vbias.
In a state where the IP block 2 has no signal transmission and its corresponding switch 11 has no risk of withstanding voltage, the second control signal EN1 of the state selection unit 121 controls the ground voltage output isolation switch 1222 to be turned off, and the third control signal EN2 of the state selection unit 121 controls the ground voltage switching section 1223 to supply the ground voltage GND to the control terminal of the corresponding switch 11.
In a state where the power supply voltage VDD of the IP block 2 is not powered up, the third control signal EN2 of the state selection unit 121 controls the ground voltage switch 1223 to be disconnected from the ground, and the second control signal EN1 of the state selection unit 121 controls the ground voltage output isolation switch 1222 to be turned on, the voltage switching and isolation unit 1221 provides the bias voltage Vbias to the control terminal of the corresponding switch 11, and the voltage switching and isolation unit 1221 simultaneously isolates the power supply voltage VDD.
More specifically, as shown in fig. 3, the voltage switching and isolating unit 1221 includes PMOS transistors PM0, PM1, NMOS transistor NM0, resistors R0, R1; the ground voltage output isolation switch 1222 includes a PMOS transistor PM 2; the ground voltage switching section 1223 includes NMOS transistors NM1 and NM 2.
The source of the NMOS transistor NM0 is connected to the power supply voltage VDD via a resistor R1; the drain electrode of the NMOS tube NM0 is connected with the drain electrode of the PMOS tube PM 2; the gate of the NMOS transistor NM0 is connected to the power supply voltage VDD through resistors R0 and R1 in this order. The input end of the boost module 13 receives the first control signal EN0 of the state selection unit 121; the output end of the boosting module 13 is connected with the gate of the NMOS transistor NM 0. The source electrode of the PMOS pipe PM0 is connected with a bias voltage Vbias; the drain electrode of the PMOS pipe PM0 is connected with the source electrode of the PMOS pipe PM 1; the drain electrode of the PMOS pipe PM1 is connected with the drain electrode of the PMOS pipe PM 2; the grid electrode of the PMOS pipe PM0 is connected with a power supply voltage; the gate of the PMOS transistor PM1 is connected to the power supply voltage VDD via resistors R0 and R1 in this order. The source electrode of the PMOS pipe PM2 is connected with the control end of the switch 11; the gate of the PMOS transistor PM2 receives the second control signal EN1 of the state selecting unit 121. The source electrode of the PMOS pipe PM2 is also connected with the drain electrode of the NMOS pipe NM 1; the source electrode of the NMOS tube NM1 is connected with the drain electrode of the NMOS tube NM 2; the source of the NMOS tube NM2 is connected with the ground GND; the grid electrode of the NMOS tube NM1 is connected with a power supply voltage VDD; the gate of the NMOS transistor NM2 receives the third control signal EN2 of the state selection unit 121.
The working principle is as follows:
the 4 output states of the control voltage Vswitch correspond to four operation scenarios of the IP block 2.
In a state where the common mode amplitude of the signal transmitted by the IP block 2 does not exceed a limit value, the IP block 2 is configured to the state 2. At this time, En _ state _0=0 and the second state signal En _ state _1=0, so the first control signal En0= GND, the second control signal En1= GND, and the third control signal En2= GND. Then Vc = Vm = VDD, NMOS transistor NM0 is turned on, and PMOS transistor PM1 is turned off by the pull-up action of resistors R1 and R0; the source of the PMOS transistor PM2 is also pulled up to VDD; and EN1= GND causes PMOS transistor PM2 to turn on; EN2= GND causes the NMOS tube NM2 to turn off, so that the output voltage Vswitch is pulled to the power supply voltage VDD output, and the switch 11 is normally turned on, ensuring normal transmission of the signal.
In a state where the common mode amplitude of the signal transmitted by the IP block 2 is higher than a limit value, the IP block 2 is configured to a state 3. At this time, En _ state _0=1 and the second state signal En _ state _1=0, so the first control signal En0= VDD, the second control signal En1= VDD, and the third control signal En2= GND. The voltage boost module 13 is turned on, and the voltage boost module 13 outputs a voltage VC =2 × VDD, Vm = VDD + (R1/(R0 + R1)) × VDD > VDD, and at this time, the NMOS transistor NM0 is turned on; the PMOS pipe PM1 is closed; although the gate terminal voltage of the PMOS transistor PM2 is VDD, the source terminal voltage Vm is greater than VDD, so the PMOS transistor PM2 can still be turned on; and the NMOS transistor NM2 is turned off, resulting in the control voltage Vswitch being a voltage Vm greater than the power voltage VDD. At this time, due to the blocking effect of the NMOS transistor NM1, the voltage across any two terminals of the NMOS transistor NM2 does not exceed VDD, and the NMOS transistor NM2 does not generate a voltage withstanding risk.
In a state in which the IP block 2 is not in signal transmission and its corresponding switch 11 is not at risk of withstanding voltage, the IP block 2 is configured to state 1. At this time, En _ state _0=0 and the second state signal En _ state _1=1, so the first control signal En0= GND, the second control signal En1= VDD, and the third control signal En2= VDD. Then Vc = Vm = VDD by the pull-up action of the resistors R1 and R0, at this time, the PMOS transistors PM1 and PM2 are turned off, and the NMOS transistors NM1 and NM2 are turned on, so that the output voltage Vswitch is pulled down to GND, and the switch 11 isolates the load of the IP block 2 from the output, and the load condition of the output of other IP blocks 2 is not aggravated. It is to be understood that in this state, the supply voltage VDD of the IP block 2 is powered up.
In a state where the power supply voltage VDD of the IP block 2 is not powered on, the IP block 2 is configured to the state 4. At this time, in any state of the En _ state _0 and the second state signal En _ state _1, the first control signal En0= GND, the second control signal En1= GND, and the third control signal En2= GND. When the power supply voltage VDD is pulled to 0, VDD = Vc = Vm = GND, at the time, the PMOS transistor PM0 is turned on, the PMOS transistor PM1 is turned on, the NMOS transistor NM1 is turned off, the PMOS transistor PM2 is turned on, the NMOS transistor NM2 is turned off, Vbias voltage is output through the paths of the PMOS transistor PMO, the PMOS transistor PM1 and the PMOS transistor PM2, and the control voltage Vswitch is pulled to the bias voltage Vbias. The Vbias voltage can provide voltage-resistant protection for the switch 11, and the voltage (Vgs, Vds, Vgd) at any two ends of the protection switch 11 does not exceed the voltage-resistant requirement of 1.2 times the power supply voltage.
What has been described above is only a preferred embodiment of the present invention, and the present invention is not limited to the above examples. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the basic concept of the present invention are to be considered as included within the scope of the present invention.
Claims (8)
1. A control system for a multi-IP multiplexed PAD, comprising:
the circuit comprises a plurality of switches (11) and a plurality of voltage selection modules (12) which are in one-to-one correspondence with each switch (11);
the switch (11) is used for controlling the connection or disconnection between the IP module (2) and the PAD (3);
the voltage selection module (12) provides corresponding control voltage for the control end of the switch (11) according to the working state of the IP module (2) connected with the corresponding switch (11);
the voltage selection module (12) comprises a state selection unit (121) and a voltage one-out-of-multiple unit (122);
the state selection unit (121) is connected with the voltage one-out-of-more unit (122);
the voltage one-out-of-multiple unit (122) is connected with the switch (11);
the state selection unit (121) selects one more unit (122) to provide corresponding control voltage for the control end of the corresponding switch (11) according to the working state control voltage of the IP module (2);
the voltage one-out-of-multiple unit (122) comprises a voltage switching and isolating part (1221), a ground voltage output isolating switch (1222) and a ground voltage switching part (1223);
a first input end of the voltage switching and isolating part (1221) is connected with a power supply voltage VDD, and a second input end of the voltage switching and isolating part (1221) is connected with a bias voltage Vbias;
the output end of the voltage switching and isolating part (1221) is connected with the control end of the switch (11) through a ground voltage output isolating switch (1222);
the ground voltage switching part (1223) is connected with the control end of the switch (11);
a second output end of the state selection unit (121) is connected with a control end of the ground voltage output isolating switch (1222);
the third output terminal of the state selection unit (121) is connected to the control terminal of the ground voltage switching unit (1223).
2. The control system for multiplexed IP PAD according to claim 1, wherein:
the voltage selection module (12) provides a power supply voltage VDD for the control end of the corresponding switch (11) under the condition that the common mode amplitude of the signals transmitted by the IP module (2) does not exceed a limit value;
under the condition that the common mode amplitude of the signals transmitted by the IP module (2) is higher than the limit value, the voltage selection module (12) provides a pull-up voltage Vcm which is larger than a power supply voltage VDD for the control end of the corresponding switch (11);
under the condition that the IP module (2) has no signal transmission and the corresponding switch (11) has no voltage withstanding risk, the voltage selection module (12) provides a ground voltage GND for the control end of the corresponding switch (11);
in the state that the power supply voltage VDD of the IP module (2) is not electrified, the voltage selection module (12) provides a bias voltage Vbias for the control end of the corresponding switch (11).
3. The control system for multiplexed IP PAD according to claim 1, wherein:
under the condition that the common mode amplitude of the signals transmitted by the IP module (2) does not exceed a limit value, the state selection unit (121) controls the voltage selection module (12) to provide a power supply voltage VDD for the control end of the corresponding switch (11);
under the condition that the IP module (2) has no signal transmission and the corresponding switch (11) has no voltage withstanding risk, the state selection unit (121) controls the voltage selection module (12) to provide a ground voltage GND for the control end of the corresponding switch (11);
in the state that the power supply voltage VDD of the IP module (2) is not electrified, the state selection unit (121) controls the voltage selection module (12) to provide the bias voltage Vbias for the control end of the corresponding switch (11).
4. The control system for multiplexed IP PAD according to claim 3, wherein:
the device also comprises a boosting module (13);
the boosting module (13) is connected with the voltage one-out-of-multiple unit (122);
a first output end of the state selection unit (121) is connected with a control end of the boosting module (13);
the boosting module (13) is used as one of the input sources of the voltage one-out-of-multiple unit (122);
and in the state that the common mode amplitude of the signals transmitted by the IP module (2) is higher than the limit value, the state selection unit (121) starts the boosting module (13), the boosting module (13) generates a level higher than a power supply voltage VDD, and the level acts on the one-out-of-voltage unit (122), so that the voltage output by the one-out-of-voltage unit (122) is pulled up.
5. The control system for multiplexed IP PAD according to claim 1, wherein:
in the state that the common mode amplitude of signals transmitted by the IP module (2) does not exceed a limit value, the state selection unit (121) controls the ground voltage switching part (1223) to be disconnected from the ground, the state selection unit (121) controls the ground voltage output isolation switch (1222) to be turned on, the voltage switching and isolation part (1221) provides a power supply voltage VDD for the control end of the corresponding switch (11), and the voltage switching and isolation part (1221) simultaneously isolates the bias voltage Vbias;
in the state that the common mode amplitude of the signals transmitted by the IP module (2) is higher than the limit value, the state selection unit (121) controls the ground voltage switching part (1223) to be disconnected with the ground, controls the ground voltage output isolating switch (1222) to be conducted, and controls the boosting module (13) to be started; the boosting module (13) pulls up the power supply voltage VDD output by the voltage switching and isolating part (1221) to generate a pull-up voltage Vcm larger than the power supply voltage VDD, and the voltage switching and isolating part (1221) isolates the bias voltage Vbias at the same time;
in the state that the IP module (2) has no signal transmission and the corresponding switch (11) has no voltage withstanding risk, the state selection unit (121) controls the ground voltage output isolation switch (1222) to be turned off and controls the ground voltage switching part (1223) to provide the ground voltage GND for the control end of the corresponding switch (11);
in the state that the power supply voltage VDD of the IP module (2) is not powered on, the state selection unit (121) controls the ground voltage switching part (1223) to be disconnected from the ground, the state selection unit (121) controls the ground voltage output isolation switch (1222) to be turned on, the voltage switching and isolation part (1221) provides the bias voltage Vbias to the control end of the corresponding switch (11), and the voltage switching and isolation part (1221) simultaneously isolates the power supply voltage VDD.
6. The control system for multiplexed IP PAD according to claim 4, wherein:
the state selection unit (121) comprises an AND gate, an OR gate, a NOT gate and a buffer;
the first state signal En _ state _0 and the second state signal En _ state _1 are transmitted to the first input end and the second input end of the OR gate one by one;
the second state signal En _ state _1 is transmitted to the input end of the buffer;
the first state signal En _ state _0 is transmitted to a first input end of the AND gate; the second state signal En _ state _1 is transmitted to the second input end of the AND gate through the NOT gate;
the output end of the AND gate outputs a first control signal EN0 to the boosting module (13);
the output end of the OR gate outputs a second control signal EN1 to the voltage one-out-of-multiple unit (122);
the second state signal En _ state _1 passes through the register and outputs the third control signal EN 2.
7. The control system for multiplexed IP PAD according to claim 1, wherein:
the voltage one-out-of-many unit (122) comprises PMOS tubes PM0, PM1, PM2, NMOS tubes NM0, NM1, NM2, resistors R0 and R1;
the source of the NMOS transistor NM0 is connected to the power supply voltage VDD via a resistor R1; the drain electrode of the NMOS tube NM0 is connected with the drain electrode of the PMOS tube PM 2; the grid of the NMOS tube NM0 is connected with a power supply voltage VDD through resistors R0 and R1 in sequence;
the input end of the boost module (13) receives a first control signal EN0 of the state selection unit (121); the output end of the boosting module (13) is connected with the grid electrode of the NMOS tube NM 0;
the source electrode of the PMOS pipe PM0 is connected with a bias voltage Vbias; the drain electrode of the PMOS pipe PM0 is connected with the source electrode of the PMOS pipe PM 1; the drain electrode of the PMOS pipe PM1 is connected with the drain electrode of the PMOS pipe PM 2; the grid electrode of the PMOS pipe PM0 is connected with a power supply voltage VDD; the grid electrode of the PMOS pipe PM1 is connected with a power supply voltage VDD through resistors R0 and R1 in sequence;
the source electrode of the PMOS pipe PM2 is connected with the control end of the switch (11); the grid electrode of the PMOS pipe PM2 receives a second control signal EN1 of the state selection unit (121);
the source electrode of the PMOS pipe PM2 is also connected with the drain electrode of the NMOS pipe NM 1; the source electrode of the NMOS tube NM1 is connected with the drain electrode of the NMOS tube NM 2; the source of the NMOS tube NM2 is connected with the ground GND; the grid electrode of the NMOS tube NM1 is connected with a power supply voltage VDD; the gate of the NMOS transistor NM2 receives the third control signal EN2 of the state selection unit (121).
8. The control system for multiplexed IP PAD according to claim 6, wherein:
when the IP module (2) has no signal transmission and the corresponding switch (11) has no voltage-resistant risk, the first state signal En _ state _0 is equal to 0 and the second state signal En _ state _1 is equal to 1;
under the state that the common-mode amplitude of the signals transmitted by the IP module (2) does not exceed the limit value, the first state signal En _ state _0 is 0, and the second state signal En _ state _1 is 0;
and under the condition that the common-mode amplitude of the signals transmitted by the IP module (2) is higher than the limit value, the first state signal En _ state _0 is 1, and the second state signal En _ state _1 is 0.
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