CN109422234A - Test structure and its manufacturing method - Google Patents
Test structure and its manufacturing method Download PDFInfo
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- CN109422234A CN109422234A CN201710778403.2A CN201710778403A CN109422234A CN 109422234 A CN109422234 A CN 109422234A CN 201710778403 A CN201710778403 A CN 201710778403A CN 109422234 A CN109422234 A CN 109422234A
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- 238000012360 testing method Methods 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 235000012431 wafers Nutrition 0.000 claims abstract description 121
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000013078 crystal Substances 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 230000005496 eutectics Effects 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 9
- 150000004767 nitrides Chemical class 0.000 claims description 5
- NCMAYWHYXSWFGB-UHFFFAOYSA-N [Si].[N+][O-] Chemical class [Si].[N+][O-] NCMAYWHYXSWFGB-UHFFFAOYSA-N 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 16
- 239000012774 insulation material Substances 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 6
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 239000011135 tin Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C99/00—Subject matter not provided for in other groups of this subclass
- B81C99/0035—Testing
- B81C99/0045—End test of the packaged device
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0009—Structural features, others than packages, for protecting a device against environmental influences
- B81B7/0012—Protection against reverse engineering, unauthorised use, use in unintended manner, wrong insertion or pin assignment
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/0077—Other packages not provided for in groups B81B7/0035 - B81B7/0074
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00269—Bonding of solid lids or wafers to the substrate
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00333—Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C3/00—Assembling of devices or systems from individually processed components
- B81C3/001—Bonding of two components
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2829—Testing of circuits in sensor or actuator systems
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/63—Connectors not provided for in any of the groups H01L24/10 - H01L24/50 and subgroups; Manufacturing methods related thereto
- H01L24/64—Manufacturing methods
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2201/00—Specific applications of microelectromechanical systems
- B81B2201/02—Sensors
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2201/00—Specific applications of microelectromechanical systems
- B81B2201/02—Sensors
- B81B2201/0292—Sensors not provided for in B81B2201/0207 - B81B2201/0285
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
- G01R31/2812—Checking for open circuits or shorts, e.g. solder bridges; Testing conductivity, resistivity or impedance
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2836—Fault-finding or characterising
- G01R31/2844—Fault-finding or characterising using test interfaces, e.g. adapters, test boxes, switches, PIN drivers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/89—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
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- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Automation & Control Theory (AREA)
- Electromagnetism (AREA)
- Health & Medical Sciences (AREA)
- General Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Micromachines (AREA)
Abstract
This application discloses a kind of test structure and its manufacturing methods, are related to technical field of semiconductors.The described method includes: providing top crystal circle structure, the top crystal circle structure includes: top wafer and multiple first pads for being separated from each other in the bottom of the top wafer；Bottom wafers structure is provided, the bottom wafers structure includes: bottom wafers and multiple second pads being separated from each other at the top of the bottom wafers, and the side of the second pad of at least one of two adjacent second pads has insulating layer；The multiple first pad is bonded by way of eutectic bonding with the multiple second pad, wherein each first pad is bonded with second pad, to form multiple pads.The application can improve the connected problem of the pad after bonding.
Description
Technical field
This application involves technical field of semiconductors more particularly to a kind of test structures and its manufacturing method.
Background technique
Wafer acceptance testing (WAT test) is after wafer completes all making technologies, for the various tests on wafer
The electrical testing that structure is carried out.
The MEMS sensors such as MEMS (MEMS) inertial sensor have the technique of two wafer eutectic bondings.?
There is test structure in the dicing lane of top wafer and bottom wafers, key will be formed after top wafer and bottom wafers eutectic bonding
Then test structure after conjunction can carry out WAT test with the test structure after para-linkage.
However, the inventors of the present application found that when test structure after para-linkage carries out WAT test, WAT test crash
Situation is relatively more.
Summary of the invention
One of the application is designed to provide a kind of test structure and its manufacturing method, the pad after capable of improving bonding
Connected problem, and then the problem of improvement WAT test crash.
According to the one side of the application, a kind of manufacturing method for testing structure is provided, comprising: provide top wafer knot
Structure, the top crystal circle structure include: top wafer and the bottom of the top wafer be separated from each other it is multiple first weldering
Disk；There is provided bottom wafers structure, the bottom wafers structure include: bottom wafers and the top of the bottom wafers to each other
The side of multiple second pads separated, the second pad of at least one of two adjacent second pads has insulating layer；It will
The multiple first pad is bonded by way of eutectic bonding with the multiple second pad, wherein each first pad and one
A second pad bonding, to form multiple pads.
In one embodiment, side has groove with the second pad of insulating layer.
In one embodiment, there is insulating layer on the side wall of the groove.
In one embodiment, the bottom of the groove is higher than the top of the bottom wafers.
In one embodiment, the side of each second pad all has insulating layer；The offer bottom wafers structure
Step includes: to provide the bottom wafers；Bonding pad material layer is formed in the bottom wafers；The bonding pad material layer is carried out
Patterning, to form multiple initial second pads in welding disking area；Insulating layer is formed in the side of initial second pad；It is right
Initial second pad performs etching, to form the groove, to form second pad.
In one embodiment, the side of each second pad all has insulating layer；The offer bottom wafers structure packet
It includes: the bottom wafers is provided；Bonding pad material layer is formed in the bottom wafers；Pattern is carried out to the bonding pad material layer
Change, to form second pad with the groove；On the side of second pad and the side wall of the groove
Form insulating layer.
In one embodiment, the area of the top wafer shared by first pad is less than shared by second pad
The area of the bottom wafers.
In one embodiment, the groove includes the substantially parallel groove of multiple extending directions.
In one embodiment, the material of the insulating layer includes one of the following or a variety of: oxide, the silicon of silicon
The nitrogen oxides of nitride, silicon.
In one embodiment, the pad includes two kinds of metallic elements；Or the pad includes metallic element and partly leads
Element of volume.
In one embodiment, MEMS biography is formed in one in the top wafer and the bottom wafers
Sensor.
According to the another aspect of the application, a kind of test structure is provided, comprising: top wafer；Bottom wafers are located at described
Below the wafer of top；With multiple pads, for connecting the top wafer and the bottom wafers；Wherein, adjacent two welderings
The side of at least one pad in disk has insulating layer.
In one embodiment, side have insulating layer pad in be embedded with the insulating layer separated.
In one embodiment, the bottom for the insulating layer being embedded in pad is higher than the top of the bottom wafers.
In one embodiment, the material of the insulating layer includes one of the following or a variety of: oxide, the silicon of silicon
The nitrogen oxides of nitride, silicon.
In one embodiment, the pad includes two kinds of metallic elements；Or the pad includes metallic element and partly leads
Element of volume.
In one embodiment, MEMS biography is formed in one in the top wafer and the bottom wafers
Sensor.
In the embodiment of the present application, since the side of the second pad of at least one of the second adjacent pad forms insulation
Layer improves WAT test crash accordingly it is possible to prevent pad adjacent in the multiple pads formed after bonding connects together
Problem.
Pass through the detailed description referring to the drawings to the exemplary embodiment of the application, other features, side
Face and its advantage will become apparent.
Detailed description of the invention
Attached drawing forms part of this specification, and which depict the exemplary embodiments of the application, and together with specification
Together for explaining the principle of the application, in the accompanying drawings:
Fig. 1 shows a kind of existing schematic diagram for testing structure；
Fig. 2 is the flow diagram according to the manufacturing method of the test structure of the application one embodiment；
Fig. 3 shows the schematic diagram of the top crystal circle structure according to the application one embodiment；
Fig. 4 shows the schematic diagram of the bottom wafers structure according to the application one embodiment；
Fig. 5 shows the schematic diagram of the test structure according to the application one embodiment；
Fig. 6 A shows the schematic diagram of the bottom wafers structure according to the application another embodiment；
Fig. 6 B shows the schematic diagram of the bottom wafers structure according to the application another embodiment；
Fig. 6 C shows the schematic top plan view for having fluted second pad；
Fig. 7 A- Fig. 7 E shows each rank for forming bottom wafers structure shown in Fig. 6 A according to the application one embodiment
The schematic diagram of section；
Fig. 8 A- Fig. 8 D shows each rank for forming bottom wafers structure shown in Fig. 6 B according to the application one embodiment
The schematic diagram of section；
Fig. 9 shows the schematic diagram of the test structure according to the application another embodiment；
Figure 10 A shows an example of the test result of existing test structure；
Figure 10 B shows an example of the test result of the test structure of the application.
Specific embodiment
The various exemplary embodiments of the application are described in detail now with reference to attached drawing.It should be understood that unless in addition specific
Illustrate, the component and the positioned opposite of step, numerical expression and numerical value otherwise illustrated in these embodiments is not understood that
For the limitation to the application range.
In addition, it should be understood that for ease of description, the size of all parts shown in attached drawing is not necessarily according to reality
The proportionate relationship on border is drawn, such as certain layers of thickness or width can be exaggerated relative to other layers.
The description of exemplary embodiment is merely illustrative below, in any sense all not as to the application and
Its any restrictions applied or used.
Technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail, but suitable
In the case of these technologies, method and apparatus, these technologies, method and apparatus should be considered as a part of this specification.
It should be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined or illustrates in attached drawing, then will not need that it is further discussed in the explanation of subsequent attached drawing.
Inventor has made intensive studies the problem of WAT test crash, discovery: wafer 101 and bottom wafers at top
After 102 bondings, two adjacent pads 103 and 104 can connect together, that is, being barricaded as bridge, as shown in Figure 1.Due to adjacent weldering
Disk is barricaded as bridge, is shorted so as to cause test structure, and then lead to WAT test crash.Accordingly, following solution party is inventors herein proposed
Case.
Fig. 2 is the flow diagram according to the manufacturing method of the test structure of the application one embodiment.Fig. 3-Fig. 5 is shown
According to the schematic diagram in each stage of the manufacturing method of the test structure of the application one embodiment.
It is carried out in detail below with reference to manufacturing method of Fig. 2, Fig. 3-Fig. 5 to the test structure according to the application one embodiment
Explanation.
As shown in Fig. 2, providing top crystal circle structure in step 202.
Fig. 3 shows the schematic diagram of the top crystal circle structure according to the application one embodiment.As shown in figure 3, top is brilliant
Circle structure includes top wafer 301 and multiple first pads 302 being separated from each other in the bottom of top wafer 301 (Fig. 3 signal
Show two to property).Each first pad 302 can be contacted with a connector 303 in top wafer 301.First weldering
The material of disk 302 can be semiconductor, such as germanium etc.；Or it is also possible to metal, such as tin, aluminium, copper etc..
It should be understood that connector 303 shown in Fig. 3 is only schematically, in fact, may include in top wafer 301
Different metal layers can be connected by corresponding connector 303 (such as metal connecting piece) between different metal layers.Separately
Outside, logic circuit, such as the logic circuit being made of devices such as MOS devices be could be formed in top wafer 301.
In step 204, bottom wafers structure is provided.
Fig. 4 shows the schematic diagram of the bottom wafers structure according to the application one embodiment.As shown in figure 4, bottom is brilliant
Justify multiple second pads 402, Mei Ge that structure includes bottom wafers 401 and is separated from each other at the top of bottom wafers 401
Two pads 402 can be contacted with a connector 403 in bottom wafers 401.In two adjacent the second pads 402 at least
The side of one the second pad 402 has insulating layer 404.The material of insulating layer 404 may include one of the following or a variety of:
Oxide (such as the SiO of silicon2), the nitride (such as SiN) of silicon, silicon nitrogen oxides (such as SiON).Second pad 402
Material can be semiconductor, such as germanium etc.；Or it is also possible to metal, such as tin, aluminium, copper etc..
In a kind of situation, the side of two adjacent the second pads 402 can have insulating layer 404, as shown in Figure 4.
In another case, the side of second pad 402 in two adjacent the second pads 402 has insulating layer 404, and it is another
The side of one the second pad 402 can not have insulating layer 404.
In one embodiment, MEMS sensor, such as MEMS inertial sensor be could be formed in bottom wafers 401
Deng.In another embodiment, it could be formed with MEMS sensor in top wafer 301.
In step 206, multiple first pads 302 are bonded by way of eutectic bonding with multiple second pads 402, with
Multiple pads 501 are formed, thus test structure as shown in Figure 5.Later, WAT test can be carried out to test structure.
In bonding, each first pad 302 the second pad 402 corresponding with one is bonded, after bonding two pads
Be formed as a pad 501.Preferably, the pad 501 after bonding is alloy pad.In one embodiment, pad 501 includes
Two kinds of metallic elements.In another embodiment, pad 501 includes metallic element and semiconductor element.Preferably, after bonding
The resistance of pad is less than the resistance of the first pad 302 before bonding, and less than the resistance of the second pad 402.
In above-described embodiment, since the side of second pad 402 of at least one of the second adjacent pad 402 forms
Insulating layer 404, accordingly it is possible to prevent pad adjacent in the multiple pads 501 formed after bonding connects together.
In one embodiment, the area of the shared top wafer 301 of the first pad 302 is less than bottom shared by the second pad 402
The area of portion's wafer 401 prevents from being bonded so that bonding reaction carries out in the region where the second pad 402 as far as possible
When bonding pad material overflowed from top wafer 301, connect together so as to be better protected from the pad 501 that is formed after bonding.
Although, in bonding, bonding pad material can may still overflow, so that key inventors have found that foring insulating layer 404
Adjacent pad 501 after conjunction may still connect together, and inventor also proposed following two further improved sides accordingly
Case.
Fig. 6 A shows the schematic diagram of the bottom wafers structure according to the application another embodiment.With bottom shown in Fig. 4
Crystal circle structure is compared, and is formed with groove 412 in the second pad 402 in bottom wafers structure shown in Fig. 6 A and (is referred to as
Recess).In one embodiment, groove 412 may include the substantially parallel groove of multiple extending directions.In another embodiment
In, groove 412 may include multiple first grooves extended along a first direction and multiple second extended along second direction
Groove, first groove and second groove can intersect intersection.The formation of groove 412 can provide space for bonding technology, to prevent
The only spilling of bonding pad material connects together to be better protected from the pad formed after bonding.
It should be understood that the application is not limited to the specific arrangement mode of groove 412 given above, as long as the second pad 402
In have and for bonding technology provide the groove 412 in space.
In one embodiment, groove 412 extends to the top of bottom wafers 401 namely groove is welded through second
Disk 402；Alternatively, groove can also stop in the second pad 402, so that the bottom of groove 412 is higher than bottom wafers 401
Top, as shown in Figure 6A.Preferably, the bottom of groove 412 is higher than the top of bottom wafers 401, so can be to avoid being formed
The connector 403 under second pad 402 is caused to damage when groove 412.
Fig. 6 B shows the schematic diagram of the bottom wafers structure according to the application another embodiment.With bottom shown in Fig. 6 A
Crystal circle structure is compared, and has insulating layer 601 on the side wall of the groove 412 in bottom wafers structure shown in Fig. 6 B.In a reality
It applies in example, insulating layer 601 can be made only in the lower part of the side wall of groove 412, that is, the top of the side wall of groove 412 can be with
There is no insulating layer 601.The second pad 402 with groove 412 can regard as including multiple strips (be also possible to other shapes,
Here by taking strip as an example) pad, adjacent strip pad separated by groove 412.In bonding process, due to top wafer and bottom
Portion's wafer meeting mutual extrusion, strip pad may topple over, thus the contact of the first pad and the second pad above and below influencing, into
And influence bonding effect.And in the case where the side wall of groove 412 has insulating layer 601, insulating layer 601 can play support and make
With improving bonding effect so as to avoid strip pad from toppling over.
Fig. 6 C shows the schematic top plan view of the second pad 401 with groove 412.Here, for sake of simplicity, illustrating only
Groove 412, and the insulating layer 601 being not shown on 412 side wall of groove.
A generation type of bottom wafers structure shown in Fig. 6 A is introduced below according to Fig. 7 A- Fig. 7 E.
Firstly, providing bottom wafers 401, and bonding pad material layer 402A is formed in bottom wafers 401, as shown in Figure 7 A.
MEMS sensor, connector 403 etc. can be formed in bottom wafers 401.
Later, bonding pad material layer 402A is patterned, in welding disking area (namely region of covering connector 403)
Multiple initial second pad 402B (namely second pad of the prior art) are formed, as shown in Figure 7 B.For example, photoetching can be passed through
Bonding pad material layer 402A is patterned with etching technics.
Next, forming insulating layer 404 in the side of initial second pad 402B.
In one implementation, as seen in figure 7 c, deposition of insulative material layer 404A, insulation material layer 404A cover bottom
The surface of wafer 401 and the surface and side of initial second pad 402B.Later, as illustrated in fig. 7d, it is carved by anisotropic
Etching off is except the insulation material layer 404A on the surface of bottom wafers 401 and the surface of initial second pad 402B, and initial second
Remaining insulation material layer 404A is as insulating layer 404 on the side of pad 402B.
Later, initial second pad 402B is performed etching, to form groove 412, to form the second pad 402, such as
Shown in Fig. 7 E.For example, patterned mask layer, such as photoresist can be formed on initial second pad 402B, to define ditch
The shape of slot；Then, initial second pad 402B is performed etching using mask layer as mask, to form groove 412.
Bottom wafers structure shown in Fig. 6 A can be formed using technique as above, it later, can be by top wafer knot shown in Fig. 3
Structure is bonded with bottom wafers structure shown in Fig. 6 A, to form the test structure similar with Fig. 5.
A generation type of bottom wafers structure shown in Fig. 6 B is introduced below according to Fig. 8 A- Fig. 8 D.
Firstly, providing bottom wafers 401, and bonding pad material layer 402A is formed in bottom wafers 401, as shown in Figure 8 A.
Later, bonding pad material layer 402A is patterned, to form second pad 402 with groove 412, such as Fig. 8 B
It is shown.In the case where the bottom of groove 412 is higher than the top of bottom wafers 402, can similarly be initially formed shown in Fig. 7 B
Then second initial pad 402B performs etching the second initial pad 402B, to form groove 412.In the bottom of groove 412
In the case where top for bottom wafers 402, the second pad with groove 412 can be formed by a photoetching.
Later, insulating layer 404 is formed on the side of the second pad 402 and the side wall of groove 412.
In one implementation, as shown in Figure 8 C, depositing insulating layer material layer 404A in the structure shown in Fig. 8 B, insulation
Material layer 404A covers the surface of bottom wafers 401, the surface of the second pad 402 and side and the bottom and side of groove 412
Wall.Later, as in fig. 8d, the surface of bottom wafers 401 and the surface of the second pad 402 are removed by anisotropic etching
On insulation material layer 404A, remaining insulation material layer 404A is as insulating layer 404, groove on the side of the second pad 402
Remaining insulation material layer 404A is as insulating layer 601 on 412 side wall.It should be noted that in anisotropic etching technique
In, the insulation material layer 404A on the top of the side wall of groove 412 may be removed a part, to be only remained in groove 412
Side wall lower part insulation material layer 404A.It should be appreciated that " top " mentioned herein and " lower part " are only opposite concept, two
The line of demarcation that person does not fix.
Bottom wafers structure shown in Fig. 6 B can be formed using technique as above, it later, can be by top wafer shown in Fig. 3
Structure is bonded with bottom wafers structure shown in Fig. 6 B, to form test structure as shown in Figure 9.
Figure 10 A shows an example of the test result of existing test structure.Figure 10 B shows the test of the application
One example of the test result of structure.Figure 10 A and Figure 10 B show the breakdown between the source electrode and drain electrode of N-type transistor
Voltage.As can be seen from Figure 10A, being connected due to pad adjacent after bonding cause to test structure short circuit, most test results
Deviate normal breakdown voltage value；And can be seen that test result floating very little from 10B, test result is effective.
Based on the manufacturing method of above-mentioned different embodiments, present invention also provides different test structures.
In one embodiment, referring to Fig. 5, testing structure includes top wafer 301, positioned at 301 lower section of top wafer
Bottom wafers 401 and multiple pads 501.Multiple pads 501 are for connecting top wafer 301 and bottom wafers 401.Adjacent
The side of at least one pad 501 in two pads 501 has insulating layer 404.In one embodiment, pad 501 is to close
Gold solder disk.For example, pad 501 may include two kinds of metallic elements.In another example pad 501 may include metallic element and partly lead
Element of volume.
In one embodiment, referring to Fig. 9, side, which has in the pad 501 of insulating layer 404, is embedded with the insulation separated
Layer 601.Preferably, the bottom for the insulating layer 601 being embedded in pad 501 is higher than the top of bottom wafers 401.
So far, the test structure and its manufacturing method according to the embodiment of the present application is described in detail.In order to avoid hiding
The design of the application is covered, some details known in the field are not described, those skilled in the art are as described above, complete
It is complete to can be appreciated how to implement technical solution disclosed herein.In addition, each embodiment that this disclosure is instructed can be certainly
By combining.It should be appreciated by those skilled in the art can carry out a variety of modifications without departing from such as to embodiments illustrated above
Spirit and scope defined in the appended claims.
Claims (17)
1. a kind of manufacturing method for testing structure characterized by comprising
There is provided top crystal circle structure, the top crystal circle structure include: top wafer and the bottom of the top wafer each other
Multiple first pads spaced apart；
There is provided bottom wafers structure, the bottom wafers structure include: bottom wafers and the top of the bottom wafers each other
The side of multiple second pads spaced apart, the second pad of at least one of two adjacent second pads has insulating layer；
The multiple first pad is bonded by way of eutectic bonding with the multiple second pad, wherein each first weldering
Disk is bonded with second pad, to form multiple pads.
2. the method according to claim 1, wherein side has groove with the second pad of insulating layer.
3. according to the method described in claim 2, it is characterized in that, there is insulating layer on the side wall of the groove.
4. according to the method in claim 2 or 3, which is characterized in that the bottom of the groove is higher than the bottom wafers
Top.
5. according to the method described in claim 2, it is characterized in that, the side of each second pad all has insulating layer；
The step of offer bottom wafers structure includes:
The bottom wafers are provided；
Bonding pad material layer is formed in the bottom wafers；
The bonding pad material layer is patterned, to form multiple initial second pads in welding disking area；
Insulating layer is formed in the side of initial second pad；
Initial second pad is performed etching, to form the groove, to form second pad.
6. according to the method described in claim 3, it is characterized in that, the side of each second pad all has insulating layer；
The offer bottom wafers structure includes:
The bottom wafers are provided；
Bonding pad material layer is formed in the bottom wafers；
The bonding pad material layer is patterned, to form second pad with the groove；
Insulating layer is formed on the side of second pad and the side wall of the groove.
7. the method according to claim 1, wherein the area of the top wafer shared by first pad is small
The area of the bottom wafers shared by second pad.
8. according to the method described in claim 2, it is characterized in that, the groove includes the substantially parallel ditch of multiple extending directions
Slot.
9. the method according to claim 1, wherein the material of the insulating layer includes one of the following or more
Kind: the oxide of silicon, the nitride of silicon, silicon nitrogen oxides.
10. the method according to claim 1, wherein
The pad includes two kinds of metallic elements；Or
The pad includes metallic element and semiconductor element.
11. the method according to claim 1, wherein one in the top wafer and the bottom wafers
In be formed with MEMS sensor.
12. a kind of test structure characterized by comprising
Top wafer；
Bottom wafers are located at below the top wafer；With
Multiple pads, for connecting the top wafer and the bottom wafers；
Wherein, the side of at least one pad in two adjacent pads has insulating layer.
13. test structure according to claim 12, which is characterized in that side, which has in the pad of insulating layer, to be embedded with point
The insulating layer separated.
14. test structure according to claim 13, which is characterized in that the bottom for the insulating layer being embedded in pad is higher than institute
State the top of bottom wafers.
15. test structure according to claim 12, which is characterized in that the material of the insulating layer includes one in following
Kind or it is a variety of: the oxide of silicon, the nitride of silicon, silicon nitrogen oxides.
16. test structure according to claim 12, which is characterized in that
The pad includes two kinds of metallic elements；Or
The pad includes metallic element and semiconductor element.
17. test structure according to claim 12, which is characterized in that in the top wafer and the bottom wafers
MEMS sensor is formed in one.
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| US15/995,301 US10600700B2 (en) | 2017-09-01 | 2018-06-01 | Test structure and manufacturing method therefor |
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| CN111413560A (en) * | 2020-03-10 | 2020-07-14 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Wafer bonding quality reliability test structure and reliability test method |
| CN114779508A (en) * | 2022-04-08 | 2022-07-22 | Tcl华星光电技术有限公司 | Display device and manufacturing method thereof, and splicing display device |
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| CN111115555B (en) * | 2019-12-20 | 2023-08-29 | 北京航天控制仪器研究所 | Silicon groove structure for MEMS wafer-level eutectic bonding packaging and preparation method |
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Also Published As
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| CN109422234B (en) | 2021-04-09 |
| US20190074232A1 (en) | 2019-03-07 |
| US10600700B2 (en) | 2020-03-24 |
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