CN109412732B - Method and device for controlling delay jitter of receiving end - Google Patents

Abstract

The invention discloses a method and a device for controlling the delay jitter of a receiving end. Two-pulse signal; every time the first pulse signal arrives and the framing is successful, the memory value that needs to be backed up and the FIFO queue water level are stored in the first register group; every second pulse signal interval and framing When successful, the value in the first register group is stored in the second register group; when a frame loss occurs, the first register group, the second register group and the watermark of the FIFO queue remain unchanged; when the framing is successful When the next first pulse signal arrives, restore the backup memory value and the watermark of the FIFO queue. The invention ensures the stability of the data flow of the receiving end and reduces the delay jitter by using two groups of register groups to back up the storage memory value and the first-in-first-out queue water level.

Description

A method and device for controlling delay jitter at a receiving end

technical field

The present invention relates to the field of communication technologies, and in particular, to a method and device for controlling delay jitter of a receiving end.

Background technique

The rapid growth of data services in recent years has put forward higher requirements for the transport network: large capacity, low cost, fast and flexible service scheduling, strong expansion capability and high reliability. At present, the development of optical fiber transmission network has gone through the following stages: space division multiplexing (Space Division Multiplexing, SDM) stage, time division multiplexing (Time Division Multiplex, TDM) stage and wavelength division multiplexing (Wavelength Division Multiplexing, WDM) stage , the currently used optical fiber transmission system is mainly based on the wavelength division multiplexing system. With the continuous development of communication technology, the current commercial 40G (Gigabit) wavelength division transmission has gradually evolved to 100G, 400G or even higher transmission rates. At the same time, the distance of data transmission is also constantly expanding.

However, with the improvement of the transmission rate and the expansion of the transmission distance, the influence of delay jitter on the quality of optical communication cannot be ignored. In the optical transport network (Optical Transport Network, OTN) system, the delay jitter in the sending link and the receiving link will cause transmission damage of the data signal, which has a negative impact on the reliability and performance of the entire system. At present, the mainstream Digital Signal Processing (DSP) chips in the industry have no special processing for this. In the 100G/400G long-distance transmission service, 100G/400G pass-through service and 100G/400G loopback service, the reliability of the system and the Performance will be affected; for services with special requirements for delay, such as 100GE (Gigabit Ethernet)/400GE services, the requirements cannot be met, which greatly reduces the usage scenarios of 100G/400G DSP chips.

SUMMARY OF THE INVENTION

In order to solve the above technical problems, the present invention provides a method and device for controlling the delay jitter of the receiving end, which can reduce the delay jitter of the receiving end link.

In order to achieve the purpose of the present invention, the technical solutions of the embodiments of the present invention are implemented as follows:

An embodiment of the present invention provides a method for controlling delay jitter at a receiving end, including:

Generating a first pulse signal with a point on the water level line of the FIFO queue at the receiving end as a reference point, the period of the first pulse signal is the same as the period of the water level line of the FIFO queue; generating a second pulse signal, the The second pulse signal is the N frequency-divided signal of the first pulse signal, and N is a natural number greater than or equal to the number of clock cycles required by the receiving end to judge that the data is abnormal;

Every time the first pulse signal or the second pulse signal arrives and the framing is successful, the memory value that needs to be backed up at the receiving end and the water level line of the FIFO queue are stored in the first register group; every second pulse signal When the interval is successful and the framing is successful, the value in the first register group is stored in the second register group;

When a frame loss occurs at the receiving end, keep the first register group, the second register group and the watermarks of the FIFO queue unchanged;

When the first pulse signal arrives after the framing is successful, the memory value backed up by the receiving end and the water level of the FIFO queue are restored according to the register value stored in the second register group.

Further, the successful framing specifically includes: the receiving end performs frame synchronization detection on the received data frame and determines that the frame synchronization of the received data frame is maintained to N1 frame lengths, where N1 is a natural number.

Further, the occurrence of frame loss at the receiving end specifically includes: the receiving end performs frame synchronization detection on the received data frames and judges that the data frames received by consecutive N2 frames are out of synchronization, wherein the N2 is greater than 1. Natural number.

Further, the first pulse signal after the framing is successful is the first first pulse signal after the framing is successful.

Further, the control method further includes: setting the ratio of valid signals in the output buffer data of the FIFO queue according to the data decoding rate of the receiving end and the read data rate of the FIFO queue.

An embodiment of the present invention further provides a control device for receiving end delay jitter, including a first-in-first-out queue, a clock tracking module, a synchronization module, a storage recovery module, a first register group and a second register group, wherein:

A first-in, first-out queue for buffering the data received by the receiving end;

The clock tracking module is used to generate a first pulse signal with a point on the water level line of the FIFO queue at the receiving end as a reference point, and the period of the first pulse signal is the same as the period of the water level line of the FIFO queue; Two-pulse signal, the second pulse signal is the N frequency-divided signal of the first pulse signal, and N is a natural number greater than or equal to the number of clock cycles required by the receiving end to judge data abnormality; the first pulse signal and the second pulse signal Output to the storage recovery module;

The synchronization module is used to perform frame synchronization detection on the received data frame, and output a framing success signal or a frame loss signal to the storage recovery module;

The storage recovery module is used to store the memory value that needs to be backed up at the receiving end and the water level line of the FIFO queue into the first register group every time the first pulse signal or the second pulse signal arrives and the framing is successful; At the interval of the second pulse signal and the framing is successful, the value in the first register group is stored in the second register group; when frame loss occurs, the first register group, the second register group and the first-in first-out queue are kept When the first pulse signal after the successful framing arrives, restore the memory value backed up by the receiving end and the water level of the FIFO queue according to the register value stored in the second register group;

The first register group and the second register group are both used to store the memory value that needs to be backed up at the receiving end and the watermark of the FIFO queue.

Further, when the frame determination by the storage recovery module is successful, the storage recovery module determines that the frame synchronization of the received data frame is maintained to N1 frame lengths, wherein the N1 is a natural number.

Further, when the frame loss occurs, the storage recovery module includes: when the storage recovery module determines that the data frames received in consecutive N2 frames are out of synchronization, wherein the N2 is a natural number greater than 1.

Further, the first pulse signal after the successful framing of the storage recovery module is the first first pulse signal after the successful framing.

Further, the control device also includes a setting module for setting the ratio of the valid signals in the output buffer data of the FIFO according to the data decoding rate of the receiving end and the read data rate of the FIFO queue. .

The technical scheme of the present invention has the following beneficial effects:

The method and device for controlling the delay jitter of the receiving end provided by the present invention use two sets of register groups to pre-store the memory values that need to be backed up and the watermarks of the FIFO queue. The watermark of the first-out queue remains unchanged, and the backed-up memory value and the watermark of the first-in-first-out queue are restored at the reference point after the framing is successful, so that when an abnormality occurs in the receiving end link, the data traffic returns to the last normal operation. The state ensures the stability of data traffic and reduces delay jitter;

Further, by setting the ratio of valid signals in the output buffer data of the FIFO queue, the impact of subsystems with large fluctuations in data traffic on subsequent subsystems is reduced, the uniformity of data enablement is ensured, and data transmission is expanded. application scenarios.

Description of drawings

The accompanying drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the attached image:

1 is a schematic flowchart of a method for controlling delay jitter at a receiving end according to an embodiment of the present invention;

2 is a schematic diagram of the periodic fluctuation of the water level of the first-in-first-out queue (First In First Out, FIFO) of the receiving end in the related art;

3 is a schematic structural diagram of an apparatus for controlling delay jitter at a receiving end according to an embodiment of the present invention;

4 is a schematic diagram of a link structure of a receiving end according to a preferred embodiment of the present invention;

5 is a schematic diagram of the timing control logic of the first register group and the second register group according to the preferred embodiment of the present invention;

6 is a schematic structural diagram of a state machine of a clock tracking module according to a preferred embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a setting module according to a preferred embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, the embodiments in the present application and the features in the embodiments may be arbitrarily combined with each other if there is no conflict.

As shown in Figure 1, a method for controlling the delay jitter of a receiving end according to the present invention includes the following steps:

Step 101: generate a first pulse signal with a point on the water level line of the FIFO queue at the receiving end as a reference point, and the period of the first pulse signal is the same as the period of the water level line of the FIFO queue; generate a second pulse signal , the second pulse signal is the N frequency-divided signal of the first pulse signal, and N is a natural number that is greater than or equal to the number of clock cycles required by the receiving end to judge that the data is abnormal;

It should be noted that the data transmission at the receiving end is transmitted in units of frames. Since the clock frequencies on both sides of the FIFO are inconsistent, as shown in Figure 2, there will be a fixed period of water level fluctuations in the FIFO. A reference point is selected in the periodic water level fluctuation of the FIFO. The reference point can be selected at any time in each cycle, but after the selection, it will not change during the entire transmission process, that is, the period of the reference point and the FIFO water level The fluctuation period is the same.

Step 102: every time the first pulse signal or the second pulse signal arrives and the framing is successful, store the memory value that needs to be backed up at the receiving end and the water level line of the FIFO queue into the first register group; every second When the interval of the pulse signal is successful and the framing is successful, the value in the first register group is stored in the second register group;

Further, the successful framing specifically includes:

The receiving end performs frame synchronization detection on the received data frame and determines that the frame synchronization of the received data frame is maintained to N1 frame lengths, where N1 is a natural number.

Step 103: when a frame loss occurs at the receiving end, keep the first register group, the second register group and the watermarks of the FIFO queue unchanged;

Further, the occurrence of frame loss at the receiving end specifically includes:

The receiving end performs frame synchronization detection on the received data frames and determines that the data frames received in consecutive N2 frames are out of synchronization, wherein the N2 is a natural number greater than 1.

Step 104 : when the first pulse signal arrives after the framing is successful, restore the memory value that needs to be backed up at the receiving end and the watermark of the FIFO queue according to the register value stored in the second register group.

Further, the first pulse signal after the framing is successful is the first first pulse signal after the framing is successful.

Further, the control method also includes:

According to the data decoding rate of the receiving end and the read data rate of the FIFO queue, the ratio of valid signals in the output buffer data of the FIFO queue is set.

As shown in Figure 3, a control device for receiving end delay jitter according to the present invention includes a first-in first-out queue, a clock tracking module, a synchronization module, a storage recovery module, a first register group and a second register group, wherein:

A first-in, first-out queue for buffering the data received by the receiving end;

The clock tracking module is used to generate a first pulse signal with a point on the water level line of the FIFO queue at the receiving end as a reference point, and the period of the first pulse signal is the same as the period of the water level line of the FIFO queue; Two-pulse signal, the second pulse signal is the N frequency-divided signal of the first pulse signal, and N is a natural number greater than or equal to the number of clock cycles required by the receiving end to judge data abnormality; the first pulse signal and the second pulse signal Output to the storage recovery module;

The synchronization module is used for framing the received data frame, and outputting a framing success signal or a frame loss signal to the storage recovery module;

The storage recovery module is used to store the memory value that needs to be backed up at the receiving end and the water level line of the FIFO queue into the first register group every time the first pulse signal or the second pulse signal arrives and the framing is successful; At the interval of the second pulse signal and the framing is successful, the value in the first register group is stored in the second register group; when frame loss occurs, the first register group, the second register group and the first-in first-out queue are kept When the first pulse signal after the successful framing arrives, restore the memory value backed up by the receiving end and the water level of the FIFO queue according to the register value stored in the second register group;

The first register group and the second register group are both used to store the memory value that needs to be backed up at the receiving end and the watermark of the FIFO queue.

Further, when the frame determination by the storage recovery module is successful, the storage recovery module determines that the frame synchronization of the received data frame is maintained to N1 frame lengths, wherein the N1 is a natural number.

Further, when the frame loss occurs, the storage recovery module includes: when the storage recovery module determines that the data frames received in consecutive N2 frames are out of synchronization, wherein the N2 is a natural number greater than 1.

Further, the first pulse signal after the successful framing of the storage recovery module is the first first pulse signal after the successful framing.

Further, the control device further includes a setting module for setting the ratio of valid signals in the output buffer data of the FIFO queue according to the data decoding rate of the receiving end and the read data rate of the FIFO queue.

The embodiment of the present invention also provides a preferred embodiment to further explain the present invention, but it is worth noting that the preferred embodiment is only for better describing the present invention, and does not constitute an improper limitation of the present invention.

As shown in Figure 4, after the fiber data enters the receiving end link, some damages caused by the fiber are eliminated through the data preprocessing subsystem, and then the data enters the synchronization (SYN) module for data deframing and data synchronization; the synchronized data After the decoding module, Turbo Product Code Decoder (TPCD) is performed; the decoded data enters the interface conversion and framing module for interface conversion and data framing in another format; the data after the framing passes through The Reed-solomon (RS) encoding module performs forward error correction channel encoding and then enters the data distribution and scrambling module, and then passes through the First Input First Output (FIFO) and then passes through the serializer/deserializer. (Serializer/Deserializer, SerDes) interface output.

In the process of data transmission, the Clock and Reset Management module (CRM) extracts the water level information of the FIFO and determines the speed of the data rate after smoothing, so as to control the entire data flow, adjust the clock deviation, and reduce the clock delay. .

A method for controlling the delay jitter of a receiving end according to the present invention includes the following steps:

Step 401: Select a reference point on the output water level line of the FIFO queue, generate a pulse signal pr_start1, the period is the same as the output water level period of the FIFO; generate the N frequency division signal pr_start2 of pr_start1, and the N is greater than or equal to judgment The natural number of clock cycles required for data exception plus 1;

It should be noted that a pulse signal pr_start1 is generated at the reference point of each cycle, and it is assumed that the time for judging abnormal data is N.M data cycles (N is the integer part, M is the fractional part), in order to prevent abnormal data from entering the first In the two registers, the frequency division signal pr_start2 of pr_start1 is generated, pr_start2>=pr_start1*N+1, that is, the frequency division is at least N+1.

Step 402: at the moment of pr_start1, store all the register values required to restore the current state into the first register group; when the framing is successful, that is, the frame out-of-frame (Out Of Frame, OOF) signal OOF=0, (the OOF signal is data; The flag of abnormal occurrence) is kept until the first pr_start1 moment after N1 frame length, and the key status register value and FIFO water level in the first register group are loaded into the second register group;

As shown in Figure 5, the update time interval between the first register group and the second register group is the distance between two pr_start2s, and this time interval can ensure that the data when the SYN is abnormal will not be written to the optical conversion unit at all ( Optical Transform Unit, OTU) FIFO. When the system is working normally, the key status register values (all registers required by the system to restore the current status) and the water level of the OTU FIFO are stored in the first register group. The first register group and the second register group two groups of registers form a shift register, pr_start2&crm_work_en& (OOF==0) is connected to the enable terminal of the first register group, wherein pr_start2 is the N frequency division signal of pr_start1, and crm_work_en is the clock tracking module The work enable signal, OOF is the frame out-of-sync signal, pr_start2&crm_work_en&(OOF==0)&flag is connected to the enable terminal of the second register group, wherein, the flag signal value is: when pr_start2&crm_work_en&(OOF==0), flag =1; when 00f=1, flag=0, it should be noted that this is sequential logic, not combinational logic, and there will be an enable cycle delay in sequential logic.

Step 403: when each pr_start2 pulse signal arrives and the framing is successful, refresh the value of the first register group; every pr_start2 pulse signal interval and when the framing is successful, refresh the value of the second register group according to the value of the first register group ;

Step 404: when the N2 frame OOF occurs continuously, keep the FIFO water level;

Step 405: After the framing is successful and OOF=0 is maintained to N1 frame lengths, the scene is restored according to the key status register value in the second register group and the FIFO water level at the first pr_start1 moment.

As shown in Figure 6, the clock tracking module does not work when the power is turned on, the OTU FIFO remains half full, the FIFO does not read or write, and the SerDes interface sends Pseudo-Random Binary Sequence (PRBS) data; After the frame is successful, OOF=0 is maintained to the first pr_start1 time after N1 frame length, and the key status register value is loaded into the second register group, the clock recovery and the OTU FIFO work normally, and the SerDes interface sends the data in the OTU FIFO at this time;

pr_start2&crm_work_en&(OOF==0)==1 refresh the first register group normally and pr_start2&crm_work_en&(OOF==0)&flag==1 refresh the second register group normally, the data of the second register group is the reference obtained from the first register group The key status register value and FIFO water level at the point time, only continuous refresh can ensure that the second register group always stores the key status register value and FIFO water level at the latest reference point in the normal state of the data;

When continuous N2 frames of OOF occur, the clock tracking module is held, and the FIFO water level is held. At this time, the SerDes interface sends PRBS, and when the synchronization module is successfully framed, OOF=0 is held until the first pr_start1 after N1 frame length. The second register group, the clock recovery and the OTU FIFO work normally, and the SerDes interface transmits the data in the OTU FIFO at this time.

It should be noted that because each system defines data exceptions differently, for example, some systems define data exceptions as 3 OOFs as data exceptions, and some systems define data exceptions as 5 OOFs as data exceptions. The N2 here can be configured online. It is understood that when the system experiences N2 OOFs, we think that the data of the system is abnormal, and start the clock tracking module to maintain the current state to prevent the system from being greatly deviated by the abnormal data band when the data is abnormal.

Further, as shown in FIG. 7 , the present invention further includes a setting module, the setting module is located between the decoding module and the FIFO queue, the purpose of which is to further reduce data delay and improve data control accuracy. The data decoded by TPC is buffered by the FIFO, and the buffered data is read uniformly according to the control of the setting module. The setting module sets the numerator N and the denominator M, where the numerator N is the amount of valid data in the FIFO queue, and the denominator M is the amount of buffered data in the FIFO queue, so that the data is output evenly. For example, there are 75 valid enables in 100 clock cycles, then the number of invalid enables is 25, so N can be configured as 75, and M can be configured as 100. In fact, in this case, N and M are not coprime, and can be simplified to N=3 and M=4. After the configuration is completed, the module will output every 3 valid signals followed by an invalid signal, and then continue with 3 valid signals, an invalid signal... . For the data of the abnormal frame, this module only discards the data and does not add the data. The discarded data can be calculated according to the data decoding rate of the receiving end and the read data rate of the FIFO queue, and the calculated discarded data can be completed by configurable or fixed padding data. In the data transmission process, there are normal data, abnormal data, and normal data. Through the processing of the present invention, the average water level difference between normal data and normal data can only differ by a few clock cycles.

The method and device for controlling the delay jitter of the receiving end provided by the present invention use two sets of register groups to pre-store the memory values that need to be backed up and the watermarks of the FIFO queue. The watermark of the first-out queue remains unchanged, and the backed-up memory value and the watermark of the first-in-first-out queue are restored at the reference point after the framing is successful, so that when an abnormality occurs in the receiving end link, the data traffic returns to the last normal operation. The state ensures the stability of data traffic and reduces delay jitter;

Further, by setting the ratio of valid signals in the output buffer data of the FIFO queue, the impact of subsystems with large fluctuations in data traffic on subsequent subsystems is reduced, the uniformity of data enablement is ensured, and data transmission is expanded. application scenarios.

Those skilled in the art can understand that all or part of the steps in the above method can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a magnetic disk or an optical disk. Optionally, all or part of the steps in the above embodiments may also be implemented by using one or more integrated circuits. Correspondingly, each module/unit in the above embodiments may be implemented in the form of hardware, or may be implemented in the form of software function modules. form realization. The present invention is not limited to any particular form of combination of hardware and software.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (10)

1. A method for controlling delay jitter of a receiving end is characterized by comprising the following steps:

generating a first pulse signal by taking one point on a water line of a first-in first-out queue of a receiving end as a reference point, wherein the period of the first pulse signal is the same as that of the water line of the first-in first-out queue; generating a second pulse signal, wherein the second pulse signal is an N frequency division signal of the first pulse signal, and N is a natural number which is greater than or equal to the sum of 1 and the number of clock cycles required by the receiving end for judging data abnormity;

when the first pulse signal or the second pulse signal arrives and the framing is successful, storing a memory value required to be backed up by a receiving end and a water level line of a first-in first-out queue into a first register group; storing the value in the first register group into the second register group every interval of the second pulse signal and when the framing is successful;

when the frame loss occurs at the receiving end, the water level lines of the first register group, the second register group and the first-in first-out queue are kept unchanged;

and when the first pulse signal after the successful framing arrives, restoring the memory value backed up by the receiving end and the water level line of the first-in first-out queue according to the register value stored by the second register group.

2. The control method according to claim 1, wherein the successful framing specifically comprises: and the receiving end carries out frame synchronization detection on the received data frame and judges that the frame synchronization of the received data frame is kept to be N1 frame lengths, wherein N1 is a natural number.

3. The control method according to claim 1, wherein the occurrence of the lost frame at the receiving end specifically includes: and the receiving end carries out frame synchronization detection on the received data frames and judges that the data frames received by continuous N2 frames are out of synchronization, wherein N2 is a natural number greater than 1.

4. The control method according to claim 1, wherein the first pulse signal after the framing success is a first one of the first pulse signals after the framing success.

5. The control method according to claim 1, characterized by further comprising: and setting the proportion of effective signals in the output buffer data of the first-in first-out queue according to the data decoding rate of a receiving end and the data reading rate of the first-in first-out queue.

6. The control device for receiving end delay jitter is characterized by comprising a first-in first-out queue, a clock tracking module, a synchronization module, a storage recovery module, a first register group and a second register group, wherein:

the first-in first-out queue is used for caching the data received by the receiving end;

the clock tracking module is used for generating a first pulse signal by taking one point on a water line of a first-in first-out queue of a receiving end as a reference point, and the period of the first pulse signal is the same as that of the water line of the first-in first-out queue; generating a second pulse signal, wherein the second pulse signal is an N frequency division signal of the first pulse signal, and N is a natural number which is greater than or equal to the sum of 1 and the number of clock cycles required by the receiving end for judging data abnormity; outputting the first pulse signal and the second pulse signal to a storage recovery module;

the synchronization module is used for carrying out frame synchronization detection on the received data frame and outputting a framing success signal or a frame missing signal to the storage recovery module;

the storage recovery module is used for storing a memory value required to be backed up by the receiving end and a water level line of the first-in first-out queue into the first register group when the first pulse signal or the second pulse signal arrives and the framing is successful; storing the value in the first register group into the second register group every interval of the second pulse signal and when the framing is successful; when the frame loss occurs, the water level lines of the first register group, the second register group and the first-in first-out queue are kept unchanged; when the first pulse signal after the successful framing arrives, restoring a memory value backed up by a receiving end and a water level line of a first-in first-out queue according to a register value stored by a second register group;

the first register group and the second register group are used for storing memory values to be backed up by the receiving end and the water level line of the first-in first-out queue.

7. The control device of claim 6, wherein the storage recovery module when framing is successful comprises: the storage recovery module judges that the frame synchronization of the received data frames is kept to be N1 frames, wherein N1 is a natural number.

8. The control device of claim 6, wherein the storage recovery module, when a lost frame occurs, comprises: and the storage recovery module judges that the data frame frames received by continuous N2 frames are out of step, wherein N2 is a natural number greater than 1.

9. The control device according to claim 6, wherein the first pulse signal of the storage recovery module after the framing is successful is the first pulse signal after the framing is successful.

10. The control device of claim 6, further comprising a setting module for setting a ratio of valid signals in the output buffer data of the fifo queue according to a data decoding rate of a receiving end and a data reading rate of the fifo queue.

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