CN109411545A - A kind of thin film transistor (TFT) and its manufacturing method - Google Patents
A kind of thin film transistor (TFT) and its manufacturing method Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 196
- 238000002955 isolation Methods 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims description 16
- 239000010410 layer Substances 0.000 description 328
- 238000000926 separation method Methods 0.000 description 83
- 239000002184 metal Substances 0.000 description 22
- 229910052751 metal Inorganic materials 0.000 description 22
- 238000010586 diagram Methods 0.000 description 16
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 238000009413 insulation Methods 0.000 description 6
- 239000011241 protective layer Substances 0.000 description 6
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- 229910001868 water Inorganic materials 0.000 description 5
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- -1 first electrode 01 Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
- H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
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- Thin Film Transistor (AREA)
Abstract
本发明提出薄膜晶体管结构和制造方法。该薄膜晶体管适配于基板上，包括：栅极；栅极绝缘层，覆盖所述栅极；半导体层，位于所述栅极绝缘层的上方；位于不同层的第一电极和第二电极，第一电极和第二电极均与所述半导体层接触；隔离层，位于第一电极和第二电极之间且覆盖部分半导体层，所述隔离层在所述半导体层上设有第一接触孔，所述第二电极通过所述第一接触孔与所述半导体层接触。本发明能够实现超高解析度的像素设计和更强的薄膜晶体管驱动能力。
The present invention proposes a thin film transistor structure and a manufacturing method. The thin film transistor is adapted to a substrate and includes: a gate electrode; a gate insulating layer covering the gate electrode; a semiconductor layer located above the gate insulating layer; a first electrode and a second electrode located on different layers, Both the first electrode and the second electrode are in contact with the semiconductor layer; the isolation layer is located between the first electrode and the second electrode and covers part of the semiconductor layer, and the isolation layer is provided with a first contact hole on the semiconductor layer , the second electrode is in contact with the semiconductor layer through the first contact hole. The present invention can realize ultra-high resolution pixel design and stronger thin film transistor driving capability.
Description
Technical field
The invention belongs to field of thin film transistors, and in particular to thin film transistor (TFT) and its manufacturing method.
Technical background
Traditional bottom gate stagger arrangement type TFT generally comprises etching protection type device architecture and back channel-etch type device architecture.
Successively film forming sequence is to form grid 01, form gate insulation layer, form semiconductor layer 02, being formed and carved to etching protection type device architecture
Erosion protective layer 03 is formed simultaneously source electrode and drain electrode 04, and finally formed thin film transistor (TFT) is as shown in Figure 1.The ditch road length of the device
Degree is a+2b, and a is the distance between same layer source electrode and drain electrode metal, is confined to exposure machine precision, b will ensure in source electrode and leakage
The hole of etch-protecting layer 03 can be covered after the etching of pole, the domain width that device entire in this way occupies is W=a+4b+2c, device
Part can not minimize, and channel length is larger.
In order to reduce processing procedure light shield quantity, effect of parasitic capacitance is reduced, develops back channel-etch type device architecture later.
Successively film forming sequence is to form grid 01, form gate insulation layer, form semiconductor layer 02, simultaneously to back channel-etch type device architecture
Source electrode and drain electrode 03 is formed, finally formed thin film transistor (TFT) is as shown in Figure 2.The channel length of the device is a, and a is same layer source
The distance between pole and drain metal are confined to exposure machine precision.The domain width that device entire in this way occupies is W=a+
2b compares and etching protection type device, and device widths are reduced, but still occupied space is larger, are not suitable for application
It is designed in the panel of super-resolution degree.
Both the above thin-film transistor structure all has the disadvantage in that TFT area occupied is big, is not suitable for developing superelevation solution
The display of analysis degree；The channel length L of TFT is restricted, and can not be reduced again, is unfavorable for current boost.
Summary of the invention
The present invention provides a kind of completely new thin-film transistor structure and manufacturing method, essentially consist in the source electrode gold of TFT
Belong to and drain metal is separately manufactured, effectively avoids the restricted degree system of the spacing between same layer metal and channel length is restricted asks
Topic realizes the pixel design and stronger thin film transistor (TFT) driving capability of super-resolution degree.
The technical solution is as follows:
The invention discloses a kind of thin film transistor (TFT), which includes:
Grid；Gate insulating layer covers the grid；Semiconductor layer, positioned at the top of the gate insulating layer；Positioned at not
The first electrode and second electrode of same layer, first electrode and second electrode are contacted with the semiconductor layer；Separation layer is located at the
Between one electrode and second electrode and covering part semiconductor layer, the separation layer are equipped with the first contact on the semiconductor layer
Hole, the second electrode are contacted by first contact hole with the semiconductor layer.
The invention also discloses a kind of thin film transistor (TFT)s, comprising:
Grid；Gate insulating layer covers the grid；Positioned at the first electrode and second electrode of different layers, first electrode
The top of gate insulating layer is respectively positioned on second electrode；Semiconductor layer, between first electrode and second electrode and with
One electrode and second electrode contact, the semiconductor layer part are located on the gate insulating layer.
Further, further include separation layer between the first electrode and second electrode, the separation layer is in institute
It states the top of semiconductor layer and is equipped with the first contact hole at the position that the semiconductor layer and gate insulating layer contact, described the
Two electrodes or first electrode are contacted by first contact hole with the part of the semiconductor layer.
The invention also discloses a kind of thin film transistor (TFT)s, comprising:
Positioned at the first electrode and second electrode of different layers；Semiconductor layer, between first electrode and second electrode and
Contacted with first electrode and second electrode；Gate insulating layer covers the first electrode, second electrode and semiconductor layer；Grid
Pole is located above the gate insulating layer.
Further, further include separation layer between the first electrode and second electrode, the separation layer is in institute
State the top of semiconductor layer and be equipped with the first contact hole at the position that the semiconductor and substrate contact, the second electrode or
First electrode is contacted by first contact hole with the part of the semiconductor layer.
The invention also discloses a kind of thin film transistor (TFT)s, comprising:
Positioned at the first electrode and second electrode of different layers；Separation layer, it is described between first electrode and second electrode
Separation layer is equipped with the first contact hole；Semiconductor layer, positioned at the top of the separation layer, a part of the semiconductor layer and second
Electrode contact, another part of the semiconductor layer is located in first contact hole to be contacted with first electrode；Gate insulating layer,
Cover the separation layer and semiconductor layer；Grid is located above the gate insulating layer.
Further, when a part Yu second electrode of the semiconductor layer contact positioned at the top of second electrode or under
Side.
The invention also discloses a kind of manufacturing methods of thin film transistor (TFT), comprising steps of
S1: grid is formed；
S2: the gate insulating layer of covering grid is formed；
S3: the semiconductor layer being located on gate insulating layer is formed；
S4: the first electrode of covering part gate insulating layer and covering part semiconductor layer is formed；
S5: the separation layer of covering gate insulating layer, first electrode and semiconductor layer is formed, the separation layer is described half
The first contact hole is set at the position of another part of conductor layer；
S6: the second electrode being located in the first contact hole is formed.
The invention also discloses a kind of manufacturing methods of thin film transistor (TFT), comprising steps of
S1: grid is formed；
S2: the gate insulating layer of covering grid is formed；
S3: the first electrode being located on gate insulating layer is formed；
S4: the semiconductor layer of covering part first electrode and covering part gate insulating layer is formed；
S5: the second electrode of another part of covering semiconductor layer is formed.
Further, it further comprises the steps of:
The separation layer of covering gate insulating layer, first electrode and semiconductor layer is formed, the separation layer is partly led described
The first contact hole is set at the position of another part of body layer；The second electrode passes through first contact hole and the semiconductor
Another part contact of layer.
The invention also discloses a kind of manufacturing methods of thin film transistor (TFT), comprising steps of
S1: first electrode is formed；
S2: the semiconductor layer of covering part first electrode is formed；
S3: the second electrode of covering semiconductor layer another part is formed；
S4: the gate insulating layer of covering first electrode, semiconductor layer and second electrode is formed；
S5: the grid being located on gate insulating layer is formed.
Further, it further comprises the steps of:
The separation layer of covering first electrode and semiconductor layer is formed, the separation layer is in another portion of the semiconductor layer
The first contact hole is set at the position divided；The second electrode passes through another part of first contact hole and the semiconductor layer
Contact.
The invention also discloses a kind of manufacturing methods of thin film transistor (TFT), comprising steps of
S1: first electrode is formed；
S2: the separation layer of formation a part covering first electrode and another part covering substrate, one of the separation layer
The quartile place of setting is equipped with the first contact hole；
S3: the semiconductor layer of a part covering separation layer and another part covering first electrode, the semiconductor layer are formed
Another part contacted in the first contact hole with first electrode；
S4: the second electrode being located in semiconductor layer a part is formed；
S5: the gate insulating layer of covering separation layer, second electrode and semiconductor layer is formed；
S6: the grid being located on gate insulating layer is formed.
The invention also discloses a kind of manufacturing methods of thin film transistor (TFT), comprising steps of
S1: first electrode is formed；
S2: the separation layer of formation a part covering first electrode and another part covering substrate, one of the separation layer
The quartile place of setting is equipped with the first contact hole；
S3: the second electrode being located on separation layer another part is formed；
S4: the semiconductor layer of a part covering second electrode and another part covering first electrode, the semiconductor are formed
Another part of layer contacts in the first contact hole with first electrode；
S5: the gate insulating layer of covering separation layer and semiconductor layer is formed；
S6: the grid being located on gate insulating layer is formed.
The present invention effectively avoids pitch problems and channel between same layer metal by the way that source electrode and drain electrode is located at different layers
Restricted problem；The present invention, for source electrode and drain electrode to be isolated, realizes the pixel design of super-resolution degree by newly-increased one layer of separation layer
With stronger thin film transistor (TFT) driving capability.
Detailed description of the invention
Below by clearly understandable mode, preferred embodiment is described with reference to the drawings, the present invention is given furtherly
It is bright.
Fig. 1 is traditional etching protection type film transistor device structural schematic diagram；
Fig. 2 is traditional back channel-etch type thin film transistor device architecture schematic diagram；
Fig. 3 is the structural schematic diagram of bottom gate formula TFT embodiment one of the present invention；
Fig. 4 is the schematic top plan view of bottom gate formula TFT embodiment one of the present invention；
Fig. 5 is the flow chart of the manufacturing method of bottom gate formula TFT embodiment one of the present invention；
Fig. 6 is the structural schematic diagram of bottom gate formula TFT embodiment two of the present invention；
Fig. 7 is the flow chart of the manufacturing method of bottom gate formula TFT embodiment two of the present invention；
Fig. 8 is the structural schematic diagram of bottom gate formula TFT embodiment three of the present invention；
Fig. 9 is the flow chart of the manufacturing method of bottom gate formula TFT embodiment three of the present invention；
Figure 10 is the structural schematic diagram of top-gated formula TFT embodiment four of the present invention；
Figure 11 is the flow chart of the manufacturing method of top-gated formula TFT embodiment four of the present invention；
Figure 12 is the structural schematic diagram of top-gated formula TFT embodiment five of the present invention；
Figure 13 is the flow chart of the manufacturing method of top-gated formula TFT embodiment five of the present invention；
Figure 14 is the structural schematic diagram of top-gated formula TFT embodiment six of the present invention；
Figure 15 is the flow chart of the manufacturing method of top-gated formula TFT embodiment six of the present invention；
Figure 16 is the structural schematic diagram of top-gated formula TFT embodiment seven of the present invention；
Figure 17 is the flow chart of the manufacturing method of top-gated formula TFT embodiment seven of the present invention.
Specific embodiment
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, Detailed description of the invention will be compareed below
A specific embodiment of the invention.It should be evident that drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing, and obtain other embodiments.
To make simplified form, part related to the present invention is only schematically shown in each figure, they are not represented
Its practical structures as product.In addition, there is identical structure or function in some figures so that simplified form is easy to understand
Component only symbolically depicts one of those, or has only marked one of those.Herein, "one" is not only indicated
" only this ", can also indicate the situation of " more than one ".
Technical solution of the present invention is described in detail below.
A kind of thin film transistor (TFT) proposed by the present invention is referred to as that the TFT structure (isolated of source electrode and drain electrode is isolated
Source and Drain TFT (ISD-TFT)), thin film transistor (TFT) of the present invention is suitable for any kind of semiconductor TFT, such as
Amorphous silicon, oxide semiconductor, low temperature polycrystalline silicon (LTPS), organic semiconductor etc..
Thin film transistor (TFT) of the present invention is respectively bottom gate formula thin film transistor (TFT) and top-gated formula thin film transistor (TFT).Wherein, bottom gate formula
Thin film transistor (TFT) includes three kinds of embodiments: source electrode and drain electrode only is isolated with separation layer isolation source electrode and drain electrode, semiconductor layer, partly leads
Source electrode and drain electrode is isolated with separation layer in body layer jointly, and bottom gate formula thin film transistor (TFT) includes four kinds of embodiments: being only isolated with separation layer
Source electrode and drain electrode is isolated with separation layer in source electrode and drain electrode, semiconductor layer isolation source electrode and drain electrode, semiconductor layer jointly.
Bottom gate formula thin film transistor (TFT) and top-gated formula thin film transistor (TFT) of the present invention are introduced separately below.
The first: bottom gate formula thin film transistor (TFT):
Fig. 3 is the structural schematic diagram of bottom gate formula TFT embodiment one of the present invention, only with separation layer isolation source electrode and
Drain electrode, as shown in Figure 1, the thin film transistor (TFT) includes grid 01 in the substrate (not shown), the grid that covers grid 01 is exhausted
Edge layer 02, the semiconductor layer 03 above gate insulating layer 02, first electrode 04, separation layer 05 and with first electrode 04
In the second electrode 06 of different layers, first electrode 04 and second electrode 06 are contacted with the semiconductor layer 03.
Wherein, the semiconductor layer 03 include along 01 extending direction of grid first part 031 and with described first
Divide the second part 032 of connection (i.e. semiconductor layer 03 is divided into left and right two parts)；First electrode 04 is set to the gate insulating layer
02 and the semiconductor layer 03 on, wherein the first electrode 04 covers the first part 031 of the semiconductor layer；Every
Absciss layer 05 covers the second part 032 of the gate insulating layer 02, first electrode 04 and semiconductor layer, the separation layer 05
Between first electrode 04 and second electrode 06 and covering part semiconductor layer 03, in the second part 032 of the semiconductor layer
The first contact hole 07 is equipped at position；Second electrode 06 covers the second part 032 of the semiconductor layer, the second electrode 06
It is contacted by first contact hole 07 with the second part 032 of the semiconductor layer.
It should be noted that second electrode 06 is drain electrode when first electrode 04 is source electrode；When first electrode 04 is drain electrode
When, second electrode 06 is source electrode.
Fig. 4 show the schematic top plan view of bottom gate formula TFT embodiment one of the present invention, successively includes from the bottom up
Grid 01, gate insulating layer 02, semiconductor layer 03, first electrode 04, the 05, second electricity of separation layer in substrate (not shown)
Pole 06.Wherein, channel length is a, and 04 metal width of first electrode is b, and the width of the first contact hole 07 is c, and entire film is brilliant
The width of body pipe can narrow down to W=a+b+c, such as a=1um, b=3um, c=2um, minimum widith W=6um.Film simultaneously
The channel length a of transistor is smaller compared to the two schemes in background technique, and the linear zone driving current of thin film transistor (TFT) is public
Show and is approximately:
Wherein, the channel length of thin film transistor (TFT) is L, and when l is small, the driving current of thin film transistor (TFT) can inverse ratio increasing
Add.A is the channel length (L=a) of TFT device, since source electrode and drain electrode metal is not same layer metal and has separation layer to separate,
Channel length a can even accomplish to be less than 1um, domain space very little shared by such thin film transistor (TFT), conducive to real on processing procedure
Existing super-resolution degree and stronger driving capability.
It is the flow chart of the manufacturing method of bottom gate formula TFT embodiment one of the present invention shown in Fig. 5, this method includes
Following steps:
S1: grid 01 is formed on substrate；
S2: the gate insulating layer 02 of covering grid 01 is formed；
S3: formed be located at gate insulating layer 02 on semiconductor layer 03, semiconductor layer include first part 031 and with institute
State the second part 032 of the connection of first part 031；
S4: the first electrode 04 of covering part gate insulating layer 02 and covering part semiconductor layer 03 is formed, wherein described
First electrode 04 covers the first part 031 of the semiconductor layer；
S5: the separation layer 05 of covering gate insulating layer 02, first electrode 04 and semiconductor layer 03, the separation layer are formed
05 is equipped with the first contact hole 07 at the second part 032 of the semiconductor layer；
S6: forming second electrode 06, and second electrode 06 is located on the second part 032 of semiconductor layer, the second electrode
06 is contacted by first contact hole 07 with the second part 032 of the semiconductor layer.
First electrode 04 and second electrode 06 are mainly kept apart by separation layer 05.
Method for fabricating thin film transistor can form ISD-TFT device according to figure 5, and subsequent process flow can root
It needs to be configured according to display, generally will increase protective layer and device is had an impact to avoid environment water oxygen etc..
Fig. 6 is the structural schematic diagram of bottom gate formula TFT embodiment two of the present invention, and source electrode is isolated by semiconductor layer
And drain electrode, as shown in fig. 6, the thin film transistor (TFT) includes the grid 01 being located in substrate (not shown), the grid for covering grid 01
Insulating layer 02, first electrode 03, semiconductor layer 04 and the second electrode 06 for being located at different layers with first electrode 03, first electrode
03 and second electrode 06 contacted with the semiconductor layer 04.
Wherein, first electrode 03 is located on the gate insulation layer 02；It is exhausted that 04 part of semiconductor layer is located at the grid
In edge layer 02, the semiconductor layer 04 extends in the first electrode 03 from the gate insulating layer 02, the semiconductor layer
04 includes the second part 042 for being located at the first part 041 of the first electrode 03 and connecting with the first part；Second
Electrode 06 covers and contacts the second part 042 of the semiconductor layer.
Since source electrode and drain electrode metal is not same layer metal and has semiconductor layer to be used as isolation separately, channel length is being made
It can accomplish to be less than 1um in journey, domain space very little shared by such thin film transistor (TFT), be conducive to realize super-resolution degree and stronger
Driving capability.
It is the flow chart of the manufacturing method of bottom gate formula TFT embodiment two of the present invention, including following step shown in Fig. 7
It is rapid:
S1: grid 01 is formed on substrate；
S2: the gate insulating layer 02 of covering grid 01 is formed；
S3: the first electrode 03 being located on gate insulating layer 02 is formed；
S4: forming the semiconductor layer 04 of covering part first electrode 03 and covering part gate insulating layer 02, described partly to lead
Body layer 04 extends in the first electrode 03 from the gate insulation layer 02, and the semiconductor layer 04 includes being located at first electricity
The first part 041 of pole 03 and the second part 042 being connect with the first part 041；
S5: the second electrode 06 of covering 04 second part 042 of semiconductor layer is formed.
First electrode 03 and second electrode 06 are mainly kept apart by semiconductor layer 04.
Fig. 8 is the structural schematic diagram of bottom gate formula TFT embodiment three of the present invention, passes through semiconductor layer and separation layer
Source electrode and drain electrode is isolated simultaneously, which includes the grid 01 being located in substrate (not shown), the grid for covering grid 01
Pole insulating layer 02, first electrode 03, semiconductor layer 04, the separation layer 05 above semiconductor layer 04 and with first electrode 03
Positioned at the second electrode 06 of different layers, first electrode 03 and second electrode 06 are contacted with the semiconductor layer 04.
The structure of TFT embodiment three and the structure of TFT embodiment two are essentially identical, and difference is
Separation layer 05 is additionally provided between first electrode 03 and second electrode 06, the separation layer 05 covers the gate insulating layer 02, institute
First electrode 03 and the semiconductor layer 04 are stated, the separation layer 05 is contacted in the semiconductor layer and gate insulating layer 02
The first contact hole 07 is equipped at 042 position of second part, the second electrode 06 passes through first contact hole 07 and described half
The second part 042 of conductor layer contacts.
Since source electrode and drain electrode is not same layer metal and has separation layer to separate, channel length can accomplish small on processing procedure
In 1um, domain space very little shared by such thin film transistor (TFT) is conducive to realize super-resolution degree and stronger driving capability.
It is the flow chart of the manufacturing method of bottom gate formula TFT embodiment three of the present invention, including following step shown in Fig. 9
It is rapid:
S1: grid 01 is formed on substrate；
S2: the gate insulating layer 02 of covering grid 01 is formed；
S3: the first electrode 03 being located on gate insulating layer 02 is formed；
S4: forming the semiconductor layer 04 of covering part first electrode 03 and covering part gate insulating layer 02, described partly to lead
Body layer 04 extends in the first electrode 03 from the gate insulation layer 02, and the semiconductor layer 04 includes being located at first electricity
The first part 041 of pole 03 and the second part 042 being connect with the first part 041；
S5: the separation layer 05 of covering gate insulating layer 02, first electrode 03 and semiconductor layer 04, the separation layer are formed
05 is equipped with the first contact hole 07 at 042 position of second part of semiconductor；The second electrode 06 is contacted by described first
Hole 07 is contacted with the second part 042 of the semiconductor layer；
S6: the second electrode 06 of covering 04 second part 042 of semiconductor layer is formed.
First electrode 03 and second electrode 06 are mainly kept apart by semiconductor layer 04 and separation layer 05.
After the completion of the manufacture of TFT device, a protective layer can be re-formed to isolation environment (such as water, oxygen, nitrogen
Deng) to device generate influence.
Second: top-gated formula thin film transistor (TFT):
Figure 10 is the structural schematic diagram of top-gated formula TFT embodiment four of the present invention, and source electrode is isolated by semiconductor layer
And drain electrode, the thin film transistor (TFT) include the first electrode 01 being located in substrate (not shown) and semiconductor layer 02 and first electrode
01 is located at second electrode 04, gate insulating layer 05 and the grid 06 of different layers, and first electrode 01 and second electrode 04 are and institute
State the contact of semiconductor layer 02.
Wherein, the semiconductor layer 02 is extended to from substrate in the first electrode 01, and the semiconductor layer 02 includes
First part 021 positioned at the first electrode 04 and the second part 022 that is connect with the first part；Second electrode
04, cover and contact the second part 022 of the semiconductor layer；Gate insulating layer 05 covers the substrate, first electrode
01, semiconductor layer 02 and second electrode 04；Grid 06 is located on the gate insulating layer 05.
Since source electrode and drain electrode metal is not same layer metal and has semiconductor layer to be used as isolation separately, channel length is being made
It can accomplish to be less than 1um in journey, domain space very little shared by such thin film transistor (TFT), be conducive to realize super-resolution degree and stronger
Driving capability.
It is the flow chart of the manufacturing method of top-gated formula TFT embodiment four of the present invention, including following step shown in Figure 11
It is rapid:
S1: first electrode 01 is formed on substrate；
S2: forming the semiconductor layer 02 of covering part first electrode 01, and the semiconductor layer 02 extends to institute from substrate
It states in first electrode 01, the semiconductor layer 02 includes positioned at the first part 021 of the first electrode 01 and with described the
The second part 022 of 021 connection of a part；
S3: the second electrode 04 of the second part 022 of covering semiconductor layer 02 is formed；
S4: the gate insulating layer 05 of covering first electrode 01, semiconductor layer 02 and second electrode 04 is formed；
S5: the grid 06 being located on gate insulating layer 05 is formed.
First electrode 01 and second electrode 04 are mainly kept apart by semiconductor layer 02.
Figure 12 is the structural schematic diagram of top-gated formula TFT embodiment five of the present invention, passes through semiconductor layer and separation layer
Source electrode and drain electrode is isolated simultaneously, which includes first electrode 01 and semiconductor layer in substrate (not shown)
02, the separation layer 03 above semiconductor layer 02 and first electrode 01 are located at the second electrode 04 of different layers, gate insulating layer
05 and grid 06, first electrode 01 and second electrode 04 contacted with the semiconductor layer 02.
The structure of TFT embodiment five and the structure of TFT embodiment four are essentially identical, and difference is
Separation layer 03 is additionally provided between the first electrode 01 and second electrode 04, the separation layer 03 covers the substrate, described
One electrode 01 and the semiconductor layer 02, the separation layer 03 are equipped with the at 022 position of second part of the semiconductor
One contact hole 07, the second electrode 04 are contacted by first contact hole 07 with the second part 022 of the semiconductor layer.
Since source electrode and drain electrode metal is not same layer metal and has separation layer to separate, channel length can be done on processing procedure
To 1um is less than, domain space very little shared by such thin film transistor (TFT) is conducive to realize super-resolution degree and stronger driving energy
Power.
It is the flow chart of the manufacturing method of top-gated formula TFT embodiment five of the present invention, including following step shown in Figure 13
It is rapid:
S1: first electrode 01 is formed on substrate；
S2: forming the semiconductor layer 02 of covering part first electrode 01, and the semiconductor layer 02 extends to institute from substrate
It states in first electrode 01, the semiconductor layer 02 includes positioned at the first part 021 of the first electrode 01 and with described the
The second part 022 of 021 connection of a part；
S3: the separation layer 03 of covering first electrode 01 and semiconductor layer 02 is formed, the separation layer 03 is in semiconductor
The first contact hole 07 is equipped at 022 position of second part；The second electrode 04 passes through first contact hole 07 and described half
The second part 022 of conductor layer contacts；
S4: the second electrode 04 of the second part 022 of covering semiconductor layer 02 is formed；
S5: the gate insulating layer 05 of covering first electrode 01, semiconductor layer 02 and second electrode 04 is formed；
S6: the grid 06 being located on gate insulating layer 05 is formed.
First electrode 01 and second electrode 04 are mainly kept apart by semiconductor layer 02 and separation layer 03.
After the completion of the manufacture of TFT device, a protective layer can be re-formed to isolation environment (such as water, oxygen, nitrogen
Deng) device is had an impact.
The structural schematic diagram of top-gated formula TFT embodiment six of the present invention shown in Figure 14, by semiconductor layer with every
Source electrode and drain electrode is isolated in absciss layer jointly, and the thin film transistor (TFT) as shown in figure 14 includes the first electrode in substrate (not shown)
01, the separation layer 02 between first electrode 01 and second electrode 04, semiconductor layer 03 and first electrode 01 are located at different layers
Second electrode 04, gate insulating layer 05 and grid 06, first electrode 01 and second electrode 04 with the semiconductor layer 02
Contact.
Wherein, the separation layer 02 extends from substrate and covers first electrode 01, and the separation layer 02 includes being covered on
The first part 021 of first electrode 01 and the second part 022 being connect with first part, at first of the separation layer 02
Divide and is equipped with the first contact hole 07 at 021 position；Semiconductor layer 03 is formed in the top of separation layer 02 and first electrode 01, described
Semiconductor layer 03 includes the second part 032 for being covered on the first part 031 of separation layer 02 and connecting with first part 031,
The second part 032 of the semiconductor layer 03 contacts in the first contact hole 07 with first electrode 01；04 shape of second electrode
At in the first part 031 of semiconductor layer 03；Gate insulating layer 05 cover the substrate, separation layer 02, second electrode 04 with
And semiconductor layer 03；Grid 06 is located on the gate insulating layer 05.
Since source electrode and drain electrode metal is not same layer metal and has separation layer to separate, channel length can be done on processing procedure
To 1um is less than, domain space very little shared by such thin film transistor (TFT) is conducive to realize super-resolution degree and stronger driving energy
Power.
It is the flow chart of the manufacturing method of top-gated formula TFT embodiment six of the present invention, including following step shown in Figure 15
It is rapid:
S1: first electrode 01 is formed on substrate；
S2: forming and be located at separation layer 02 in substrate and first electrode 01, and the separation layer 02 extends and covers from substrate
Lid first electrode 01, the separation layer 02 include being covered on the first part 021 of first electrode 01 and connecting with first part
Second part 022, at 021 position of first part of the separation layer 02 be equipped with the first contact hole 07；
S3: forming the upper semiconductor layer 03 for being located at separation layer 02 and first electrode 01, and the semiconductor layer 03 includes
The second part 032 for being covered on the first part 031 of separation layer 02 and being connect with first part 031, the semiconductor layer 03
Second part 032 contacted in the first contact hole 07 with first electrode 01；
S4: the second electrode 04 being located in 03 first part 031 of semiconductor layer is formed；
S5: the gate insulating layer 05 of covering separation layer 03, second electrode 04 and semiconductor layer 03 is formed；
S6: the grid 06 being located on gate insulating layer 05 is formed.
First electrode 01 and second electrode 04 are mainly kept apart by separation layer 02 and semiconductor layer 03.
After the completion of the manufacture of TFT device, a protective layer can be re-formed to isolation environment (such as water, oxygen, nitrogen
Deng) device is had an impact.
It is the structural schematic diagram of top-gated formula TFT embodiment seven of the present invention shown in Figure 16, source is isolated by separation layer
Pole and drain electrode, the thin film transistor (TFT) as shown in figure 16 include the first electrode 01 being located in substrate (not shown), are located at the first electricity
Separation layer 02, semiconductor layer 04 between pole 01 and second electrode 03, the second electrode 03 for being located at different layers with first electrode 01,
Gate insulating layer 05 and grid 06, first electrode 01 and second electrode 03 are contacted with the semiconductor layer 04.
Wherein, the structure of TFT embodiment seven and the structure of TFT embodiment six are essentially identical, area
It is not that the semiconductor layer 04 is formed in the top of first electrode 01, separation layer 02 and second electrode 03, the semiconductor
Layer 04 includes the second part 042 for being covered on the first part 041 of second electrode 03 and connecting with first part 041, described
The second part 042 of semiconductor layer 04 contacts in the first contact hole 07 with first electrode 01.
Since source electrode and drain electrode metal is not same layer metal and has separation layer to separate, channel length can be done on processing procedure
To 1um is less than, domain space very little shared by such thin film transistor (TFT) is conducive to realize super-resolution degree and stronger driving energy
Power.
It is the flow chart of the manufacturing method of top-gated formula TFT embodiment seven of the present invention, including following step shown in Figure 17
It is rapid:
S1: first electrode 01 is formed on substrate；
S2: forming the separation layer 02 being located in substrate and first electrode 01, and the separation layer 02 extends simultaneously from substrate
First electrode 01 is covered, the separation layer 02 includes being covered on the first part 021 of first electrode 01 and connecting with first part
The second part 022 connect is equipped with the first contact hole 07 at 021 position of first part of the separation layer 02；
S3: the second electrode 03 being located on 02 second part 022 of separation layer is formed；
S4: the semiconductor layer 04 of covering first electrode 01, separation layer 02 and second electrode 03, the semiconductor layer are formed
04 includes the second part 042 for being covered on the first part 041 of second electrode 03 and connecting with first part 041, and described half
The second part 042 of conductor layer 04 contacts in the first contact hole 07 with first electrode 01；
S5: the gate insulating layer 05 of covering separation layer 02 and semiconductor layer 04 is formed；
S6: the grid 06 for being located at gate insulating layer 05 is formed.
First electrode 01 and second electrode 03 are mainly kept apart by separation layer 02 and semiconductor layer 04.
After the completion of the manufacture of TFT device, a protective layer can be re-formed to isolation environment (such as water, oxygen, nitrogen
Deng) device is had an impact.
In the embodiment of seven kinds of structures described above, semiconductor layer material is not limited to amorphous silicon, oxide semiconductor, polycrystalline
Silicon, organic semiconductor etc.；Grid, source electrode, drain metal layer material are not limited to single-layer metal, lamination metal, such as Mo single layer, fold
Layer Ti/Cu, Mo/Al/Mo etc.；Gate insulating layer, insolated layer materials are not limited to SiO2、SiOx、Al2O3, SiNx etc., or can be with
Preferred multi-layer insulation superposition is required according to TFT device property.
It should be noted that the above is only a preferred embodiment of the present invention, but the present invention is not limited to above-mentioned
Detail in embodiment, it is noted that for those skilled in the art, in technology of the invention
In conception range, various improvements and modifications may be made without departing from the principle of the present invention, to technology of the invention
Scheme carries out a variety of equivalents, these are improved, retouching and equivalents also should be regarded as protection scope of the present invention.
Claims (14)
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