CN109411436B - 64-channel analog quantity acquisition BGA (ball grid array) packaging chip - Google Patents
64-channel analog quantity acquisition BGA (ball grid array) packaging chip Download PDFInfo
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- CN109411436B CN109411436B CN201811033522.6A CN201811033522A CN109411436B CN 109411436 B CN109411436 B CN 109411436B CN 201811033522 A CN201811033522 A CN 201811033522A CN 109411436 B CN109411436 B CN 109411436B
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
The invention relates to the technical field of telemetering communication, and discloses a 64-channel analog quantity acquisition BGA (ball grid array) packaging chip, which comprises a substrate, a bare chip and a solder ball; the substrate comprises a wiring layer, a grounding layer, a power supply layer, a bottom layer, a first conductive connecting unit, a second conductive connecting unit and a third conductive connecting unit which are arranged in a laminated mode; a first bonding pad serving as a first bonding point is arranged at a position, corresponding to the first conductive connecting unit, on the surface of the wiring layer, a second bonding pad serving as a second bonding point is arranged at a position, corresponding to the second conductive connecting unit, and a third bonding pad serving as a third bonding point is arranged at a position, corresponding to the third conductive connecting unit, on the surface of the wiring layer; an AD chip in the bare chip is electrically connected with a second bonding point and a third bonding point on the wiring layer, and the operational amplifier and the analog gate are electrically connected with a first bonding point and a second bonding point on the wiring layer; the substrate has compact structure and high space utilization rate, and adopts bare chips to design and package circuits, so that the volume is reduced by about 85 percent, and the universality of the chips is improved.
Description
Technical Field
The invention belongs to the technical field of telemetering communication, and particularly relates to a 64-channel analog quantity acquisition BGA packaging chip.
Background
In the telemetering communication technology, the telemetering acquisition and coding circuit is mainly responsible for conditioning and acquiring signals of a plurality of sensors, and an analog acquisition module is an important component of the telemetering acquisition and coding circuit and has the functions of analog conditioning, routing and AD acquisition. In the field of aerospace, the impact sensor is required to have the highest sampling rate among various sensors, the number of sampling paths of the impact sensor is generally not more than 6, the sampling rate is not more than 20kHz, and a multi-path analog quantity acquisition module is required to be designed, so that data acquisition of 6 paths of the impact sensor can be completed, and data acquisition of other sensors can also be completed. The sampling rate of 64 analog quantity acquisition modules (comprising 4 analog gates) is 125kHz shared by 16 analog gates, one analog gate in the module can finish the data acquisition task of the impact sensor, 48 analog gates left can be used for data acquisition of other sensors, and in most products, all analog quantity acquisition can be finished by only using one 64 analog quantity acquisition module.
At present, the module with 64 analog acquisition functions used on a telemetry stand-alone unit of an aerospace product is a conventional printed board level circuit, and specifically, one AD7656(AD company, size 12mm 10mm 1.6mm), four operational amplifiers TLE2071(TI company, size 5.00mm 4.00mm 1.75mm), four analog gates ADG506A (AD company, size 12.57mm 4.51mm) with a package are reflow-soldered on an FR-4 printed circuit board with size at least about 30mm × 30mm × 2mm, the size is large, and the external shape of the printed circuit board needs to be designed into different shapes according to the shape of a cavity of the telemetry stand-alone unit, so that the universality of a single analog acquisition module is poor. With the great advance of microsystem technology and application in the electronic industry, 64-channel analog quantity acquisition modules in a printed board level assembly mode cannot meet the urgent requirements of miniaturization and generalization of telemetering electronic products.
Disclosure of Invention
In view of at least one of the defects or the improvement requirements of the prior art, the present invention provides a 64-channel analog acquisition Ball Grid Array (BGA) package chip, which aims to solve the problems of large size, high cost and poor versatility of the existing printed board level assembled analog acquisition module.
To achieve the above object, according to one aspect of the present invention, there is provided a 64-way analog quantity acquisition BGA package chip, including a substrate, a plurality of bare chips, and solder balls; the substrate comprises a wiring layer, a grounding layer, a power supply layer and a bottom layer which are arranged in a laminated mode, and a first conductive connecting unit, a second conductive connecting unit and a third conductive connecting unit which penetrate through the wiring layer, the grounding layer, the power supply layer and the bottom layer;
the power supply layer is provided with a through hole allowing the first conductive connecting unit to pass through, and the size of the through hole is larger than the size of the cross section of the first conductive connecting unit so as to ensure that no electric connection exists between the power supply layer and the first conductive connecting unit; a first bonding pad serving as a first bonding point is arranged at a position, corresponding to the first conductive connecting unit, on the surface of the wiring layer; through holes allowing the second conductive connecting units to penetrate through are formed in the grounding layer and the power layer, and the size of each through hole is larger than the size of the cross section of each second conductive connecting unit so as to ensure that no electric connection exists among the grounding layer, the power layer and the second conductive connecting units; a second bonding pad serving as a second bonding point is arranged on the surface of the wiring layer at a position corresponding to the second conductive connecting unit; the ground layer is provided with a through hole allowing the third conductive connecting unit to pass through, and the size of the through hole is larger than the cross section size of the third conductive connecting unit so as to ensure no electric connection between the ground layer and the third conductive connecting unit; a third bonding pad serving as a third bonding point is arranged at a position, corresponding to the third conductive connecting unit, on the surface of the wiring layer;
the bare chip comprises an AD chip, four operational amplifiers and four analog gates which are tiled on the wiring layer; the AD chip is electrically connected with the second bonding point and the third bonding point on the wiring layer; the operational amplifier and the analog gate are electrically connected with a first bonding point and a second bonding point on the wiring layer; and the bottom surface is provided with a fourth bonding pad at the position corresponding to the first conductive connecting unit, the second conductive connecting unit and the third conductive connecting unit, and the fourth bonding pad is used for welding a solder ball to realize the signal output of the chip.
Preferably, the 64-channel analog quantity acquisition BGA package chip further includes a molding compound for coating the substrate and the bare chip, wherein the molding compound is made of an epoxy resin material and has a size of 18mm × 18mm × 0.8 mm.
Preferably, the 64-channel analog quantity acquisition BGA package chip has a bare chip electrically connected to each bonding point through a gold wire bonding process; and the bonding point is formed on the surface of the wiring layer through an etching process.
Preferably, a dielectric layer is disposed between the ground layer and the power layer of the 64-channel analog quantity acquisition BGA package chip, and the dielectric layer is made of bismaleimide modified triazine resin.
Preferably, the fourth pad of the 64-channel analog quantity acquisition BGA package chip is a circular metal pad with a diameter of 0.55mm, and the distance between adjacent fourth pads is 1.00 mm.
Preferably, the solder balls of the 64-channel analog quantity acquisition BGA package chip are arranged in a ball grid array, and the pitch, diameter and height of the solder balls are 1.0mm, 0.5mm and 0.38mm, respectively.
In general, compared with the prior art, the above technical solution contemplated by the present invention can achieve the following beneficial effects:
(1) according to the 64-channel analog quantity acquisition BGA packaging chip, an AD chip, four operational amplifiers and four analog gates are adhered to a substrate through non-conductive adhesive patches and then bonded to bonding points of the substrate through gold wires, and the bonding points are formed on the upper surface of the substrate through an etching process. The micro-integration design and the micro-assembly are carried out through the packaging of the substrate with smaller size, the three bare chips and the square molding compound, the space utilization rate on the substrate is improved, and compared with a 64-channel analog quantity acquisition module in the existing printed board level assembly mode, the volume is reduced by about 85 percent, and the weight is also greatly reduced;
(2) the 64-channel analog quantity acquisition BGA packaging chip provided by the invention has the advantages that the substrate is a four-layer structural plate consisting of the wiring layer, the grounding layer, the power supply layer and the bottom layer, the separately arranged grounding layer and the power supply layer are provided with complete power supply/ground planes which are not divided by metal wiring, a complete current backflow path can be provided for the metal wiring on the wiring layer, the inductance of a signal loop is reduced, the ground coupling of the power supply is increased, and the direct-current voltage drop is reduced; the thickness of the four-layer structure substrate is increased, so that the deformation degree of the substrate is smaller, the technical processes of glue sticking, bonding and the like of a bare chip are facilitated, and the probability of failures such as overlarge internal stress, delamination, chip cracks and the like caused by high and low temperature changes of a packaged chip sample during assembly is reduced; the substrate has small volume, compact structure and high space utilization rate, so that the length of metal wiring on the wiring layer is reduced, and the integrity and the anti-interference capability of signals are greatly improved;
(3) the shape of the 64-channel analog quantity acquisition BGA packaging chip provided by the invention does not need to be designed into different shapes according to different shapes of a cavity of a telemetering single-machine like a 64-channel analog quantity acquisition module assembled by a printed board, an FPGA control circuit, a power supply circuit and a peripheral circuit can be conveniently matched, and the universality of a functional module chip is realized;
(4) according to the 64-channel analog quantity acquisition BGA packaging chip, the dielectric layer in the substrate is made of bismaleimide modified triazine resin, and compared with the existing FR-4 substrate, the 64-channel analog quantity acquisition BGA packaging chip has better parameter stability and lower moisture absorption.
Drawings
FIG. 1 is a cross-sectional view of a 64-way analog acquisition BGA package chip provided by an embodiment of the present invention;
FIG. 2 is a top view of the interior of a 64-way analog acquisition BGA package chip provided by an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a substrate according to an embodiment of the present invention;
FIG. 4 is a bottom view of a 64-way analog acquisition BGA package chip provided by an embodiment of the present invention;
in all the figures, the same reference numerals denote the same features, in particular: 1-substrate, 11-wiring layer, 12-grounding layer, 13-power layer, 14-bottom layer, 15-first conductive connecting unit, 16-second conductive connecting unit, 17-third conductive connecting unit, 2-bare chip, 3-solder ball, 4-molding compound, 5-first bonding pad, 6-second bonding pad, 7-third bonding pad and 8-fourth bonding pad.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Fig. 1 is a schematic structural diagram of a 64-way analog quantity acquisition BGA package chip provided in this embodiment, as shown in fig. 1, the 64-way analog quantity acquisition BGA package chip includes a substrate 1, a bare chip 2, solder balls 3 and a molding compound 4;
the upper surface of the substrate 1 is provided with bonding points formed by an etching process, the bare chip 2 is adhered on the substrate 1 through a non-conductive patch, and then bonded on the bonding points of the substrate 1 in a gold wire bonding mode; the solder balls 3 are arranged on the lower surface of the substrate 1 in a ball grid array; the molding compound 4 is used for coating the upper surface of the substrate 1 and the bare chip 2 thereon.
In the 64-channel analog quantity acquisition BGA package chip provided in this embodiment, the bare chip 2 includes an AD chip, four operational amplifiers and four analog gates, as shown in fig. 2, the bare chip 2 is bonded to the upper surface of the substrate 1 in a tiled manner, where U1, U2, U3 and U4 represent the bare chips of the operational amplifiers, U5, U6, U7 and U8 represent the bare chips of the analog gates, and U9 represents the AD bare chip; the four analog gates are used for receiving 64 paths of slowly-changed analog quantity input from the outside, the 64 paths of slowly-changed analog quantity are subjected to signal amplification through 4 operational amplifiers and then input to the AD chip, the AD chip converts the acquired amplified analog signals into digital signals, and the functions of amplifying, acquiring and converting the 64 paths of analog quantity signals are achieved.
FIG. 3 is a schematic structural diagram of a substrate according to an embodiment of the present invention; as shown in fig. 3, the substrate 1 includes a wiring layer 11, a ground layer 12, a power supply layer 13, a bottom layer 14, and a first conductive connecting unit 15, a second conductive connecting unit 16, a third conductive connecting unit 17 penetrating the wiring layer 11, the ground layer 12, the power supply layer 13, and the bottom layer 14;
the wiring layer 11 is used for making metal wiring, and the first conductive connecting unit 15 is used for realizing the electrical conduction between the wiring layer 11 and the ground layer 12 and simultaneously interconnecting with the solder balls 3 on the lower surface of the bottom layer 14; the power layer 13 is provided with a through hole for allowing the first conductive connecting unit 15 to pass through, and the size of the through hole is larger than the cross-sectional size of the first conductive connecting unit 15 so as to ensure that no electric connection exists between the power layer 13 and the first conductive connecting unit 15; a first bonding pad 5 serving as a first bonding point is arranged at a position, corresponding to the first conductive connecting unit 15, on the surface of the wiring layer 11, and the bare chip 2 is bonded to the first bonding point on the wiring layer 11 through a gold wire to realize electrical connection with the wiring layer 11;
the second conductive connecting unit 16 is used for realizing direct interconnection between the wiring layer 11 and the solder balls 3 on the lower surface of the bottom layer 14, through holes allowing the second conductive connecting unit 16 to pass through are formed on the ground layer 12 and the power supply layer 13, and the size of the through holes is larger than the size of the cross section of the second conductive connecting unit 16 so as to ensure no electrical connection among the ground layer 12, the power supply layer 13 and the second conductive connecting unit 16; a second bonding pad 6 serving as a second bonding point is arranged on the surface of the wiring layer 11 at a position corresponding to the second conductive connection unit 16 and serves as a second bonding point electrically connected with the bare chip 2;
the third conductive connecting unit 17 is used for realizing the electrical connection between the wiring layer 11 and the power supply layer 13 and simultaneously interconnecting with the solder balls 3 on the lower surface of the bottom layer 14; the ground layer 12 is provided with a through hole for allowing the third conductive connection unit 17 to pass through, and the size of the through hole is larger than the cross-sectional size of the third conductive connection unit 17 so as to ensure no electrical connection between the ground layer 12 and the third conductive connection unit 17; a third bonding pad 7 serving as a third bonding point is arranged at a position, corresponding to the third conductive connection unit 17, on the surface of the wiring layer 11, and the bare chip 2 is bonded to the third bonding point on the wiring layer 11 through a gold wire to realize electrical connection with the wiring layer 11;
the positions, corresponding to the first conductive connection unit 15, the second conductive connection unit 16 and the third conductive connection unit 17, of the surface of the bottom layer 12 are provided with 17 × 17-289 fourth bonding pads 8 which are arranged in a square shape, and the fourth bonding pads are used for soldering the solder balls 3 to realize signal output of 64-channel analog quantity acquisition BGA package chips, and the distance and the diameter of each fourth bonding pad 8 are 1.00mm and 0.55mm respectively.
The AD chip is respectively bonded to the second bonding point and the third bonding point on the surface of the wiring layer 11 through gold wires; the operational amplifier and the analog gate are bonded to the first bonding point and the second bonding point on the surface of the wiring layer 11 by gold wires, respectively.
A dielectric layer core is arranged between the grounding layer 12 and the power supply layer 13 and used for keeping the insulation and isolation between the grounding layer 12 and the power supply layer 13 and supporting the whole substrate 1; the dielectric layer core is made of bismaleimide modified triazine resin materials and is called as a BT substrate, compared with a glass fiber epoxy resin copper clad laminate (FR-4 substrate) adopted in the existing printed board level assembly mode, the BT substrate has better parameter stability and lower moisture absorption, and the size of the substrate 1 is 18mm by 0.35 mm;
the ground layer 12 and the power layer 13 have complete power/ground planes which are not divided by metal wires, so that a complete current return path can be provided for the metal wires on the wiring layer 11, the inductance of a signal loop can be reduced, the ground coupling of the power can be increased, and the direct-current voltage drop can be reduced; the direct current voltage drop exceeds a certain limit, which can cause the chip to be incapable of working normally due to undervoltage, and the voltage drop of the power supply for supplying power to the bare chip 2 is small, thereby ensuring the normal work of the chip.
The power layer 13 comprises analog power supplies, +15V and-15V power supplies and is used for supplying power for the AD chip, the operational amplifier and the analog gate; correspondingly, the ground layer 12 includes an analog ground AGND thereon.
The substrate provided by the embodiment is a four-layer structure plate consisting of a wiring layer 11, a ground layer 12, a power layer 13 and a bottom layer 14, the ground layer 12 and the power layer 13 which are independently arranged have complete power/ground planes which are not divided by metal wires, so that the power supply of a bare chip in a package is ensured, and the voltage drop is reduced; the thickness of the four-layer structure substrate is slightly increased, so that the deformation degree of the substrate is smaller, the technical processes of glue sticking, bonding and the like of a bare chip are facilitated, and the probability of failure such as overlarge internal stress, delamination, chip crack and the like caused by high and low temperature change of a packaged chip sample during assembly is reduced; the substrate has compact structure and high space utilization rate, realizes the circuit micro-integration design and the micro-assembly of the bare chip, and greatly reduces the whole volume of the 64-channel analog quantity acquisition module.
The upper surface of the substrate and the bare chip on the substrate are coated by square molding compound 4, the molding compound 4 is made of epoxy resin material, and the external dimension is 18mm multiplied by 0.8 mm.
As shown in fig. 4, the solder balls 3 are soldered on the fourth pads 8 on the lower surface of the bottom plate 14 in a ball grid array arrangement, and the pitch, diameter and height of the solder balls 3 are 1.00mm, 0.50mm and 0.38mm, respectively. The 289-pin solder balls are led out of the 64-channel analog quantity acquisition BGA packaging chip provided by the embodiment, and the overall external size of the 64-channel analog quantity acquisition BGA packaging chip is 18mm multiplied by 1.53mm (including the height of the solder balls).
The model of the AD chip adopted in this example is the AD chip SAD7656X of chongqing 24, and the size is 5.56mm 6.65mm 0.33 mm; the operational amplifier is TLE2071 of TI company, and the size is 1.45mm x 2.125mm x 0.375 mm; the simulated door was ADG506A from AD, with dimensions of 1.5mm 2.925mm 0.5 mm; after the three bare chips are fixed on a substrate and packaged by a molding compound, the size of the prepared 64-path analog quantity acquisition BGA packaging chip is 18mm multiplied by 1.53mm, and compared with a 64-path analog quantity acquisition module of a printed board level assembly mode with the size of about 40mm multiplied by 2mm, the volume of the module is reduced to 15.49 percent of the original (18mm multiplied by 1.53mm)/(40mm multiplied by 2mm), so that the conversion of the functional circuit from the printed board level mounting to the chip level mounting is realized, and the volume is reduced by about 85 percent. Three bare chips with smaller sizes are selected for circuit micro-integration design and micro-assembly, so that the space utilization rate of the substrate is improved, and the overall volume of the 64-channel analog quantity acquisition module is greatly reduced; therefore, the shape of the module does not need to be designed into different shapes according to the different shapes of the cavity of the telemetering single-machine like a 64-channel analog quantity acquisition module assembled by a printed board, an FPGA control circuit, a power supply circuit and a peripheral circuit can be conveniently matched, and the universality of a functional module chip is realized. In addition, the price of the bare chip is lower than that of the chip with the packaging structure, so that the production cost of the 64-channel analog quantity acquisition module can be reduced; the weight of the 64-channel analog quantity acquisition BGA packaging chip provided by the embodiment is reduced to several grams from several tens grams of 64-channel analog quantity acquisition modules assembled by a printed board, and the light weight of the functional module chip is realized.
The manufacturing process of the 64-channel analog quantity acquisition BGA package chip provided by the embodiment comprises the following steps:
s1: manufacturing a BT substrate, and pre-burying signal lines on a wiring layer, a ground layer and a power layer;
s2: carrying out plasma cleaning on the bare chip and the BT substrate, and carrying out room-temperature 1h of temperature return treatment on the surface mount adhesive;
s3: adhering the AD chip on the substrate by using a chip mounter according to a chip mounting program; drying the patch adhesive for 2h at 125 ℃ by using an integral nitrogen-filled oven; removing the redundant substances and checking; repeating the steps until the rest bare chips are pasted on the substrate;
s4: carrying out plasma cleaning on the substrate on which all the bare chips are adhered; carrying out gold wire ball bonding by using a full-automatic ball wedge bonding machine;
s5: sequentially carrying out plastic packaging and solder ball array packaging, and coating molding compounds outside the substrate and the bare chip; the excess was purged and examined.
According to the 64-path analog quantity acquisition BGA packaging chip, the substrate is provided with a complete power supply/ground plane, a complete current backflow path can be provided for metal wiring on a wiring layer, the inductance of a signal loop is reduced, and the increase of power supply ground coupling and the reduction of direct current voltage drop are facilitated; the substrate of the four-layer structural plate has smaller deformation degree than the two-layer structural plate, which is beneficial to the technical processes of glue sticking, bonding and the like of a bare chip and reduces the probability of failure of overlarge internal stress, delamination, chip cracks and the like caused by high and low temperature changes of a packaged chip sample during assembly; the substrate has small volume, compact structure and high space utilization rate, so that the length of metal wiring on the wiring layer is reduced, and the integrity and the anti-interference capability of signals are greatly improved; compared with printed board level packaging, the bare chip is adopted for circuit design and packaging, the volume is reduced by about 85%, and the universality of the chip is improved.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (3)
1. A64-channel analog quantity acquisition BGA (ball grid array) packaging chip is characterized by comprising a substrate, a bare chip and a solder ball; the substrate comprises a wiring layer, a grounding layer, a power supply layer and a bottom layer which are arranged in a laminated mode, and a first conductive connecting unit, a second conductive connecting unit and a third conductive connecting unit which penetrate through the wiring layer, the grounding layer, the power supply layer and the bottom layer;
the first conductive connecting unit is used for realizing the electrical connection between the wiring layer and the grounding layer and between the wiring layer and the solder balls on the lower surface of the bottom layer; a first bonding pad serving as a first bonding point is arranged at a position, corresponding to the first conductive connecting unit, on the surface of the wiring layer; the second conductive connecting unit is used for realizing the electric connection between the wiring layer and the solder balls on the lower surface of the bottom layer, and a second bonding pad serving as a second bonding point is arranged at the position, corresponding to the second conductive connecting unit, on the surface of the wiring layer; the third conductive connecting unit is used for realizing the electric connection between the wiring layer and the power supply layer and between the wiring layer and the solder balls on the lower surface of the bottom layer, and a third bonding pad serving as a third bonding point is arranged at the position, corresponding to the third conductive connecting unit, on the surface of the wiring layer; the grounding layer and the power supply layer are provided with complete power supply/ground planes which are not divided by the metal routing, and can provide complete current return paths for the metal routing on the wiring layer; a dielectric layer is arranged between the grounding layer and the power supply layer, and the dielectric layer is made of bismaleimide modified triazine resin;
the bare chip comprises an AD chip, four operational amplifiers and four analog gates which are tiled on the wiring layer; the four analog gates are used for receiving 64 paths of slowly-changed analog quantity input from the outside, the 64 paths of slowly-changed analog quantity are subjected to signal amplification through the four operational amplifiers and then input to the AD chip, the AD chip converts the acquired amplified analog signals into digital signals, and the functions of amplifying, acquiring and converting the 64 paths of analog quantity signals are realized; the AD chip is electrically connected with the second bonding point and the third bonding point on the wiring layer; the operational amplifier and the analog gate are electrically connected with a first bonding point and a second bonding point on the wiring layer; a fourth bonding pad is arranged on the surface of the bottom layer at a position corresponding to the first conductive connecting unit, the second conductive connecting unit and the third conductive connecting unit, and the solder balls are welded on the fourth bonding pad in a ball grid array mode to achieve signal output of the chip;
the fourth bonding pads are circular metal bonding pads with the diameter of 0.55mm, and the distance between every two adjacent fourth bonding pads is 1.00 mm;
the solder balls are arranged in a ball grid array mode, and the pitch, the diameter and the height of the solder balls are 1.0mm, 0.5mm and 0.38mm respectively.
2. The 64-way analog quantity acquisition BGA package chip of claim 1, further comprising a molding compound for encapsulating the substrate and the bare chip, wherein the molding compound is an epoxy material and has a size of 18mm x 0.8 mm.
3. The 64-way analog acquisition BGA package chip of claim 1 or 2, wherein the bare chip is electrically connected to each bonding point by a gold wire bonding process; and the bonding point is formed on the surface of the wiring layer through an etching process.
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| CN111653551B (en) * | 2020-06-16 | 2022-06-10 | 西安科技大学 | A BGA chip package structure with high anti-electromagnetic pulse interference capability |
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