CN109406990A - A kind of built-in chip type excess temperature sluggishness protection detection circuit - Google Patents
A kind of built-in chip type excess temperature sluggishness protection detection circuit Download PDFInfo
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H5/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal non-electric working conditions with or without subsequent reconnection
- H02H5/04—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal non-electric working conditions with or without subsequent reconnection responsive to abnormal temperature
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Abstract
本发明公开了一种芯片内置过温迟滞保护检测电路，包括PTAT电压产生电路，迟滞采样电路和温度迟滞检测电路。芯片内置过温迟滞保护检测电路通过基准源产生的温度漂移，利用电阻的分压原理使迟滞采样电路在同一温度下可以输出两个不同的门限电压，而不同的温度下的基准源电压值不同，通过基本的逻辑门电路，判断是否达到过温上限，产生并输出一个带有迟滞特性的控制信号，从而在实现带迟滞特性的过温保护的同时避免产生更多的功耗。本发明的一种芯片内置过温迟滞保护检测电路解决了当前现有技术的芯片工作在非正常温度的苛刻环境造成整个集成电路损坏的技术难题。进一步保护了芯片，具备很强的实用及商用价值。The invention discloses a chip built-in over-temperature hysteresis protection detection circuit, comprising a PTAT voltage generating circuit, a hysteresis sampling circuit and a temperature hysteresis detection circuit. The built-in over-temperature hysteresis protection detection circuit generates temperature drift through the reference source, and the hysteresis sampling circuit can output two different threshold voltages at the same temperature by using the voltage division principle of resistors, and the reference source voltage values at different temperatures are different. , through the basic logic gate circuit, to determine whether the upper limit of the over temperature is reached, and to generate and output a control signal with hysteresis characteristics, so as to avoid generating more power consumption while realizing the over temperature protection with hysteresis characteristics. The chip built-in over-temperature hysteresis protection detection circuit of the present invention solves the technical problem that the chip in the prior art works in a harsh environment with abnormal temperature and causes damage to the entire integrated circuit. It further protects the chip and has strong practical and commercial value.
Description
Technical field
It is more specific to be still not exclusively to a kind of built-in chip type excess temperature sluggishness guarantor the present invention relates to integrated circuit fields
Protect detection circuit.
Background technique
With the rapid development of information technology, circuit integration becomes the important measure for meeting circuit miniaturization, and integrate
The power consumption of the IC chips such as power supply, driver is very big in circuit, once phenomena such as short circuit inside circuit occurs, pole has can
Chip can be burnt, lead to unpredictable loss.In order to avoid the damage of chip, usually it was added in the inside of integrated circuit
Temperature protection circuit, when temperature is more than preset threshold value, thermal-shutdown circuit is started to work, and the functional circuit of chip is made to stop work
Make, additional power consumption will not be increased when chip works normally in this way, and can protect chip.In order to realize the function of overheat protector
Can, usually achieve the purpose that pass through this detection electricity to temperature detection in such a way that temperature signal is converted into voltage signal
Road exports a control signal, realizes the shutdown to the functional circuit of entire chip, but introduce new temperature signal and be converted to
The detection circuit of electric signal can increase to a certain extent the power consumption of chip, and will increase the volume of chip, to improve chip
Cost, and do not have lagging characteristics.For overheat protector, if when chip temperature reaches set temperature, triggering excess temperature is protected
Shield, if can resume work immediately once temperature is lower than setting without temperature hysteresis, then and once again trigger overheat protector, this
Sample, the temperature for finally only resulting in chip are maintained always near overheat protector temperature, can not really be realized in triggering excess temperature
After protection, make chip cooling technique, just resume work, the work of prolonged periods will lead to chip interior under hot operation state
Unpredictable failure occurs for circuit, so as to lead to the paralysis of whole system.If being re-introduced into a cooling recovery, that
, in the design of temperature protection, it is necessary to which a lowest temperature is as recovery temperature, for ensuring the temperature when chip from height
Resume work when temperature drop to low temperature, and this temperature is not triggered when chip temperature is from low-temperature-rise to high temperature.Overheat protector
Triggering temperature and recovery temperature between section, as temperature hysteresis.How reasonably temperature to be detected and exports control
Signal processed is the great difficult problem that those skilled in the art face.One of solution to the problems described above is exactly that will test in circuit
It is placed in chip power module, the power supply of cut-off signals shutdown chip is exported directly in power module, is accurately controlled shutdown
Signal and the circuit for realizing this performance of lagging characteristics are one of those skilled in the art's problems faceds.And excess temperature sluggishness is protected
Shield detection circuit is built in chip interior, largely reduces chip area, cost is greatly saved.
Summary of the invention
In view of one or more problems in the prior art, a kind of built-in chip type excess temperature sluggishness protection detection electricity is provided
Road, comprising:
PTAT voltage generation circuit, have the first power input, second source input terminal, reference voltage output end, partially
Voltage output end is set, the first power input receives positive supply, second source input end grounding, reference voltage output end
One temperature independent reference voltage is provided, bias voltage output be the PMOS tube of rear stage provide one it is identical inclined
Set voltage；
There is sluggish sample circuit the first power input, second source input terminal, bias voltage input, first to adopt
Sample output end, the second sampled output, the first power input receive positive supply, and second source input end grounding is inclined
Set the bias voltage that voltage input end receives the output of PTAT voltage generation circuit bias voltage output, the first sampled output
Restore reference voltage for exporting, the second sampled output is for exporting overheat protector starting voltage；
Temperature hysteresis detection circuit has the first reference voltage input terminal, the second reference voltage input terminal, third with reference to electricity
Input terminal, enabled output end are pressed, the first reference voltage input terminal receives sluggish the first sampled output of sample circuit output
Restore reference voltage, the second reference voltage input terminal receive PTAT voltage generation circuit reference voltage output end output with temperature
Unrelated reference voltage is spent, third reference voltage input terminal receives the excess temperature of sluggish the second sampled output of sample circuit output
Protection starting voltage enables output end output control signal.The PTAT voltage generation circuit, comprising:
First PMOS tube, has grid, source electrode and drain electrode, and source electrode is coupled to the first power input, grid coupling
To bias voltage output；
First PNP bipolar junction transistor, has collector, base stage and emitter, and emitter is coupled to the first PMOS tube
Drain electrode, base stage is coupled to the collector and second source input terminal of the first PNP bipolar junction transistor, and collector is coupled to
The base stage and second source input terminal of first PNP bipolar junction transistor；
Second PMOS tube, has grid, source electrode and drain electrode, and source electrode is coupled to the source electrode and the first power supply of the first PMOS tube
Input terminal, grid are coupled to the grid and bias voltage output of the first PMOS tube；
First resistor has a first end and a second end, and first end is coupled to the drain electrode of the second PMOS tube；
2nd PNP bipolar junction transistor, has collector, base stage and emitter, and emitter is coupled to first resistor
Second end, base stage are coupled to the base stage of the first PNP bipolar junction transistor, the collector of the first PNP bipolar junction transistor, second
The collector and second source input terminal of PNP bipolar junction transistor, collector are coupled to the base of the first PNP bipolar junction transistor
Pole, the collector of the first PNP bipolar junction transistor, the 2nd PNP bipolar junction transistor base stage and second source input terminal；
First operational amplifier, has reverse side, in-phase end and output end, and reverse side is coupled to the leakage of the first PMOS tube
The emitter of pole and the first PNP bipolar junction transistor, in-phase end be coupled to the second PMOS tube drain electrode and first resistor
One end, output end are coupled to the grid and bias voltage output of the grid of the first PMOS tube, the second PMOS tube；
Third PMOS tube, has grid, source electrode and drain electrode, and source electrode is coupled to the source electrode of the first PMOS tube, the 2nd PMOS
The source electrode of pipe and the first power input, grid are coupled to the grid of the first PMOS tube, the grid of the second PMOS tube and first
The output end and bias voltage output of operational amplifier；
Second resistance has a first end and a second end, and first end is coupled to the drain electrode of third PMOS tube, second segment coupling
It is connected to the base stage of the first PNP bipolar junction transistor, collector, the 2nd PNP bipolar junction transistor of the first PNP bipolar junction transistor
Base stage, the 2nd PNP bipolar junction transistor collector and second source input terminal.
The sluggishness sample circuit, comprising:
4th PMOS tube, has grid, source electrode and drain electrode, and source electrode is coupled to the first power input, grid coupling
To bias voltage input；
5th PMOS tube, has grid, source electrode and drain electrode, and source electrode is coupled to the first power input, grid coupling
To the grid and bias voltage input of the 4th PMOS tube；
3rd resistor has a first end and a second end, and first end is coupled to the drain electrode of the 4th PMOS tube, second end coupling
It is connected to the first sampled output；
4th resistance, has a first end and a second end, and first end is coupled to the second end and the first sampling of 3rd resistor
Output end, second end are coupled to second source input terminal；
5th resistance, has a first end and a second end, and first end is coupled to the drain electrode of the 5th PMOS tube, second end coupling
It is connected to the second sampled output；
6th resistance, has a first end and a second end, and first end is coupled to the second end and the second sampling of the 5th resistance
Output end, second end are coupled to the second end and second source input terminal of the 4th resistance.
The temperature hysteresis detection circuit, comprising:
Second operational amplifier has in-phase end, reverse side and output end, and it is defeated that in-phase end is coupled to the first reference voltage
Enter end, reverse side is coupled to the second reference voltage input terminal；
Third operational amplifier, has in-phase end, reverse side and output end, and in-phase end is coupled to second operational amplifier
Reverse side and the second reference voltage input terminal, reverse side is coupled to third reference voltage input terminal；
First phase inverter, has input terminal and output end, and input terminal is coupled to the output end of second operational amplifier；
Second phase inverter, has input terminal and output end, and input terminal is coupled to the output end of third operational amplifier；
First basic RS filpflop, has S input terminal, R input and Q output, and R input is coupled to the first reverse phase
The output end of device, the end S are coupled to the output end of the second phase inverter, and Q output is coupled to enabled output end.
First operational amplifier, which is characterized in that using PMOS as input to the two-level operating amplifier of pipe.
The resistance value R3 of the 3rd resistor, the 4th resistance R4, the 5th resistance resistance value R5 and the 6th resistance resistance
Value R6 substantially meets R3+R4=R5+R6, i.e. the sum of resistance value of the resistance value of 3rd resistor and the 4th resistance is equal to the 5th resistance
Resistance value and the 6th resistance the sum of resistance value.
First sampled output provides the recovery of a temperature hysteresis for the temperature hysteresis detection circuit of rear stage
Signal, second sampled output provide the triggering letter an of overheat protector for the temperature hysteresis detection circuit of rear stage
Number.
The second operational amplifier and third operational amplifier puts the second level operation of pipe as input using PMOS
Big device.
First phase inverter and the second phase inverter, for making the defeated of second operational amplifier and third operational amplifier
It is converted into high level or low level out.
The enabled output end, which is characterized in that available state is in when high level, the signal of output will control chip
Starting or pause.
What a kind of built-in chip type excess temperature sluggishness protection detection circuit provided by the invention can be generated by common a reference source
Temperature drift, two different thresholding electricity can be exported by making sluggish sample circuit at the same temperature using the voltage divider principle of resistance
Pressure, and it is different at a temperature of a reference source voltage value it is different, by basic logic gates, judge whether to reach on excess temperature
Limit generates and exports the control signal for having lagging characteristics, thus while realizing the overheat protector with lagging characteristics
It avoids generating more power consumptions.The chip operation for solving currently existing technology causes entirely in the harsh environment of improper temperature
The technical problem of integrated circuit damage.Chip is further protected, has very strong practical and commercial value.
Detailed description of the invention
The specific embodiment that the present invention will be described in detail below with reference to the accompanying drawings, wherein identical appended drawing reference indicates identical
Component or feature.
Fig. 1 shows a kind of built-in chip type excess temperature sluggishness protection detection circuit module proposed according to an embodiment of the present invention
Schematic diagram；
Fig. 2 shows the PTAT voltage generation circuit schematic diagrames proposed according to an embodiment of the present invention；
Fig. 3 shows the sluggish sample circuit schematic diagram proposed according to an embodiment of the present invention；
Fig. 4 shows the temperature hysteresis detection circuit schematic diagram proposed according to an embodiment of the present invention；
Fig. 5 shows the built-in chip type excess temperature sluggishness protection detection circuit temperature difference proposed according to an embodiment of the present invention
Voltage difference schematic diagram；
The sluggishness that Fig. 6 shows the built-in chip type excess temperature sluggishness protection detection circuit proposed according to an embodiment of the present invention is special
Property verifying schematic diagram.
Specific embodiment
Specific embodiment below represents exemplary embodiment of the present invention, and substantially merely illustrative explanation rather than
Limitation.In the following description, in order to provide a thorough understanding of the present invention, a large amount of specific details are elaborated.However, for ability
Domain those of ordinary skill it is evident that: these specific details are not required for the present invention.In other instances,
In order to avoid obscuring the present invention, well known circuit, material or method are not specifically described.
In the description, it is specific described in the embodiment to refer to that " one embodiment " or " embodiment " means to combine
Feature, structure or characteristic are included at least one embodiment of the present invention.Term " in one embodiment " is in specification
In each position occur not all referring to identical embodiment, nor mutually exclusive other embodiments or variable implementing
Example.All features disclosed in this specification or disclosed all methods or in the process the step of, in addition to mutually exclusive feature
And/or other than step, it can combine in any way.In addition, it should be understood by one skilled in the art that provided herein
Diagram is provided to the purpose of explanation, and diagram is not necessarily drawn to scale.It should be appreciated that when claiming " element " " connection
To " or when " coupled " to another element, it, which can be, is directly connected or coupled to another element or there may be intermediary elements.
On the contrary, intermediary element is not present when claiming element " being directly connected to " or " being directly coupled to " another element.Identical attached drawing mark
Note indicates identical element.It when title " element " " reception " a certain signal, can make directly to receive, switch, electricity can also be passed through
Resistance, level displacement shifter, signal processing unit etc. receive.Term "and/or" used herein includes that one or more correlations are listed
Project any and all combinations.
A kind of built-in chip type excess temperature sluggishness protection detection circuit module signal that Fig. 1 is proposed according to an embodiment of the present invention
Figure, comprising: PTAT voltage generation circuit module, sluggish sample circuit module, temperature hysteresis detection circuit module.
The PTAT voltage generation circuit has the first power input (Vdd), second source input terminal (GND), benchmark
Voltage output end (Vref), bias voltage output (Vb), the first power input receive positive supply, second source input
End ground connection, reference voltage output end provide a temperature independent reference voltage, and bias voltage output is rear stage
PMOS tube provide an identical bias voltage；
The sluggishness sample circuit, has the first power input (Vdd), second source input terminal (GND), bias voltage
Input terminal (Vb), the first sampled output (Vref_low), the second sampled output (Vref_high), the first power input
End receives positive supply, second source input end grounding, and bias voltage input receives PTAT voltage generation circuit biased electrical
The bias voltage of output end output is pressed, the first sampled output restores reference voltage, the second sampled output for exporting
For exporting overheat protector starting voltage；
The temperature hysteresis detection circuit has the first reference voltage input terminal (Vref_low), the second reference voltage defeated
Enter end (Vref), third reference voltage input terminal (Vref_high), enabled output end (Signal_EN), the first reference voltage
Input terminal receives the recovery reference voltage of sluggish the first sampled output of sample circuit output, and the second reference voltage input terminal connects
Receive the temperature independent reference voltage of PTAT voltage generation circuit reference voltage output end output, the input of third reference voltage
The overheat protector that end receives sluggish the second sampled output of sample circuit output starts voltage, enables output end output control letter
Number.
Wherein, PTAT voltage generation circuit module provides the output of a reference voltage for whole system, and when temperature
When degree changes, a reference source voltage of PTAT voltage generation circuit can also change therewith, and sluggish sample circuit module, then lead to
The partial pressure to the different resistance values of a reference source voltage is crossed, the overturning threshold voltage of overheat protector is formed and restores voltage, to realize temperature
Degree lagging characteristics are prepared, and temperature hysteresis detection circuit module is realized by being compared to the signal of input with sluggishness
The overheat protector of characteristic acts on.
The PTAT voltage generation circuit schematic diagram that Fig. 2 is proposed according to an embodiment of the present invention, comprising: the first PMOS tube
(M1), the first PNP bipolar junction transistor (Q1), the second PMOS tube (M2), first resistor (R1), the 2nd PNP bipolar junction transistor
(Q2), the first operational amplifier (OP1), third PMOS tube (M3), second resistance (R2).
The PTAT voltage generation circuit, comprising: the first PMOS tube has grid, source electrode and drain electrode, and source electrode is coupled to
First power input, grid are coupled to bias voltage output；First PNP bipolar junction transistor has collector, base stage
And emitter, emitter are coupled to the drain electrode of the first PMOS tube, base stage is coupled to the current collection of the first PNP bipolar junction transistor
Pole and second source input terminal, collector are coupled to the base stage and second source input terminal of the first PNP bipolar junction transistor；The
Two PMOS tube have grid, source electrode and drain electrode, and source electrode is coupled to the source electrode and the first power input of the first PMOS tube,
Grid is coupled to the grid and bias voltage output of the first PMOS tube；First resistor, have first segment and second end, first
End is coupled to the drain electrode of the second PMOS tube；2nd PNP bipolar junction transistor has collector, base stage and emitter, emitter
It is coupled to the second end of first resistor, base stage is coupled to the base stage of the first PNP bipolar junction transistor, the first ambipolar crystalline substance of PNP
The collector and second source input terminal of the collector of body pipe, the 2nd PNP bipolar junction transistor, collector are coupled to first
The base stage of PNP bipolar junction transistor, the collector of the first PNP bipolar junction transistor, the 2nd PNP bipolar junction transistor base stage and
Second source input terminal；First operational amplifier, has reverse side, in-phase end and output end, and reverse side is coupled to first
The drain electrode of PMOS tube and the emitter of the first PNP bipolar junction transistor, in-phase end are coupled to the drain electrode and the of the second PMOS tube
The first end of one resistance, output end are coupled to the grid and bias voltage output of the grid of the first PMOS tube, the second PMOS tube；
Third PMOS tube, has grid, source electrode and drain electrode, and source electrode is coupled to the source electrode of the source electrode of the first PMOS tube, the second PMOS tube
With the first power input, grid is coupled to the grid of the first PMOS tube, the grid of the second PMOS tube and the first operation amplifier
The output end and bias voltage output of device；Second resistance has a first end and a second end, and first end is coupled to the 3rd PMOS
The drain electrode of pipe, second segment be coupled to the base stage of the first PNP bipolar junction transistor, the first PNP bipolar junction transistor collector,
The collector and second source input terminal of the base stage of 2nd PNP bipolar junction transistor, the 2nd PNP bipolar junction transistor.Described
First operational amplifier uses two-level operating amplifier of the PMOS as input to pipe.
For generation negative temperature coefficient voltage, the base emitter voltage of bipolar transistor, or more generally say,
The forward voltage that PN saves diode has negative temperature coefficient.By taking NPN as an example:
Wherein VTFor thermal voltage equivalent, VT=kT/q；K is Boltzmann constant, and T is thermodynamic temperature, and q is electron charge
Amount.Is is reverse phase saturation current, μ ∝ μ0Tm, m takes -3/2, and, wherein the conduction band of elemental silicon and the energy of valence band and difference are about
1.12eV。
In formula (2), b is the constant of a fixed proportion.VbeTo temperature T derivation, it is assumed that ICIt is temperature independent, then:
In conjunction with formula (1), can obtain:
So:
By formula (3) and formula (5), can obtain:
By formula (4-6) it is found that VbeTemperature coefficient and VbeSize it is related.For positive temperature coefficient voltage, if
The work of two transistors is under unequal current density, then the difference of their base emitter voltage is just and absolute temperature
It is directly proportional and unrelated with collector current, to constitute PTAT structure.
At room temperature, VbeTemperature coefficient be -1.5mV/K, the temperature coefficient of Δ Vbe is 0.087mV/K.So, to positive temperature
Degree coefficient and negative temperature coefficient voltage term are weighted summation:
VREF=Vbe+αVT lnn (7)
Wherein, as α VTlnn ≈ 17.2, the voltage of available zero-temperature coefficient, V at this timeREF=1.25V.
And on its basis, by allowing PTAT current to flow through resistance, so that it may obtain a PTAT voltage.PMOS is added to make
To input the performance that two pole operational amplifiers of pipe can be improved with PTAT voltage.
The sluggish sample circuit schematic diagram that Fig. 3 is proposed according to an embodiment of the present invention, comprising: the 4th PMOS tube (M4),
5th PMOS tube (M5), 3rd resistor (R3), the 4th resistance (R4), the 5th resistance (R5), the 6th resistance (R6).
The sluggishness sample circuit, comprising: the 4th PMOS tube has grid, source electrode and drain electrode, and source electrode is coupled to first
Power input, grid are coupled to bias voltage input；5th PMOS tube has grid, source electrode and drain electrode, source electrode coupling
It is connected to the first power input, grid is coupled to the grid and bias voltage input of the 4th PMOS tube；3rd resistor has
First end and second end, first end are coupled to the drain electrode of the 4th PMOS tube, and second end is coupled to the first sampled output；The
Four resistance, have a first end and a second end, and first end is coupled to the second end and the first sampled output of 3rd resistor, the
Two ends are coupled to second source input terminal；5th resistance, has a first end and a second end, and first end is coupled to the 5th PMOS tube
Drain electrode, second end is coupled to the second sampled output；6th resistance, has a first end and a second end, first end coupling
To the second end and the second sampled output of the 5th resistance, second end be coupled to the 4th resistance second end and second source it is defeated
Enter end.Resistance value R3, the 4th resistance R4, the resistance value R5 of the 5th resistance and the resistance value of the 6th resistance of the 3rd resistor
R6 substantially meets R3+R4=R5+R6, i.e. the sum of resistance value of the resistance value of 3rd resistor and the 4th resistance is equal to the 5th resistance
The sum of the resistance value of resistance value and the 6th resistance；First sampled output provides one for the temperature hysteresis detection circuit of rear stage
The recovery signal of a temperature hysteresis, second sampled output provide a mistake for the temperature hysteresis detection circuit of rear stage
The trigger signal of temperature protection.
After the PTAT voltage obtained by PTAT voltage generation circuit, acted on using the partial pressure of Resistance versus voltage, to PTAT
Suitable tap is arranged in voltage.
Start from there, one embodiment of the invention will be with canonical reference voltage 1.2V, 85 DEG C of threshold temperature and sluggishness temperature
For 65 DEG C of degree, the working principle of its sluggishness sampling is elaborated.
By the way that suitable voltage value is arranged to 3rd resistor, the 4th resistance, the 5th resistance, the 6th resistance in Fig. 3, meets and close
It is R3+R4=R5+R6, i.e., the sum of resistance value of the resistance value of 3rd resistor and the 4th resistance is equal to the resistance value of the 5th resistance and the 6th electricity
The sum of resistance value of resistance is guaranteed under the same bias voltage and the same power input voltage, the current value of two branches with this
It is almost equal, guarantee the accuracy of sampling.
The temperature hysteresis detection circuit schematic diagram that Fig. 4 is proposed according to an embodiment of the present invention, comprising: the second operation amplifier
Device (OP2), third operational amplifier (OP3), the first phase inverter (INV1), the second phase inverter (INV2), the first basic RS triggering
Device (RS1).
The temperature hysteresis detection circuit, comprising: second operational amplifier has in-phase end, reverse side and output end,
In-phase end is coupled to the first reference voltage input terminal, and reverse side is coupled to the second reference voltage input terminal；Third operation amplifier
Device, has in-phase end, reverse side and output end, and in-phase end is coupled to the reverse side and second of second operational amplifier with reference to electricity
Input terminal is pressed, reverse side is coupled to third reference voltage input terminal；First phase inverter has input terminal and output end, defeated
Enter the output end that end is coupled to second operational amplifier；Second phase inverter, has input terminal and output end, and input terminal is coupled to
The output end of third operational amplifier；First basic RS filpflop has S input terminal, R input and Q output, R input
End is coupled to the output end of the first phase inverter, and the end S is coupled to the output end of the second phase inverter, and Q output is coupled to enabled
Output end.The second operational amplifier and third operational amplifier puts the second level operation of pipe as input using PMOS
Big device；First phase inverter and the second phase inverter, for making the output of second operational amplifier and third operational amplifier
It is converted into high level or low level；The enabled output end, available state is in when high level, and the signal of output will control chip
Starting or pause.
Realization about circuit lagging characteristics, it usually needs using the operational amplifier of the full input range of rail-to-rail, but benefit
It is larger with such circuit design difficulty.So making the realization of temperature hysteresis characteristic using the holding step response of basic RS filpflop.
Wherein, rest-set flip-flop is realized by nor gate.
Three input end signals of detection circuit are originated from band-gap reference, and operational amplifier is using PMOS as input to pipe
Second level amplifier, pass through sufficiently high gain guarantee comparator sensitivity.Wherein, the second reference voltage input terminal is originated from PTAT
Voltage generation circuit, the threshold voltage as comparator overturning.First reference voltage and third reference voltage be with temperature at than
The reference voltage of example is originated from the first sampled output and the second sampled output, reaches 1.2V in 65 DEG C, 85 DEG C respectively.Simultaneously
Because the first reference voltage and the second reference voltage are PTAT voltage, temperature coefficient having the same is can guarantee in this way 65
DEG C when, the first reference voltage be equal to 1.2V, the second reference voltage be less than 1.2V, at 85 DEG C, the first reference voltage be greater than 1.2V,
Second reference voltage is equal to 1.2V.
In amplifier output end and rest-set flip-flop input terminal, it is inserted into phase inverter, mainly the output of operational amplifier is carried out
Shaping does binary conversion treatment to the output of amplifier, shortens amplifier and exported rising edge/failing edge temperature range, at the same prevent because
The output of amplifier near threshold voltage, is causing trigger to fall into indefinite state just, and generation is accidentally turned over.
The built-in chip type excess temperature sluggishness that Fig. 5 is proposed according to an embodiment of the present invention protects detection circuit temperature difference voltage
Difference schematic diagram, available from Fig. 4, the first reference voltage reaches 1.2V threshold voltage at 65 DEG C, and the first reference voltage exists
Reach 1.2V threshold voltage at 85 DEG C.
The lagging characteristics that Fig. 6 shows the built-in chip type excess temperature sluggishness protection detection circuit of one embodiment of the invention proposition are tested
Schematic diagram is demonstrate,proved, it is available from Fig. 5, it enables output end at different temperatures, there is fine temperature hysteresis characteristic.Chip temperature
When raising, at 85 DEG C, enable signal is pulled low, and chip stops working.When temperature drops to 65 DEG C, enable signal is just again
Restore high level, resumes work again.It will be appreciated from fig. 6 that a kind of built-in overheat protector observation circuit proposed by the present invention has very much
Protection circuit work in effect ground has well solved the chip operation of currently existing technology improper within the scope of normal temperature
The harsh environment of temperature causes the technical problem of entire integrated circuit damage.
In this disclosure used quantifier "one", "an" etc. be not excluded for plural number." first " in text, "
Two " etc. are merely represented in the sequencing occurred in the description of embodiment, in order to distinguish like." first ", " second " exist
Appearance in claims is only for the purposes of the fast understanding to claim rather than in order to be limited.Right is wanted
Any appended drawing reference in book is asked to should be construed as the limitation to range.
Claims (10)
1. a kind of built-in chip type excess temperature sluggishness protects detection circuit, comprising:
PTAT voltage generation circuit has the first power input, second source input terminal, reference voltage output end, biased electrical
Output end is pressed, the first power input receives positive supply, second source input end grounding, and reference voltage output end provides
One temperature independent reference voltage, bias voltage output provide an identical biased electrical for the PMOS tube of rear stage
Pressure；
Sluggish sample circuit has the first power input, second source input terminal, bias voltage input, the first sampling defeated
Outlet, the second sampled output, the first power input receive positive supply, second source input end grounding, biased electrical
Input terminal is pressed to receive the bias voltage of PTAT voltage generation circuit bias voltage output output, the first sampled output is used for
Output restores reference voltage, and the second sampled output is for exporting overheat protector starting voltage；
Temperature hysteresis detection circuit has the first reference voltage input terminal, the second reference voltage input terminal, third reference voltage defeated
Enter end, enabled output end, the first reference voltage input terminal receives the recovery of sluggish the first sampled output of sample circuit output
Reference voltage, the second reference voltage input terminal receive PTAT voltage generation circuit reference voltage output end output with temperature without
The reference voltage of pass, third reference voltage input terminal receive the overheat protector of sluggish the second sampled output of sample circuit output
Start voltage, enables output end output control signal.
2. a kind of built-in chip type excess temperature sluggishness protection detection circuit according to claim 1, which is characterized in that the PTAT
Voltage generation circuit, comprising:
First PMOS tube has grid, source electrode and drain electrode, and source electrode is coupled to the first power input, and grid is coupled to partially
Set voltage output end；
First PNP bipolar junction transistor, has collector, base stage and emitter, and emitter is coupled to the leakage of the first PMOS tube
Pole, base stage are coupled to the collector and second source input terminal of the first PNP bipolar junction transistor, and collector is coupled to first
The base stage and second source input terminal of PNP bipolar junction transistor；
Second PMOS tube, has grid, source electrode and drain electrode, and source electrode is coupled to the source electrode and the first power input of the first PMOS tube
End, grid are coupled to the grid and bias voltage output of the first PMOS tube；
First resistor has a first end and a second end, and first end is coupled to the drain electrode of the second PMOS tube；
2nd PNP bipolar junction transistor, has collector, base stage and emitter, and emitter is coupled to the second of first resistor
End, base stage are coupled to collector, the 2nd PNP of the base stage of the first PNP bipolar junction transistor, the first PNP bipolar junction transistor
The collector and second source input terminal of bipolar junction transistor, collector be coupled to the first PNP bipolar junction transistor base stage,
The base stage and second source input terminal of the collector of first PNP bipolar junction transistor, the 2nd PNP bipolar junction transistor；
First operational amplifier, have reverse side, in-phase end and output end, reverse side be coupled to the first PMOS tube drain electrode and
The emitter of first PNP bipolar junction transistor, in-phase end are coupled to the drain electrode of the second PMOS tube and the first end of first resistor,
Its output end is coupled to the grid and bias voltage output of the grid of the first PMOS tube, the second PMOS tube；
Third PMOS tube, has grid, source electrode and drain electrode, and source electrode is coupled to the source electrode of the first PMOS tube, second PMOS tube
Source electrode and the first power input, grid are coupled to the grid of the first PMOS tube, the grid of the second PMOS tube and the first operation
The output end and bias voltage output of amplifier；
Second resistance has a first end and a second end, and first end is coupled to the drain electrode of third PMOS tube, and second segment is coupled to
The base stage of first PNP bipolar junction transistor, the collector of the first PNP bipolar junction transistor, the 2nd PNP bipolar junction transistor base
Pole, the 2nd PNP bipolar junction transistor collector and second source input terminal.
3. a kind of built-in chip type excess temperature sluggishness according to claim 1 protects detection circuit, which is characterized in that the sluggishness
Sample circuit, comprising:
4th PMOS tube has grid, source electrode and drain electrode, and source electrode is coupled to the first power input, and grid is coupled to partially
Set voltage input end；
5th PMOS tube has grid, source electrode and drain electrode, and source electrode is coupled to the first power input, and grid is coupled to the
The grid and bias voltage input of four PMOS tube；
3rd resistor has a first end and a second end, and first end is coupled to the drain electrode of the 4th PMOS tube, and second end is coupled to
First sampled output；
4th resistance, has a first end and a second end, and first end is coupled to the second end and the first sampling output of 3rd resistor
End, second end are coupled to second source input terminal；
5th resistance, has a first end and a second end, and first end is coupled to the drain electrode of the 5th PMOS tube, and second end is coupled to
Second sampled output；
6th resistance, has a first end and a second end, and first end is coupled to the second end and the second sampling output of the 5th resistance
End, second end are coupled to the second end and second source input terminal of the 4th resistance.
4. a kind of built-in chip type excess temperature sluggishness according to claim 1 protects detection circuit, which is characterized in that the temperature
Sluggish detection circuit, comprising:
Second operational amplifier, has in-phase end, reverse side and output end, and in-phase end is coupled to the input of the first reference voltage
End, reverse side are coupled to the second reference voltage input terminal；
Third operational amplifier, has in-phase end, reverse side and output end, and in-phase end is coupled to the anti-of second operational amplifier
Phase end and the second reference voltage input terminal, reverse side are coupled to third reference voltage input terminal；
First phase inverter, has input terminal and output end, and input terminal is coupled to the output end of second operational amplifier；
Second phase inverter, has input terminal and output end, and input terminal is coupled to the output end of third operational amplifier；
First basic RS filpflop, has S input terminal, R input and Q output, and R input is coupled to the first phase inverter
Output end, the end S are coupled to the output end of the second phase inverter, and Q output is coupled to enabled output end.
5. a kind of built-in chip type excess temperature sluggishness according to claim 2 protects detection circuit, which is characterized in that described the
One operational amplifier, which is characterized in that using PMOS as input to the two-level operating amplifier of pipe.
6. a kind of built-in chip type excess temperature sluggishness according to claim 3 protects detection circuit, which is characterized in that described the
Resistance value R3, the 4th resistance R4, the resistance value R5 of the 5th resistance and the resistance value R6 of the 6th resistance of three resistance substantially meet
The sum of resistance value of R3+R4=R5+R6, the i.e. resistance value of 3rd resistor and the 4th resistance is equal to the resistance value and the 6th resistance of the 5th resistance
The sum of resistance value.
7. a kind of built-in chip type excess temperature sluggishness according to claim 3 protects detection circuit, which is characterized in that described the
One sampled output provides the recovery signal an of temperature hysteresis for the temperature hysteresis detection circuit of rear stage, and described second adopts
Sample output end provides the trigger signal of an overheat protector for the temperature hysteresis detection circuit of rear stage.
8. a kind of built-in chip type excess temperature sluggishness according to claim 4 protects detection circuit, which is characterized in that described the
Two operational amplifiers and third operational amplifier, using PMOS as input to the two-level operating amplifier of pipe.
9. a kind of built-in chip type excess temperature sluggishness according to claim 4 protects detection circuit, which is characterized in that described the
One phase inverter and the second phase inverter, for make the output of second operational amplifier and third operational amplifier be converted into high level or
Low level.
10. a kind of built-in chip type excess temperature sluggishness according to claim 4 protects detection circuit, which is characterized in that described
Enabled output end, when high level, are in available state, and the signal of output will control the starting or pause of chip.
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|---|---|---|---|
| CN201811462919.7A CN109406990A (en) | 2018-12-03 | 2018-12-03 | A kind of built-in chip type excess temperature sluggishness protection detection circuit |
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| CN201811462919.7A CN109406990A (en) | 2018-12-03 | 2018-12-03 | A kind of built-in chip type excess temperature sluggishness protection detection circuit |
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Application publication date: 20190301 |