CN109391604A - A kind of bridge-set and management system managing data input and output agreement - Google Patents

Abstract

Embodiments of the present invention disclose a bridging device and a management system for managing data input and output protocols. The bridging device includes: a first connector, a distributor, and at least one second connector; the first connector is connected to the The distributor is connected to receive management data input and output protocol information, and convert the received information into communication protocol information for parallel transmission; the distributor is connected to the at least one second connector and is used to connect the The communication protocol information is distributed to the at least one second connector; the at least one second connector is used to convert the internal protocol into the management data input and output protocol information and output, and manage and The at least one second connector is connected to the target device.

Description

A bridge device and management system for managing data input and output protocols

technical field

The invention relates to bridging technology, in particular to a bridging device for managing data input and output protocols.

Background technique

In the context of more and more network applications, devices based on Ethernet protocols (such as IEEE802.3, IEEE802.3ba and IEEE802.3u) formulated by the Institute of Electrical and Electronics Engineers (IEEE) are becoming more and more More and more, there are more and more physical layer (PHY, Physical Layer) chips inside a single chip or PHY chips on a single board, which are compatible with Ethernet protocols and support management data input and output (MDIO, Management Data Input/Output). ) interface protocol is also more and more PHY chips, therefore, it is particularly important to realize the unified management of multiple PHY chips through the MDIO interface.

The MDIO interface realizes the management of multiple PHY chips. It is necessary to distribute the MDIO sent by the management device to multiple PHY chips. After the PHY chip receives the above information, the management of the PHY chip is realized through the internal MDIO interface, as shown in Figure 1. , when more PHY chips need to be managed, the working rate of managing PHY chips will be limited. For the broadband high-speed Ethernet, how to manage more PHY chips while ensuring the working rate, there is no effective solution in related technologies.

SUMMARY OF THE INVENTION

In view of this, the embodiments of the present invention expect to provide a bridge device and a management system for managing data input and output protocols, so as to manage more PHY chips while ensuring the working rate.

In order to achieve the above-mentioned purpose, the technical scheme of the embodiment of the present invention is realized as follows:

An embodiment of the present invention provides a bridging device for managing data input and output protocols, including: a first connector, a distributor, and at least one second connector; wherein,

The first connector is connected to the distributor, and is used for receiving management data input and output protocol information, and converting the received information into parallel transmission communication protocol information;

the distributor, connected to the at least one second connector, for distributing the communication protocol information to the at least one second connector;

The at least one second connector is configured to convert the internal protocol into the management data input/output protocol information and output it, and manage the target device connected to the at least one second connector according to the output information.

In the above solution, the distributor includes at least one register for buffering and managing data information of the target device.

In the above solution, the communication protocol information includes the data information and the access address;

The first connector includes a first data terminal and an address terminal; wherein,

The address terminal is used to access the corresponding register according to the access address;

The data terminal is used for transmitting the data information to the register buffer.

In the above solution, the at least one second connector includes a management terminal; wherein,

The management terminal is connected to the target device, and is used for transmitting the management data input and output protocol information to the target device, and manages the target device according to the output information.

In the above scheme, the distributor includes an address conversion terminal and a read-write terminal; wherein,

the address conversion terminal, configured to convert the address transmitted by the first connector into an access address of the target device;

The read-write terminal is used to read the data in the register for the target device, and transmit the data to the second connector.

In the above solution, the distributor includes a data selector for selecting a target register from the at least one register according to the received selection instruction.

In the above solution, the first connector, the distributor and the at least one second connector all include a clock control terminal and a reset terminal; wherein,

The clock control terminal is used to receive clock control information, and the clock control information is used to control the working state;

The reset terminal is used to receive reset information, and the reset information is used to control reset.

In the above scheme, the distributor includes a rate control terminal and a state query terminal; wherein,

the rate control terminal, used to control the working rate of the target device connected to the at least one second connector;

The status query terminal is configured to query the status information of the target device connected to the at least one second connector.

In the above solution, the first connector includes a protocol conversion module for converting the management data input and output protocol information into the communication protocol information.

In the above solution, the first connector and the at least one second connector include: an enabling terminal for transmitting an enabling signal, and controlling the input and output of information according to the enable signal.

An embodiment of the present invention further provides a management system, including: a bridge device, a management device, and at least one target device; wherein,

The management device, connected to the bridge device, is configured to generate and output management data input and output protocol information, and manage the at least one target device according to the output information;

The bridging device, connected to the at least one target device, is configured to receive the management data input and output protocol information, convert the received information into parallel communication protocol information; perform multiple distribution of the communication protocol information, Converting the distributed information into multiplexed management data input and output protocol information;

The at least one target device is configured to receive the management data input and output protocol information transmitted by the bridge device, and perform corresponding management operations according to the received information.

In the above solution, the target device is a physical layer chip or the bridge device at the next level.

By implementing the solution of the embodiment of the present invention, the received MDIO protocol information can be converted into parallel internal communication protocol information, and then the internal communication protocol information can be distributed to different second connectors, and the internal communication protocol information can be distributed through the second connectors. The communication protocol information is converted into multi-channel MDIO protocol information for output, so as to realize the unified management of multiple devices supporting the MDIO protocol; in addition, the working rates between the second connectors are independent of each other, which avoids the target The device is completely limited to the lowest MDIO rate, thus increasing the working rate of unified management.

Description of drawings

1 is a schematic diagram of multiple device connections of a kind of MDIO provided by the implementation of the present invention;

2 is a schematic diagram of a MAC sublayer, a PHY layer, and a MII between the two layers in an OSI reference model provided by an embodiment of the present invention;

3 is a schematic structural diagram of a bridge device of an MDIO protocol provided by the implementation of the present invention;

4 is a schematic structural diagram of a bridge device of another MDIO protocol provided by the implementation of the present invention;

FIG. 5 is a schematic diagram of the composition and structure of a first connector provided by the implementation of the present invention;

FIG. 6 is a schematic diagram of the composition and structure of a dispenser provided by the implementation of the present invention

FIG. 7 is a schematic diagram of the composition and structure of a second connector provided by the implementation of the present invention;

FIG. 8 is a schematic diagram of the composition and structure of a management system provided by the implementation of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Before the present invention is further described in detail, the terms and terms involved in the embodiments of the present invention are described. The terms and terms involved in the embodiments of the present invention are applicable to the following explanations.

1) MDIO, MDIO is a simple two-wire serial interface that connects management devices (such as MAC devices, microprocessors) with a PHY chip with management functions, thereby realizing the management of the PHY chip.

2) PHY refers to the physical layer. The chip with PHY function can communicate with external devices. Among them, the PHY chip has a standard management interface that conforms to the 22nd paragraph of the IEEE802.3u standard, that is, the media independent interface (MII, MediaIndepended Interface) , also known as MII management interface, this interface includes two interfaces: Metadata Distributor (MDC, MetaData Controller) and MDIO. Among them, the MDC interface is the clock input of the management data, that is, the input is the clock signal, and the maximum rate can reach 8.3 megahertz (MHz); the MDIO is the input and output bidirectional interface of the management data, that is, the input is the MDIO protocol information.

Ethernet (Ethernet) is a computer local area network networking technology, based on the IEEE 802.3 standard formulated by IEEE, which specifies the content of the physical layer connection, electrical signal and media access control (MAC, Media Access Control) sub-layer protocol. . For the Ethernet interface, its essence is the process that the device of the MAC sublayer controls the PHY chip or device through the MII bus.

With reference to FIG. 2 , FIG. 2 is a schematic diagram of a MAC sublayer, a PHY layer, and an MII between the two layers in an OSI reference model provided by an embodiment of the present invention.

1) MAC sublayer

The MAC protocol is located in a sublayer of the data link layer in the OSI seven-layer protocol, and is mainly responsible for controlling and connecting the physical medium of the physical layer. When sending data, the MAC protocol can determine in advance whether the data can be sent. If it can be sent, it will add some control information to the data, and finally send the data and control information to the physical layer in a specified format; when receiving data, the MAC The protocol first judges the input information and whether there is a transmission error. If there is no error, the control information is removed and sent to the Logical Link Control (LLC, Logical Link Control) sublayer. Ethernet MAC is defined by the IEEE-802.3 Ethernet standard.

2) MII management interface

The MII management interface is the media independent interface. "Media independent" means that any type of PHY device can work normally without redesigning or replacing the MAC hardware.

The MII management interface transmits data bidirectionally in a 4-bit (bit), ie nibble mode. When the clock rate is 25MHz, its working rate can reach 100Mb/s. The MII management interface is a dual-signal interface, one is the clock signal, that is, the MDC signal; the other is the data signal, that is, the MDIO signal. Through the MII management interface, the upper layer can monitor and control the PHY chip; Speed, duplex capability, etc.) are reflected in the registers, and the MAC device obtains its current state by reading and writing the registers of the PHY chip through the Serial Management Interface (SMI, Serial Management Interface); in addition, it can also read the corresponding instructions in the registers, Realize the control of the PHY chip. The control of the PHY chip can also be achieved by setting the registers of the PHY through the SMI to achieve the purpose of control, such as opening and closing the flow control, auto-negotiation mode or forced mode, etc.

The Reduced Media Independant Interface (RMII, Reduced Media Independant Interface) is one of the standard Ethernet interfaces and has fewer input/output (I/O, Input/Output) outputs than MII.

The Gigabit Medium Independent Interface (GMII, Gigabit Medium Independent Interface) is the MII management interface of the Gigabit network.

About the difference between RMII management interface, GMII management interface and MII port: RMII management interface uses 2 wires to transmit data, MII management interface uses 4 wires to transmit data, and GMII connection uses 8 wires to transmit data.

MII/RMII is an interface. For 10M line speed, the clock of MII is 2.5M, and the clock of RMII is 5M; for 100M line speed, the clock of MII is 25M, and the clock of RMII is 50M.

3) PHY layer

PHY includes MII/GMII sublayer, Physical Code Sublayer (PCS, Physical Code Sublayer), Physical Media Attachment (PMA, Physical Media Attachment) sublayer, Physical Medium Dependent (PMD, Physical MediumDependent) sublayer, Medium Dependent Interface (MDI) , Medium Dependent Interface) sublayer.

For the baseband transmission (100BaseTX) signal with a transmission rate of 100 megabits per second (Mbit/s), 4B/5B encoding is used. When the PHY chip or device receives the data from the MAC, when sending data, it will increase by 1 bit for every 4 bits. Error detection code, and then convert the parallel data into serial stream data, and then encode the data according to the coding rules of the physical layer, and then convert the data into an analog signal to send the data. When the PHY chip or device is receiving data, the process is opposite to that of sending data. In addition, PHY can also implement some functions of Carrier Sense Multiple Access with Collision Detection (CSMA/CD, Carrier Sense Multiple Access with Collision Detection) to detect whether there is data being transmitted on the network, if so, wait and continue to detect; No, then wait for a random time to send the data. Here, the above random time is not a constant, but the random time calculated at different times is different, and there are multiple algorithms to deal with the two data with low probability of occurrence. A second conflict between hosts.

The data interaction between the PHY and the MAC is implemented through a standard defined by IEEE, that is, the MII management interface connects the MAC and the PHY, and the MII management interface transmits all data and data control of the network. The MAC determines the working state of the PHY and controls the PHY by using a serial management interface (SMI, Serial Management Interface) by reading and writing the registers of the PHY. In addition, the PHY reflects its current status into the register, and the MAC continuously reads the status register of the PHY through the SMI bus to know the current status of the PHY, such as connection speed, duplex capability, etc.

Under the background of more and more extensive network applications, more and more devices based on Ethernet protocol, PHY chips compatible with Ethernet protocol and supporting MDIO interface protocol are also increasing. For management, the MDIO and MDC sent by the main control device need to be distributed to multiple PHY chips respectively. After the PHY chip receives the above information, the management of the PHY chip is realized through the internal MDIO interface, as shown in Figure 1. When more PHY chips need to be managed, the overall operating rate of the interface cannot be higher than the lowest rate among the connected devices, so the operating rate will be limited. To this end, an embodiment of the present invention proposes a solution, as shown in FIG. 3 , which is a schematic structural diagram of a bridge device 300 of an MDIO protocol provided by the implementation of the present invention, wherein the bridge device 300 can pass the first management data ( The S_MDI) interface receives the MDIO protocol information sent by the external device, converts the received information into parallel communication protocol information, then distributes the communication protocol information in multiple ways, and converts the distributed information into multi-channel MDIO protocol information, Then, the converted MDIO protocol information is output through the second management data (Mi_MDI) interface, where i=0, 1, 2, ..., n (n is a non-negative integer).

Therefore, through the bridging device 300 in the embodiment of the present invention, one channel of MDIO protocol information sent by an external device is converted into multiple channels of MDIO protocol information, thereby realizing management or control of multiple PHY chips; in addition, the Mi_MDI interface can By connecting PHY chips, it is also possible to cascade bridge devices at the next level, so that a larger number of PHY chips can be managed or controlled.

So far, the overall work of the bridging device 300 has been introduced. Here, with reference to FIG. 4 , the realized functions are explained from the internal structure of the bridging device 300. FIG. Including: a first connector 310, a dispenser 320 and at least one second connector 330; wherein,

The first connector 310, connected to the distributor 320, is used for receiving management data input and output protocol information, and converting the received information into parallel transmission communication protocol information;

a distributor 320, connected to the at least one second connector 330, for distributing the communication protocol information to the at least one second connector 330;

The at least one second connector 330 is used to convert the internal protocol into management data input and output protocol information and output it, and manage the target device connected to the at least one second connector 330 according to the output information.

5, the internal structure and function of the first connector 310 will be described. FIG. 5 is a schematic structural diagram of a first connector 310 provided by the implementation of the present invention, including: a clock control (WCLK) terminal, a reset (Reset) end, PHY identification (ID) end, metadata control (S_MDC) end, enable (S_OEN) end, management data input (S_MDI) end, management data output (S_MDO) end, port selection (Port) end, address (Addr ) end, read and write control (OP) end, management data output (DATA_O) end and management data input (DATA_I) end; wherein, the S_MDI end and the S_MDO end constitute the data end described in the embodiments of the present invention.

The first connector 310 is used for receiving management data input and output protocol information, and converting the received information into parallel transmission communication protocol information.

Here, the management data input and output protocol information is serial communication information, and the communication protocol information is parallel communication protocol information. The conversion process is mainly to convert the access address, access direction, read and write control instructions and data in the management data input and output protocol information. Information and other information are extracted, therefore, communication protocol information of parallel communication is obtained, wherein the communication protocol information includes information such as data information, access address, read and write control instructions, and access direction. It should be noted that the access direction refers to which target device needs to be accessed, such as a target PHY chip.

Among them, the WCLK terminal is used to receive the external clock signal. Assuming that the external clock signal is the clock signal A, the input information (or level signal) of the S_MDC terminal and the S_MDI terminal is sampled according to the clock signal A received by the WCLK terminal. Parallel communication protocol information of the same frequency as the clock signal A.

The reset terminal is used to reset the first connector 310 .

The PHY ID terminal is used to receive the identification of the PHY chip or the physical layer protocol.

The S_MDC terminal is used to receive the clock signal of the management interface, and the clock signal is an aperiodic signal.

The S_MDI terminal is used to transmit the control information of the MAC layer and the status information of the physical layer. The status information is sampled by the MDIO protocol transmission. The information input by the S_MDI terminal is synchronized with the clock input by the S_MDC terminal. For example, when the rising edge of the clock arrives, the S_MDI start to enter information.

The S_OEN terminal is used to output the enable signal to control the input and output of the device or chip connected to the first connector. The low level is used to indicate the input data of the device or chip; the high level is used to indicate the device or chip. Chip output data.

The S_MDO end, similar to the S_MDI end, is used to receive the control information of the MAC layer and the state information of the physical layer. The state information is sampled by the MDIO protocol transmission, and the information output by the S_MDO end is synchronized with the clock input by the S_MDC end.

The Port terminal is connected to the Port terminal in the distributor 320 so as to transmit a selection command to the data selector connection, wherein the selection command is a selection command for selecting a target register from at least one register, so as to control the corresponding target device.

The Addr terminal is connected to the Addr terminal in the distributor 320, transmits the above-mentioned access address, and searches for the corresponding register in the distributor 320 according to the access address.

The OP end is connected to the OP end in the distributor 320, and transmits the above-mentioned read-write control command, which is used to control the read-write operation of the target device, wherein the read-write control command can be represented by binary, and the bit "10" represents For a read operation, bit "01" indicates a write operation.

The DATA_O end is connected to the Din end of the distributor 320, and is used for transmitting the above-mentioned data information, so that the data information is buffered in the corresponding register in the distributor 320, and then distributed to the corresponding second connector according to the clock control instruction 330.

The DATA_I terminal is connected to the Dout terminal of the distributor 320 , and is used for receiving the data information returned by the target device through the second connector 330 and the distributor 320 .

Therefore, the connector 310 composed of the above-mentioned structural parts realizes the parallel transmission of the communication protocol information in the conversion of the received MDIO protocol information, and then transmits the parallel communication protocol information to the distributor 320 through the corresponding port, so that Complete the next steps.

In conjunction with Fig. 6, the internal structure and function of the distributor are described. Fig. 6 is a schematic structural diagram of a distributor 320 provided by the implementation of the present invention, including: a WCLK end, a reset (Rst_n) end, at least one register 321, a Port end , address conversion (Addr) end, OP end, management data input (Din) end, management data output (Dout) end, data selector 322, and rate control (Pi_div) end, Pi_DEV end, address (Pi_Addr) end, management A data output (Pi_Dout) end, a read-write control (Pi_OP) end, a management data input (Pi_Din) end, and a status query (Pi_Status) end; wherein, the Pi_Dout end and the Pi_Din end form the management end described in the embodiment of the present invention, i is an integer greater than or equal to 0.

The WCLK terminal is used to receive an external clock signal. Assuming that the external clock signal is the clock signal B, the parallel communication protocol information is sampled according to the clock signal B received by the WCLK terminal, so as to obtain the parallel communication protocol information with the same frequency as the clock signal B. . It should be noted that the above-mentioned clock signal A and clock signal B may be clock signals generated from the same clock source.

The Rst_n terminal is used to reset the distributor 320.

At least one register 321 is used for buffer management of data information of the target device.

The Port terminal is connected to the Port terminal in the first connector 310, so as to transmit a selection instruction to the data selector 322 for connection, wherein the selection instruction is a selection instruction for selecting a target register from at least one register 321, so as to control the corresponding target device.

The data selector 322 is used to select a designated one from the Addr end, the OP end and the Din end according to the selection instruction transmitted by the Port end and send it to the output end, so as to transmit the corresponding data to the register 321 for corresponding operations.

The Addr terminal is connected to the Addr terminal in the first connector 310, transmits the above-mentioned access address, and searches for the corresponding register 321 in the distributor 320 according to the access address.

The OP terminal is connected to the OP terminal in the first connector 310, and transmits the above-mentioned read-write control command, which is used to control the read-write operation of the target device.

The Din terminal is connected to the DATA_O terminal of the first connector 310, and is used to transmit the above-mentioned data information, so that the data information is buffered in the corresponding register 321 in the distributor 320, and then distributed to the corresponding first according to the clock control instruction. Two connectors 330 .

The Dout terminal is connected to the DATA_I terminal of the first connector 310 , and is used to output the data information returned by the target device through the second connector 330 and the distributor 320 .

The Pi_div end is connected to the div end of the i-th second connector 330, and is used to transmit the working rate of the first connector 310, so that the i-th second connector 330 is connected to the i-th second connector 330 The working speed of the target device is consistent with the working speed of the first connector 310 .

The Pi_Addr end is connected to the Addr end of the i-th second connector 330, and is used to convert the address transmitted by the first connector 310 into the access address of the target device, and pass the converted access address through the i-th second connector. 330 transmits to the target device to gain access to the target device.

The Pi_Dout terminal is connected to the DATA_I terminal of the i-th second connector 330 , and is used to read the data in the register 321 for the target device, and transmit the read data to the second connector 330 .

The Pi_OP terminal is connected to the OP terminal of the i-th second connector 330, and is used to control the read and write operations of the target device.

The Pi_Din terminal is connected to the DATA_O terminal of the i-th second connector 330 for inputting the data information output by the second connector 330 .

The Pi_Status terminal is connected to the Status terminal of the i-th second connector 330 , and is used to query the working status of the first connector 310 .

Here, i represents the number of port groups connected to the second connector 330, and also represents the number of registers 321, Pi represents the i-th group of ports connected to the second connector in the distributor, and different Pis are connected to different The two connectors 330 are independent of each other, and the operating rates and operating frequencies are independent of each other. Therefore, the operating rates and operating frequencies of the target devices connected to the second connector 330 are independent of each other, avoiding the interface in the traditional method. The overall operating rate cannot be higher than the lowest rate among the connected devices, so that all target devices do not have to be completely limited to the lowest MDIO rate.

The distributor 320 constituted by the above structure realizes the distribution of the parallel communication protocol information sent by the first connector 310 to different second connectors 330 .

The internal structure and function of the second connector 330 will be described with reference to FIG. 7 . FIG. 7 is a schematic structural diagram of a second connector 330 provided by the implementation of the present invention, including: a WCLK terminal, a Reset terminal, a div terminal, and a DEV terminal. , Addr end, DATA_I end, OP end, Status end, DATA_O end, and metadata control (M_MDC) end, management data input (M_MDI) end, enable (M_OEN) end and management data output (M_MDO) end; here, The DATA_I terminal and the DATA_O terminal form the second data terminal, taking the i-th second connector 330 as an example, wherein,

The WCLK terminal is used to receive an external clock signal. Assuming that the external clock signal is a clock signal C, the parallel communication protocol information is sampled according to the clock signal C received by the WCLK terminal, and subjected to parallel/serial conversion to obtain the same clock signal C. MDIO protocol information of the same frequency. It should be noted that the above-mentioned clock signal A, clock signal B and clock signal C may be clock signals generated from the same clock source.

The reset terminal is used to reset the second connector 330 .

The div terminal is connected to the Pi_div terminal in the distributor 320, and is used to transmit the working rate of the first connector 310, so that the ith second connector 330 and the target device connected to the ith second connector 330 have The working rate is consistent with the working rate of the first connector 310 .

The Addr terminal is connected to the Pi_Addr terminal in the distributor 320, and is used for the distributor 320 to transmit the converted access address to the target device through the i-th second connector 330, so as to access the target device.

The DATA_I terminal is connected to the Pi_Dout terminal in the distributor 320, and is used for inputting the data read in the register 321 for the target device.

The OP terminal is connected to the Pi_OP terminal in the distributor 320, and is used to control the read and write operations of the target device.

The Status terminal is connected to the Pi_Status terminal in the distributor 320, and is used to query the working status of the port Pi.

It should be noted that the signals (or information) input or output from the above div end, DEV end, Addr end, DATA_I end, OP end, and Status end are parallel communication protocol signals (or information).

The DATA_O terminal is connected to the Pi_Din terminal in the distributor 320 , and is used for outputting the data information output by the second connector 330 .

The M_MDC terminal is used to output the clock signal of the management interface, and the clock signal is an aperiodic signal.

The M_MDI terminal is used to transmit the control information of the MAC layer and the status information of the physical layer. The status information is sampled by the MDIO protocol transmission. The information output by the M_MDI terminal is synchronized with the clock input by the M_MDC terminal. For example, when the rising edge of the clock arrives, the M_MDI start to enter information.

The M_OEN terminal is used to input the enable signal to control the input and output of the device or chip connected to the first connector 310 , the low level is used to instruct the device or chip to input data; the high level is used to instruct the device or chip output data.

The M_MDO end, similar to the M_MDI end, is used to receive the control information of the MAC layer and the state information of the physical layer. The state information is sampled by the MDIO protocol transmission, and the information output by the M_MDO end is synchronized with the clock input by the M_MDC end.

The second connector 330 constituted by the above structure converts the parallel communication protocol into the serial MDIO protocol.

Therefore, through the solution of the embodiment of the present invention, the input MDIO protocol information is converted into the MDIO protocol information of multiple branches through internal conversion, so as to realize the unified management of multiple target devices; in addition, the MDIO protocols of different branches are The information is independent of each other, so that the working rates, working states and working frequencies of different target devices are independent of each other and are not affected by each other.

In addition, through the solution of the embodiment of the present invention, since different second connectors are independent of each other, the second connectors can be grouped according to the working rate, the devices with similar rates are grouped into a group, and the target devices with large differences in rates, such as PHY The chips are divided into different groups; then, these groups are connected to different second connectors of the bridge device in a conventional manner, so that unified management of PHY chips of different rates can be realized.

An embodiment of the present invention further provides a management system, as shown in FIG. 8 , which is a schematic structural diagram of a management system provided by the implementation of the present invention, including: a bridge device 300, a management device 400, and at least one target device 500; in,

a management device 400, connected to the bridge device 300, for generating and outputting management data input and output protocol information, so as to manage the at least one target device 500 according to the output information;

Here, the management apparatus 400 may be a MAC device.

The bridging device 300 is connected to at least one target device 500, and is used for receiving management data input and output protocol information, converting the received information into parallel communication protocol information; multiplexing the communication protocol information, and converting the distributed information Input and output protocol information for multiple management data;

At least one target device 500 is configured to receive the management data input and output protocol information transmitted by the bridge device 500, and perform corresponding management operations according to the received information.

In an optional embodiment, the target device is a physical layer chip or a next-level bridge device.

For the internal function and structure of the bridge device 300, reference may be made to FIG. 3 to FIG. 7, and details are not repeated here.

In the management system system, the bridging device 300 converts the access of the management device 400 to this interface, and expands it to access to multiple target devices 500; the conversion relationship is as shown in Table 1. It should be noted that the register addresses mentioned later are only for illustration. For convenience, it does not stipulate that the address must be used or the registers are divided in this way; it can be divided flexibly on the premise of ensuring the necessary information required by this conversion relationship.

Table 1 Conversion relationship

For the standard MDIO protocol (register address bit width is 5 bits), the bridge structure can support up to 3 second connectors; for the address register bit width supported by the extended protocol is 16 bits, it can support up to 6,000 second connectors.

Through this bridge device, the access to the connected MDIO device becomes as follows, assuming that the PHY of the device to be accessed is hung on port 1 of the bridge, the ID of the PHY is PHY_ID, and the address of the accessed register is Addr: (MIIWrite is MDIO The write operation of the interface, MIIRead is the read operation of the MDIO interface).

A) Read access:

MIIWrite: {2'h1,3'h2}, PHY_ID; //write port 1's PHY/DEV register to PHY_ID;

MIIWrite: {2'h1,3'h0}, Addr; //The Addr register of write port 1 is Addr;

MIIWrite: {2'h1,3'h5}, 16'h1; //write the OP register of port 1 to 1; trigger the read operation of port 1MDIO;

MIIREAD: {2'h1,3'h4}, DATA; //Read the Status register of port 1, the DATA return value is 1 to indicate that the read operation is being performed; zero indicates that the read operation is completed;

MIIREAD: {2'h1,3'h1}, DATA; //Read the DATA register of port 1, when the read operation is completed, return the read data;

B) Write access:

MIIWrite: {2'h1,3'h2}, PHY_ID; //write port 1's PHY/DEV register to PHY_ID;

MIIWrite: {2'h1,3'h0}, Addr; //The Addr register of write port 1 is Addr;

MIIWrite: {2'h1,3'h1}, DATA; //Write the DATA register of port 1 to trigger the write operation to port 1MDIO;

MIIREAD: {2'h1,3'h1}, DATA; //Read the Status register of port 1, the DATA return value is 1 to indicate that the operation is being performed; zero indicates that the operation is completed.

When accessing the same PHY chip or device of a second connector continuously, the address of the register in the chip or device does not need to be updated every time; Updates are required to improve access efficiency. In the Status of the address {2'h3,3'h0}, Status[1:0] indicates the status of port P0, Status[3:2] indicates the status of P1, and Status[5:4] indicates the status of P2; Querying this state first and accessing idle devices can make each port parallel and further improve the access efficiency.

Through the scheme of the embodiment of the present invention, the following beneficial effects can be obtained:

1) The working rates of the second connectors in the bridge device are independent of each other. Therefore, PHY chips with large differences in speed can be operated on different second connectors. Compared with the traditional method, the target device is prevented from being completely Limited by the lowest MDIO rate, thus improving the work rate of unified management.

2) Each second connector in the bridging device can be directly connected to multiple target chips or devices, or can be cascaded with the next-level bridging device, which greatly increases the number of managed PHY chips or devices.

The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements and improvements made within the spirit and scope of the present invention are included in the protection scope of the present invention.

Claims (12)

1. A bridging apparatus for managing a data input output protocol, comprising: a first connector, a dispenser and at least one second connector; wherein,

the first connector is connected with the distributor and used for receiving management data input and output protocol information and converting the received information into parallel transmission communication protocol information;

the distributor is connected with the at least one second connector and used for distributing the communication protocol information to the at least one second connector;

the at least one second connector is configured to convert the distributed communication protocol information into the management data input/output protocol information and output the management data input/output protocol information, and manage a target device connected to the at least one second connector according to the output information.

2. The apparatus of claim 1, wherein the dispatcher includes at least one register for caching data information that manages the target apparatus.

3. The apparatus of claim 2, wherein the communication protocol information comprises the data information and an access address;

the first connector comprises a first data end and an address end; wherein,

the address end is used for accessing the corresponding register according to the access address;

and the data end is used for transmitting the data information to the register cache.

4. The apparatus of claim 2, wherein the second connector comprises a second data terminal for obtaining data information buffered in the register.

5. The apparatus of claim 1, wherein the at least one second connector each comprises a management end; wherein,

the management terminal is connected with the target device and used for transmitting the management data input and output protocol information to the target device and managing the target device according to the output information.

6. The apparatus of claim 3, wherein the distributor comprises an address translation end and a read-write end; wherein,

the address conversion end is used for converting the address transmitted by the first connector into an access address of the target device;

and the read-write end is used for reading the data in the register aiming at the target device and transmitting the data to the second connector.

7. The apparatus of claim 3, wherein the dispatcher includes a data selector configured to select a destination register from the at least one register according to a received selection instruction.

8. The apparatus of claim 1, wherein the first connector, the distributor, and the at least one second connector each comprise a clock control terminal and a reset terminal; wherein,

the clock control end is used for receiving clock control information, and the clock control information is used for controlling the working state;

the reset end is used for receiving reset information, and the reset information is used for controlling reset.

9. The apparatus of claim 1, wherein the distributor comprises a rate control end and a status query end; wherein,

the rate control end is used for controlling the working rate of a target device connected with the at least one second connector;

the state inquiry terminal is used for inquiring the state information of the target device connected with the at least one second connector.

10. The apparatus of claim 1, wherein the first connector and the at least one second connector comprise: and the enabling end is used for transmitting an enabling signal and controlling the input and the output of information according to the enabling signal.

11. A management system, comprising: a bridge device, a management device and at least one target device; wherein,

the management device is connected with the bridging device and used for generating and outputting management data input and output protocol information;

the bridge device is connected with the at least one target device and used for receiving the management data input and output protocol information and converting the received information into parallel communication protocol information; carrying out multi-path distribution on the communication protocol information, and converting the distributed information into multi-path management data input and output protocol information;

the at least one target device is used for receiving the management data input and output protocol information transmitted by the bridging device and carrying out corresponding management operation according to the received information.

12. The system of claim 11, wherein the target device is a physical layer chip or the bridge device at a next level.