CN109379243B - Method for establishing topology display model of silicon cube high-performance computer - Google Patents

Abstract

The invention provides a method for establishing a topology display model of a silicon cube high-performance computer. The silicon cube high-performance computer is composed of a plurality of silicon elements connected according to the topology of 3D Torus, and each of the silicon elements is composed of 12 silicon elements. The switching chips are connected in a 3D Torus topology, and each of the switching chips is connected to a plurality of computing nodes. The method includes: establishing a silicon cube topology page based on WebGL, where the silicon cube topology page is used to display the silicon cube Topological relationship between the silicon elements of the high-performance computer; in each silicon element, the internal topology page of the silicon element is established based on WebGL, and the internal topology page of the silicon element is used to display the topology between the switching chips inside the silicon element relation. The present invention can establish a 6D topology display model to meet the display requirements.

Description

A Method for Establishing Topological Display Model of Silicon Cube High Performance Computer

technical field

The invention relates to the technical field of servers, in particular to a method for establishing a topology display model of a silicon cube high-performance computer.

Background technique

As the network scale of various data centers in the high-performance field continues to expand, it is expected that there will be hundreds of millions of computing needs, and the corresponding network topology will become more complex. In order to cope with the complex network topology in billion-scale computing, a new high-dimensional network topology, 6D Torus, and a silicon cube high-performance computer using 6D Torus topology have emerged. In order to monitor the silicon cube high-performance computer using the 6D Torus topology, it is necessary to implement corresponding pages to display and monitor the topological structure of the silicon cube in multiple levels and dimensions.

The existing WebGL technology can display three-dimensional structures, and can also observe three-dimensional structures from multiple perspectives by rotating or dragging. However, since the silicon cube high-performance computer needs to display six dimensions, it is obvious that the existing WebGL technology cannot meet the requirements of silicon cubes. cubic display needs.

SUMMARY OF THE INVENTION

In order to solve the above problems, the present invention provides a method for establishing a topology display model of a silicon cube high-performance computer, which can establish a 6D topology display model to meet the display requirements.

The invention provides a method for establishing a topology display model of a silicon cube high-performance computer. The silicon cube high-performance computer is composed of a plurality of silicon elements connected according to the topology of 3D Torus, and each of the silicon elements is composed of 12 silicon elements. The switching chips are connected according to the topology of 3D Torus, and each of the switching chips is connected to a plurality of computing nodes. The method includes:

Create a silicon cube topology page based on WebGL, the silicon cube topology page is used to display the topological relationship between the silicon elements of the silicon cube high-performance computer;

In each silicon element, an internal topology page of the silicon element is established based on WebGL, and the internal topology page of the silicon element is used to display the topology relationship between each switching chip inside the silicon element.

Optionally, the topological relationship between the silicon elements of the silicon cube high-performance computer includes: the connection mode between the silicon elements, the information of each silicon element itself, and the information of each edge between the silicon elements, wherein , the connection between the silicon elements is the standard cube-shaped 3D Torus connection.

Optionally, the information of each silicon element of the silicon cube high-performance computer includes: the serial number and coordinates of each silicon element and the current working state of each silicon element.

Optionally, the mapping rule for the serial number and coordinates of each silicon element is: on the silicon cube topology page, set the x direction to be from left to right, the y direction to be from front to back, and the z direction to be from bottom to top, then The serial number 0 corresponds to the coordinate (0, 0, 0), and the coordinates corresponding to the other serial numbers are incremented according to the priority of x, y, and z.

Optionally, the information of each edge between the silicon elements of the silicon cube high-performance computer includes: the serial numbers of the silicon elements at both ends of each edge, the number of links on each edge, and the port information of each link. .

Optionally, the topological relationship between the switching chips inside the silicon element includes: the connection mode between the switching chips, the information of the switching chips themselves, and the information of each connection between the switching chips, wherein, The connection between the switching chips inside the silicon element is as follows: 12 switching chips are divided into upper, middle and lower layers, and each vertex of the middle layer forms a loop with a vertex of the upper layer and a vertex of the lower layer. connected.

Optionally, the information of each switch chip inside the silicon element includes: the serial number and coordinates of each switch chip and the current working state of each switch chip.

Optionally, the mapping rule of the serial number and coordinates of each switch chip is: on the internal topology page of the silicon element, set the a direction to be from left to right, the b direction to be from front to back, and the c direction to be from bottom to top, Then the serial number 0 corresponds to the coordinate (0, 0, 0), and the coordinates corresponding to the other serial numbers are incremented according to the priority of a, b, and c.

Optionally, the information of each connection between the switching chips inside the silicon element includes: link information of the link corresponding to each connection.

The method for establishing a topology display model of a silicon cube high-performance computer provided by the present invention can establish a 6D topology display model, which is mainly divided into two pages - a silicon cube topology page and a silicon element internal topology page, which can not only display the silicon cube Its own topology can also select a silicon element from the silicon cube topology page to further display the internal topology of the silicon element, as well as the basic information and alarm status of nodes on the topology, fully meeting the display needs.

Description of drawings

1 is a schematic flowchart of an embodiment of a method for establishing a topology display model of a silicon cube high-performance computer according to the present invention;

2 is a schematic diagram of a 4X4X4 silicon cube topology page established in an embodiment of the present invention;

FIG. 3 is a schematic diagram of an internal topology page of a silicon element established in an embodiment of the present invention.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments It is only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

The embodiment of the present invention provides a method for establishing a topology display model of a silicon cube high-performance computer. A silicon cube high-performance computer is composed of a plurality of silicon elements connected according to the topology of 3D Torus, and each silicon element is composed of 12 switches. The chips are connected according to the topology of 3D Torus, and each switching chip is connected to multiple computing nodes, as shown in Figure 1, the method includes:

S11. Build a silicon cube topology page based on WebGL, and the silicon cube topology page is used to display the topological relationship between the silicon elements of the silicon cube high-performance computer;

S12. In each silicon element, an internal topology page of the silicon element is established based on WebGL, and the internal topology page of the silicon element is used to display the topology relationship between each switching chip inside the silicon element.

Optionally, the topological relationship between the silicon elements of the silicon cube high-performance computer includes: the connection mode between the silicon elements, the information of each silicon element itself, and the information of each edge between the silicon elements; The topology relationship between the switching chips includes: the connection mode between the switching chips, the information of the switching chips themselves, and the information of each connection between the switching chips.

Specifically, the silicon cube topology page mainly displays the topological relationship between the silicon elements, and can display the connection mode between the silicon elements, the information of each silicon element itself, and the information of each edge between the silicon elements. Among them, the topology between each silicon element adopts a standard cube-shaped 3DTorus structure. As shown in Figure 2, it is a standard 4X4X4 silicon cube 3DTorus structure. For clarity, the coordinate reference direction and the coordinate origin are shown. It should be noted that the silicon cube can be expanded infinitely. The information of each silicon element includes the serial number, coordinates of each silicon element and the current working state of each silicon element. The current working status indicates whether the silicon element is abnormal. If there is an abnormality, an alarm message will be displayed.

On the Silicon Cube topology page, set x as the width, and the direction is from left to right; y is the depth, and the direction is from front to back; z is the height, and the direction is from bottom to top. Taking a vertex of the cube as the origin, its (x, y, z) coordinates are (0, 0, 0), so that the coordinate position of each silicon element in the silicon cube is determined.

The mapping rule between silicon element serial numbers and coordinates: serial number 0 corresponds to the coordinate origin (0, 0, 0), and then increments according to the priority of x, y, and z until all serial numbers correspond to the upper coordinates. Taking a 2x2x3 cube as an example, the mapping relationship between the silicon element number and the silicon element coordinates is shown in Table 1 below:

Table 1

The information of each edge between the silicon elements includes: ① the serial numbers of the silicon elements at both ends of the edge; ② there are several links on this edge, and each link is connected to which switch chip from which port of which switch chip which port (obtained by physical connection).

The internal topology page of the silicon element mainly displays the topology relationship between the switching chips inside the silicon element, which can display the connection method between the switching chips, the information of each switching chip itself, and the information of each connection between the switching chips. Among them, the topology between each switching chip adopts a 3D Torus structure with a special shape. As shown in Figure 3, it is a 3DTorus structure of silicon element. For clarity, the coordinate reference direction and the coordinate origin are shown. The 12 switching chips of the silicon element are divided into upper, middle and lower layers, and each vertex of the middle layer is required to be connected with a vertex of the upper layer and a vertex of the lower layer in a loop. The information of each switching chip itself includes: the serial number and coordinates of each switching chip, and the current working state of each switching chip. The current working status indicates whether the switch chip is abnormal. If there is an abnormality, an alarm message is displayed.

On the internal topology page of the silicon element, set a as the width, and the direction is from left to right; b is the depth, and the direction is from front to back; c is the height, and the direction is from bottom to top. A certain vertex of the lower layer is used as the origin, and its (a, b, c) coordinates are (0, 0, 0), so that the coordinate position of each exchange chip in the silicon element is determined.

Exchange the mapping rules of chip serial numbers and coordinates: serial number 0 corresponds to the coordinate origin (0,0,0), and then increments according to the priorities of a, b, and c until all serial numbers correspond to the upper coordinates. The mapping relationship between the serial number of each switch chip inside a silicon element and the coordinates of the switch chip is shown in Table 2 below:

Table 2

Switch chip serial number Swap chip coordinates (c,b,a) 0 0,0,0 1 0,0,1 2 0,1,0 3 0,1,1 4 1,0,0 5 1,0,1 6 1,1,0 7 1,1,1 8 2,0,0 9 2,0,1 10 2,1,0 11 2,1,1

The information of each connection between the switching chips inside the silicon element includes: the link information of the link corresponding to each connection, that is, the link is connected from which port of which switching chip to which port of which switching chip. Port (obtained by physical connection).

Place the switch chip on the corresponding coordinates of the 3D topology of a silicon element according to the serial number of the switch chip, and then add a connection between the corresponding two switch chips according to the link information between the switch chip and the switch chip. The topological relationship between the switching chips inside the silicon element is displayed.

The method for establishing a topology display model of a silicon cube high-performance computer provided by the embodiment of the present invention can establish a 6D topology display model, which is mainly divided into two pages - a silicon cube topology page and a silicon element internal topology page, which can display both The topology of the silicon cube itself can also be selected from the silicon cube topology page to further display the internal topology of the silicon element, as well as the basic information and alarm status of nodes on the topology, fully meeting the display requirements.

Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be implemented by instructing relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. During execution, the processes of the embodiments of the above-mentioned methods may be included. The storage medium may be a magnetic disk, an optical disk, a read-only memory (Read-Only Memory, ROM), or a random access memory (Random Access Memory, RAM) or the like.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical scope disclosed by the present invention can easily think of changes or substitutions. All should be included within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims (5)

1. A method for establishing a topology display model of a silicon cube high-performance computer, the silicon cube high-performance computer is composed of a plurality of silicon elements connected according to the topology of 3D Torus, and each of the silicon elements is composed of 12 switches. The chips are connected according to the topology of 3DTorus, and each of the switching chips is connected to a plurality of computing nodes. It is characterized in that, the method includes: A silicon cube topology page is established based on WebGL. The silicon cube topology page is used to display the serial number of each silicon element of the silicon cube high-performance computer, the coordinates of each silicon element, the current working state of each silicon element, and the relationship between each silicon element. Information of each edge, in which the current working state of each silicon element indicates whether the silicon element is abnormal. If an abnormality occurs, an alarm message will be displayed. The information of each edge between each silicon element includes: the silicon element serial number at both ends of each edge, The number of links on each edge and the port information of each link; In each silicon element, an internal topology page of the silicon element is established based on WebGL. The internal topology page of the silicon element is used to display the serial number of each switching chip inside the silicon element, the coordinates of each switching chip, the current working status of each switching chip and The information of each connection between the switching chips. The current working status of each switching chip indicates whether the switching chip is abnormal. If there is an abnormality, an alarm message will be displayed. The information of each connection between the switching chips includes: each Link information of the link corresponding to the connection. 2 . The method according to claim 1 , wherein the silicon cube topology page is further used to display the connection mode between the silicon elements, wherein the connection mode between the silicon elements is a standard cubic shape. 3 . 3D Torus connection method. 3. The method according to claim 1, wherein the mapping rule of the serial numbers and coordinates of each silicon element is: on the silicon cube topology page, set the x direction to be from left to right, and the y direction to be from front to right Then, the z direction is from bottom to top, the sequence number 0 corresponds to the coordinate (0, 0, 0), and the coordinates corresponding to the other sequence numbers are incremented according to the priority of x, y, and z. 4 . The method according to claim 1 , wherein the internal topology page of the silicon element is further used to display the connection mode between each switching chip inside the silicon element, wherein each switching chip inside the silicon element The connection mode is as follows: 12 switching chips are divided into upper, middle and lower layers, and each vertex of the middle layer is connected to a vertex of the upper layer and a vertex of the lower layer in a loop. 5 . The method according to claim 1 , wherein the mapping rule of the serial numbers and coordinates of each switching chip is: in the internal topology page of the silicon element, set the a direction as from left to right, and the b direction as the former Finally, the c direction is from bottom to top, then the sequence number 0 corresponds to the coordinate (0, 0, 0), and the other sequence numbers correspond to the coordinates according to the priority of a, b, and c.

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