CN109360854A - A power device terminal structure and its manufacturing method - Google Patents
A power device terminal structure and its manufacturing method Download PDFInfo
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- CN109360854A CN109360854A CN201811266036.9A CN201811266036A CN109360854A CN 109360854 A CN109360854 A CN 109360854A CN 201811266036 A CN201811266036 A CN 201811266036A CN 109360854 A CN109360854 A CN 109360854A
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- 238000004519 manufacturing process Methods 0.000 title claims description 20
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 229920005591 polysilicon Polymers 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims description 47
- 238000005530 etching Methods 0.000 claims description 17
- 238000002513 implantation Methods 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 claims 1
- 238000002347 injection Methods 0.000 abstract description 20
- 239000007924 injection Substances 0.000 abstract description 20
- 230000003071 parasitic effect Effects 0.000 abstract description 9
- 238000002360 preparation method Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 318
- 239000004065 semiconductor Substances 0.000 description 30
- 150000002500 ions Chemical class 0.000 description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 21
- 238000009792 diffusion process Methods 0.000 description 21
- 229910052710 silicon Inorganic materials 0.000 description 21
- 239000000463 material Substances 0.000 description 17
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- 230000008569 process Effects 0.000 description 11
- 238000000151 deposition Methods 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 8
- 229910052796 boron Inorganic materials 0.000 description 8
- 229910052785 arsenic Inorganic materials 0.000 description 7
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 239000004411 aluminium Substances 0.000 description 6
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
- H10D62/125—Shapes of junctions between the regions
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
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- Electrodes Of Semiconductors (AREA)
Abstract
The present invention provides a kind of power device terminal structure and preparation method thereof, it include: the substrate of the first conduction type, first epitaxial layer of the first conduction type, it is sequentially formed in the first groove of first epitaxial layer upper surface, second groove and third groove, second epitaxial layer of the second conduction type, the injection region of second conduction type, third epitaxial layer, the fourth epitaxial layer of first conduction type, 5th epitaxial layer of the second conduction type, dielectric layer, first contact hole, second contact hole, high resistance polysilicon layer, the terminal structure is in the case where minimizing terminal structure length, increase device depletion region area, and it not will increase the parasitic capacitance of device, improve the Performance And Reliability of power device terminal structure.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of power device terminal structure and preparation method thereof.
Background technique
One of most important performance of power device is exactly anti-high pressure ability, and device can exhausting with device interfaces by design
High pressure is born in area, with the increase of applied voltage, depletion region electric field strength also be will increase, and is eventually exceeded material limits and is avenged
Collapse breakdown.When device edge depletion region electric field curvature increases, it is big to will lead to electric field ratio die internal, in the raised mistake of voltage
Die edge avalanche breakdown can occur earlier than die internal in journey, in order to improve the performance of device, need to design in device edge
Partial-pressure structure reduces depletion region curvature, is laterally extended depletion region, enhances the voltage endurance capability of horizontal direction.
Termination extension technology is one of the partial-pressure structure generallyd use in current power device.Its simple process, can be with
It is diffuseed to form together with active area.Termination extension technology is the p type island region domain that one circle of production is lightly doped around main knot.When main knot
When reverse-biased, knot terminal extended area can be depleted simultaneously.It is equivalent to introduce negative electricity inside the depletion region of drift region at this time
Lotus, these negative electrical charges extend depletion region, and itself can also absorb a part of electric field, to reduce the electric field of main knot edge
Spike.And then improve the breakdown characteristics of device.But the shortcomings that this structure is that the interface charge of surface oxide layer can be to device
Surface potential produces a very large impact, and influences to divide effect, reduces anti-breakdown voltage capabilities.PN junction is reverse-biased when device reverse operation
Formation depletion region area is larger, and following parasitic capacitance will increase the switching loss of device, while this structure will increase device
The area of part, to increase the cost of manufacture of power device.
Summary of the invention
The present invention is based on the above problem, a kind of power device terminal structure and preparation method thereof is proposed, is being minimized eventually
In the case where end structure length, device depletion region area is increased, and not will increase the parasitic capacitance of device, improve power device
The Performance And Reliability of part terminal structure.
On the one hand, the present invention provides a kind of production methods of power device terminal structure, this method comprises:
The substrate of first conduction type is provided；
Surface forms the first epitaxial layer of the first conduction type over the substrate；
First groove, second groove and third groove are sequentially formed in first epitaxial layer upper surface；
On the first groove side wall, the second groove side wall, the third groove and first epitaxial layer
Surface forms the second epitaxial layer of the second conduction type；
The second conduction type is formed in the first groove bottom surface and the second groove underrun ion implanting mode
Injection region；
The side wall of second epitaxial layer in the first groove forms the third epitaxial layer of the first conduction type；
The fourth epitaxial layer of the first conduction type is filled in the remainder of the second groove；
The 5th of the second conduction type the is formed in the remainder of first epitaxial layer upper surface and the first groove
Epitaxial layer；
Dielectric layer is formed in the 5th epitaxial layer upper surface；
Etch the dielectric layer, the 5th epitaxial layer forms the first contact hole, first contact hole and the third
Epitaxial layer is connected with the 5th epitaxial layer in the first groove；
Etch the dielectric layer, the 5th epitaxial layer and the second epitaxial layer shape of first epitaxial layer upper surface
At the second contact hole, second contact hole lower surface is connect with first epitaxial layer upper surface；
High resistance polysilicon layer is formed in the dielectric layer upper surface, first contact hole and second contact hole.
Further, the depth of the first groove, the second groove and the third groove is roughly equal.
Further, the width of the first groove is greater than the width of the second groove, the width of the second groove
Greater than the width of the third groove.
Further, in the first groove side wall, the second groove side wall, the third groove and described first
Epitaxial layer upper surface forms the second epitaxial layer of the second conduction type, specifically includes:
In the side wall and bottom surface, the third groove, first extension of the first groove and the second groove
Layer upper surface forms the 6th epitaxial layer of the second conduction type；
The 6th epitaxial layer for etching away the first groove and the second groove bottom surface forms second extension
Layer.
Further, the side wall of second epitaxial layer in the first groove forms the third of the first conduction type
Epitaxial layer is filled the fourth epitaxial layer of the first conduction type in the remainder of the second groove, is specifically included:
Second extension in second epitaxial layer upper surface, the first groove bottom surface, the first groove
Layer side wall, the second groove form the 7th epitaxial layer；
The 7th epitaxial layer of second epitaxial layer upper surface, the first groove bottom surface is etched away to described
The side wall of second epitaxial layer in first groove forms the third epitaxial layer of the first conduction type, in the second groove
Remainder fills the fourth epitaxial layer of the first conduction type.
Further, the ion concentration of the 5th epitaxial layer is higher than the ion concentration of second epitaxial layer.
On the other hand, the present invention provides a kind of power device terminal structure, which includes:
The substrate of first conduction type；
It is formed in the first epitaxial layer of the first conduction type of the upper surface of substrate；
It is sequentially formed in the first groove, second groove and third groove of first epitaxial layer upper surface；
It is formed in the first groove side wall, the second groove side wall, the third groove and first extension
Second epitaxial layer of the second conduction type of layer upper surface；
It is formed in the injection region of the second conduction type of the first groove bottom surface and the second groove bottom surface；
It is formed in the third epitaxial layer of the first conduction type of the second epitaxial layer side wall in the first groove；
It is filled in the fourth epitaxial layer of the first conduction type of the second groove remainder；
It is formed in the 5th of the second conduction type of first epitaxial layer upper surface and the first groove remainder the
Epitaxial layer；
It is formed in the dielectric layer of the 5th epitaxial layer upper surface；
Etch the dielectric layer, the first contact hole that the 5th epitaxial layer is formed, first contact hole and described the
Three epitaxial layers are connected with the 5th epitaxial layer in the first groove；
Etch the dielectric layer, the 5th epitaxial layer and the second epitaxial layer shape of first epitaxial layer upper surface
At the second contact hole, second contact hole lower surface is connect with first epitaxial layer upper surface；
The high resistance polysilicon being formed in the dielectric layer upper surface, first contact hole and second contact hole
Layer.
Further, the width of the first groove is greater than the width of the second groove, the width of the second groove
Greater than the width of the third groove.
Further, the ion concentration of the 5th epitaxial layer is higher than the ion concentration of second epitaxial layer.
Further, the ion concentration of the third epitaxial layer and the fourth epitaxial layer is higher than first epitaxial layer
Ion concentration.
The present invention is through the above technical solutions, propose a kind of power device terminal structure, by etching groove, repeatedly outside
Prolong, can make to divide the termination extension structure that region forms junction depth and concentration gradient under the premise of the process compatible with device.
It is compared with traditional structure, simple process, junction depth and concentration can be controlled by extension width and concentration, and production cost is low.Junction depth
Raising voltage dividing ability can be maximized with concentration gradient, device area is reduced, reduces the cost of manufacture of device, promote the property of device
Energy.Epitaxial layer is connect with the terminal of device outermost end by high resistance polysilicon layer, advantageously reduces the parasitic capacitance of device.It should
Terminal structure increases device depletion region area, and not will increase posting for device in the case where minimizing terminal structure length
Raw capacitor, improves the Performance And Reliability of power device terminal structure.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below to needed in embodiment description
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, general for this field
For logical technical staff, without creative efforts, it is also possible to obtain other drawings based on these drawings.?
In attached drawing:
Fig. 1 is the flow diagram of the production method for the power device terminal structure that one embodiment of the present of invention provides；
Fig. 2 to Fig. 8 is the structure of the making step for the function power device terminal structure that one embodiment of the present of invention provides
Schematic diagram；
Description of symbols:
1- substrate；The first epitaxial layer of 2-；The second epitaxial layer of 3-；4- third epitaxial layer；5- fourth epitaxial layer；The 5th extension of 6-
Layer；The 6th epitaxial layer of 7-；The 7th epitaxial layer of 8-；9- first groove；10- second groove；11- third groove；The injection region 12-；13-
Dielectric layer；The first contact hole of 14-；The second contact hole of 15-；16- high resistance polysilicon layer.
Specific embodiment
It below will the present invention will be described in more detail refering to attached drawing.In various figures, identical element uses similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use that " A is directly on B herein to describe located immediately at another layer, another region above scenario
The expression method of face " or " A on B and therewith abut ".In this application, " A is in B " indicates that A is located in B, and
And A and B is abutted directly against, rather than A is located in the doped region formed in B.
In this application, term " semiconductor structure " refers to entire half formed in each step of manufacturing semiconductor devices
The general designation of conductor structure, including all layers formed or region.
Many specific details of the invention, such as structure, material, the size, processing side of device are described hereinafter
Method and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
Below in conjunction with Fig. 1 to Fig. 8 to a kind of power device terminal structure provided in an embodiment of the present invention and preparation method thereof
It is described in detail.
The embodiment of the present invention provides a kind of production method of power device terminal structure, one embodiment as shown in Figure 1
The flow diagram of the production method of the power device terminal structure of offer, the production method of the terminal structure include:
Step S1: the substrate 1 of the first conduction type is provided；
Step S2: the first epitaxial layer 2 of the first conduction type is formed in 1 upper surface of substrate；
Step S3: first groove 9, second groove 10 and third groove are sequentially formed in 2 upper surface of the first epitaxial layer
11；
Step S4: in 9 side wall of first groove, 10 side wall of the second groove, the third groove 11 and described
First epitaxial layer, 2 upper surface forms the second epitaxial layer 3 of the second conduction type；
Step S5: is formed in 9 bottom surface of first groove and 10 underrun ion implanting mode of the second groove
The injection region 12 of two conduction types；
Step S6: the side wall of second epitaxial layer 3 in the first groove 9 forms the third of the first conduction type
Epitaxial layer 4；
Step S7: the fourth epitaxial layer 5 of the first conduction type is filled in the remainder of the second groove 10；
Step S8: the second conductive-type is formed in the remainder of 2 upper surface of the first epitaxial layer and the first groove 9
5th epitaxial layer 6 of type；
Step S9: dielectric layer 13 is formed in 6 upper surface of the 5th epitaxial layer；
Step S10: the dielectric layer 13 is etched, the 5th epitaxial layer 6 forms the first contact hole 14, first contact
Hole 14 is connect with the 5th epitaxial layer 6 in the third epitaxial layer 4 and the first groove 9；
Step S11: the described of the dielectric layer 13, the 5th epitaxial layer 6 and 2 upper surface of the first epitaxial layer is etched
Second epitaxial layer 3 forms the second contact hole 15, and 15 lower surface of the second contact hole and 2 upper surface of the first epitaxial layer connect
It connects；
Step S12: it is formed in 13 upper surface of dielectric layer, first contact hole 14 and second contact hole 15
High resistance polysilicon layer 16.
Technical solution of the present invention is related to designing and manufacturing for semiconductor devices, and semiconductor refers to that a kind of electric conductivity can be controlled
System, conductive extensions can be from insulator to the material changed between conductor, and common semiconductor material has silicon, germanium, GaAs etc., and
Silicon is most powerful, one kind for being most widely used in various semiconductor materials.Semiconductor is divided into intrinsic semiconductor, p-type
Semiconductor and N-type semiconductor, free from foreign meter and without lattice defect semiconductor is known as intrinsic semiconductor, in pure silicon crystal
It mixes triad (such as boron, indium, gallium), is allowed to replace the seat of silicon atom in lattice, P-type semiconductor is just formed, pure
Silicon crystal in mix pentad (such as phosphorus, arsenic), be allowed to replace the position of silicon atom in lattice, be formed N-type and partly lead
The conduction type of body, P-type semiconductor and N-type semiconductor is different, and in an embodiment of the present invention, the first conduction type is N-type, the
Two conduction types are p-type, in an embodiment of the present invention, if not otherwise specified, the preferred doping of every kind of conduction type from
Son is all that can be changed to the ion with same conductivity type, is just repeated no more below.
Specifically, the substrate 1 is the carrier in integrated circuit, and the substrate 1 plays the role of support, the substrate 1
Also assist in the work of the integrated circuit.The substrate 1 can be silicon substrate 1, or Sapphire Substrate 1 can also be
Silicon carbide substrates 1, it might even be possible to be silicon Chu substrate 1, it is preferred that the substrate 1 is silicon substrate 1, this is because 1 material of silicon substrate
Have the characteristics that low cost, large scale, conductive, avoids edge effect, yield can be increased substantially.In reality of the invention
Apply in example, the substrate 1 is the substrate 1 of the first conduction type, and first conduction type is N-type, the doping of the substrate 1 from
Son is phosphorus or arsenic etc., and 1 doping concentration of substrate is highly doped.
Referring next to attached drawing, the production method of power device terminal structure described above is elaborated.
Attached drawing 2 is please referred to, step S1, S2 is executed, specifically: the substrate 1 of the first conduction type is provided；In the substrate 1
Upper surface forms the first epitaxial layer 2 of the first conduction type.Wherein epitaxial growth shape can be used in 1 upper surface of substrate
At first epitaxial layer 2 can also be formed in 1 upper surface of substrate by ion implanting and/or the method for diffusion.Into one
Step ground, can be epitaxially-formed in the 1 upper surface use of substrate, can also pass through ion implanting and/or diffusion P elements
Or the method for any combination of arsenic element or both forms first epitaxial layer 2 in 1 upper surface of substrate.Specifically, institute
The method for stating epitaxial growth or diffusion includes depositing operation.In some embodiments of the invention, depositing operation can be used to exist
1 upper surface of substrate forms first epitaxial layer 2, for example, depositing operation can be selected from electron beam evaporation, chemical gaseous phase
One of deposition, atomic layer deposition, sputtering.Preferably, described first is formed using chemical vapor deposition on the substrate 1
Epitaxial layer 2, chemical vapor deposition include process for vapor phase epitaxy.In production, chemical vapor deposition uses vapour phase epitaxy work mostly
Skill forms the first epitaxial layer 2 using process for vapor phase epitaxy in 1 upper surface of substrate, and silicon material can be improved in process for vapor phase epitaxy
The perfection of material improves the integrated level of device, reaches raising minority carrier life time, reduces the leakage current of storage element.The substrate 1
Doping concentration is different from the doping concentration of first epitaxial layer 2.Preferably, the doping concentration of the substrate 1 is higher than described the
The doping concentration of one epitaxial layer 2, the resistivity of substrate 1 described in the resistivity ratio of first epitaxial layer 2 is high at this time, reduces parasitic
Resistance, to improve the breakdown reverse voltage of device.
Please refer to attached drawing 2, execute step S3, specifically: first epitaxial layer upper surface sequentially form first groove,
Second groove and third groove.Further, the depth of the first groove, the second groove and the third groove is substantially
It is equal；The width of the first groove is greater than the width of the second groove, and the width of the second groove is greater than the third
The width of groove.In some embodiments of the invention, mask material is prepared in the upper surface of first epitaxial layer 2, it is described
Mask material is specially the first photoresist, is formed on first photoresist layer by etching and runs through first epitaxial layer 2
The first groove 9, the second groove 10 and the third groove 11, then remove first photoresist.Wherein, it etches
Method include dry etching and wet etching, it is preferred that the method for the etching used be dry etching, dry etching includes light
Volatilization, gaseous corrosion, plasma etching etc., and dry etching easily realizes that automation, treatment process are not introduced into pollution, cleannes
It is high.In some embodiments of the invention, the bottom surface of the first groove 9, the second groove 10 and the third groove 11
It is not connected with the substrate 1.
Attached drawing 3 and Fig. 4 are please referred to, step S4 is executed, specifically: in 9 side wall of first groove, the second groove 10
Side wall, the third groove 11 and 2 upper surface of the first epitaxial layer form the second epitaxial layer 3 of the second conduction type, tool
Body includes: the side wall and bottom surface, the third groove 11, described first in the first groove 9 and the second groove 10
2 upper surface of epitaxial layer forms the 6th epitaxial layer 7 of the second conduction type；Etch away the first groove 9 and the second groove
The 6th epitaxial layer 7 of 10 bottom surfaces forms second epitaxial layer 3.In some embodiments of the invention, described first
The side wall and bottom surface of groove 9 and the second groove 10, the third groove 11,2 upper surface of the first epitaxial layer use
Extension or the method for diffusion form the 6th epitaxial layer 7, further, in the first groove 9 and the second groove
10 side wall and bottom surface, the third groove 11,2 upper surface of the first epitaxial layer pass through extension or diffusion boron element or indium member
Any combination of element or aluminium element or three form the 6th epitaxial layer 7.Etch away the first groove 9 and second ditch
The 6th epitaxial layer 7 of 10 bottom surface of slot forms second epitaxial layer 3.
Attached drawing 4 is please referred to, step S5 is executed, specifically: in 10 bottom surface of 9 bottom surface of first groove and the second groove
The injection region 12 of the second conduction type is formed by ion implanting mode.At least partly surface exposure of the injection region 12 is in institute
State the upper surface of 10 bottom surface of 9 bottom surface of first groove and the second groove.The injection region 12 can by being epitaxially-formed,
It can also be formed by ion implanting and/or the method for diffusion.Further, the injection region 12 can pass through epitaxial growth shape
At the method shape of ion implanting and/or diffusion boron element or phosphide element or aluminium element or any combination of three can also be passed through
At.Preferably, the method that ion implanting can be used forms the injection region 12, forms the injection region 12 by ion implanting
The accumulated dose, depth distribution and surface uniformity that impurity can accurately be controlled can prevent spreading again for original impurity, while can realize
Self-aligned technology, to reduce capacity effect.The injection region is formed in the first groove 9 and 10 lower surface of the second groove
12, in the case where not increasing epitaxy layer thickness, the area of depletion region when device reverse operation can be improved.
Please refer to attached drawing 5 and Fig. 6, execute step S6 and S7, specifically: in the first groove 9 described second outside
The side wall for prolonging layer 3 forms the third epitaxial layer 4 of the first conduction type；It is led in the remainder filling first of the second groove 10
The fourth epitaxial layer 5 of electric type.It specifically includes: in 3 upper surface of the second epitaxial layer, 9 bottom surface of the first groove, described
3 side wall of the second epitaxial layer, the second groove 10 in one groove 9 form the 7th epitaxial layer 8；It etches away outside described second
Prolong the 7th epitaxial layer 8 of 3 upper surface of layer, 9 bottom surface of the first groove to described second in the first groove 9
The side wall of epitaxial layer 3 forms the third epitaxial layer 4 of the first conduction type, fills first in the remainder of the second groove 10
The fourth epitaxial layer 5 of conduction type.In some embodiments of the invention, in 3 upper surface of the second epitaxial layer, described first
Extension or diffusion are used in 3 side wall of the second epitaxial layer, the second groove 10 in 9 bottom surface of groove, the first groove 9
Method form the 7th epitaxial layer 8, further, 3 upper surface of the second epitaxial layer, 9 bottom surface of the first groove,
Pass through extension or diffusion P elements or arsenic in 3 side wall of the second epitaxial layer, the second groove 10 in the first groove 9
Any combination of element or both forms the 7th epitaxial layer 8.Etch away 3 upper surface of the second epitaxial layer, described first
The 7th epitaxial layer 8 of 9 bottom surface of groove forms the to the side wall of second epitaxial layer 3 in the first groove 9
The third epitaxial layer 4 of one conduction type fills the fourth epitaxial of the first conduction type in the remainder of the second groove 10
Layer 5.The epitaxial layer that different-thickness is arranged can maximize the anti-breakdown voltage capabilities for promoting device, while can reduce device side
Product, reduces element manufacturing cost.
Attached drawing 6 is please referred to, step S8 is executed, specifically: in 2 upper surface of the first epitaxial layer and the first groove 9
Remainder formed the second conduction type the 5th epitaxial layer 6.Further, the ion concentration of the 5th epitaxial layer 6 is high
In the ion concentration of second epitaxial layer 3.In some embodiments of the invention, in 2 upper surface of the first epitaxial layer and
The remainder of the first groove 9 forms the 5th epitaxial layer 6 using the method for extension or diffusion, further, in institute
The remainder for stating 2 upper surface of the first epitaxial layer and the first groove 9 passes through extension or diffusion boron element or phosphide element or aluminium
The method of any combination of element or three forms the 5th epitaxial layer 6.
Attached drawing 7 is please referred to, step S9 is executed, specifically: dielectric layer 13 is formed in 6 upper surface of the 5th epitaxial layer.Institute
Stating dielectric layer 13 is insulating layer, and sputtering can be used for the dielectric layer 13 or thermal oxide is formed.In some embodiments of the present invention
In, the dielectric layer 13 is the silicon oxide layer that thermal oxide is formed, and in subsequent doping step, the silicon oxide layer is as protection
Layer, and by the interlayer insulating film as resulting devices.
Attached drawing 7 is please referred to, step S10 and S11 are executed, specifically: etch the dielectric layer 13, the 5th epitaxial layer 6
Form the first contact hole 14, first contact hole 14 and the described 5th in the third epitaxial layer 4 and the first groove 9
Epitaxial layer 6 connects；Etch described the second of the dielectric layer 13, the 5th epitaxial layer 6 and 2 upper surface of the first epitaxial layer
Epitaxial layer 3 forms the second contact hole 15, and 15 lower surface of the second contact hole is connect with 2 upper surface of the first epitaxial layer.?
In some embodiments of the present invention, mask material is prepared in the upper surface of the 5th epitaxial layer 6, the mask material is specially
Second photoresist forms first contact hole 14 and second contact hole by etching on second photoresist layer
15, then remove second photoresist.Wherein, the method for etching includes dry etching and wet etching, it is preferred that the quarter used
The method of erosion is dry etching, and dry etching includes photoablation, gaseous corrosion, plasma etching etc., and dry etching is easily real
Now automation, treatment process are not introduced into pollution, cleannes height.In some embodiments of the invention, first contact hole 14
The 5th epitaxial layer 6 and the third epitaxial layer 4 and institute through the dielectric layer 13,3 upper surface of the second epitaxial layer
The 5th epitaxial layer 6 connection in first groove 9 is stated, second contact hole 15 runs through 2 upper surface of the first epitaxial layer
Second epitaxial layer 3 and the 5th epitaxial layer 6 connect with 2 upper surface of the first epitaxial layer.
Attached drawing 8 is please referred to, step S12 is executed, specifically: in 13 upper surface of dielectric layer, first contact hole 14
With formation high resistance polysilicon layer 16 in second contact hole 15.In 13 upper surface of dielectric layer, first contact hole 14
The high resistance polysilicon layer 16 is formed by the method for extension or diffusion in second contact hole 15.Specifically, described outer
The method prolonged or spread includes depositing operation.In some embodiments of the invention, depositing operation can be used in the medium
High resistance polysilicon layer 16 is formed in 13 upper surface of layer, first contact hole 14 and second contact hole 15, for example, deposition work
Skill can be selected from one of electron beam evaporation, chemical vapor deposition, atomic layer deposition, sputtering.Preferably, in the medium
In 13 upper surface of layer, first contact hole 14 and second contact hole 15 (referred to as using low-pressure chemical vapor deposition
LPCVD, i.e. Low Pressure Chemical Vapor Deposition) the high resistance polysilicon layer 16 is formed, formation
The purity is high of the high resistance polysilicon layer 16, uniformity are good.Such structure setting will be outside second epitaxial layer 3, the third
Prolong layer 4 and the 5th epitaxial layer 6 to connect by the high resistance polysilicon layer 16 with the terminal of device outermost end, is conducive to drop
The parasitic capacitance of low device.
A kind of power device terminal structure provided in an embodiment of the present invention is described in detail below in conjunction with Fig. 1 to Fig. 8.
The embodiment of the present invention provides a kind of power device terminal structure, and the power device terminal structure includes:
The substrate 1 of first conduction type；
It is formed in the first epitaxial layer 2 of the first conduction type of 1 upper surface of substrate；
It is sequentially formed in first groove 9, second groove 10 and the third groove 11 of 2 upper surface of the first epitaxial layer；
It is formed in 9 side wall of first groove, 10 side wall of the second groove, the third groove 11 and described first
Second epitaxial layer 3 of the second conduction type of 2 upper surface of epitaxial layer；
It is formed in the injection region 12 of the second conduction type of 10 bottom surface of 9 bottom surface of first groove and the second groove；
It is formed in the third epitaxial layer of the first conduction type of 3 side wall of the second epitaxial layer in the first groove 9
4；
It is filled in the fourth epitaxial layer 5 of the first conduction type of 10 remainder of second groove；
It is formed in the of the second conduction type of 9 remainder of 2 upper surface of the first epitaxial layer and the first groove
Five epitaxial layers 6；
It is formed in the dielectric layer 13 of 6 upper surface of the 5th epitaxial layer；
Etch the dielectric layer 13, the first contact hole 14 that the 5th epitaxial layer 6 is formed, first contact hole 14 with
The 5th epitaxial layer 6 connection in the third epitaxial layer 4 and the first groove 9；
Etch second extension of the dielectric layer 13, the 5th epitaxial layer 6 and 2 upper surface of the first epitaxial layer
The second contact hole 15 that layer 3 is formed, 15 lower surface of the second contact hole is connect with 2 upper surface of the first epitaxial layer；
The high resistant being formed in 13 upper surface of dielectric layer, first contact hole 14 and second contact hole 15 is more
Crystal silicon layer 16.
Technical solution of the present invention is related to designing and manufacturing for semiconductor devices, and semiconductor refers to that a kind of electric conductivity can be controlled
System, conductive extensions can be from insulator to the material changed between conductor, and common semiconductor material has silicon, germanium, GaAs etc., and
Silicon is most powerful, one kind for being most widely used in various semiconductor materials.Semiconductor is divided into intrinsic semiconductor, p-type
Semiconductor and N-type semiconductor, free from foreign meter and without lattice defect semiconductor is known as intrinsic semiconductor, in pure silicon crystal
It mixes triad (such as boron, indium, gallium), is allowed to replace the seat of silicon atom in lattice, P-type semiconductor is just formed, pure
Silicon crystal in mix pentad (such as phosphorus, arsenic), be allowed to replace the position of silicon atom in lattice, be formed N-type and partly lead
The conduction type of body, P-type semiconductor and N-type semiconductor is different, and in an embodiment of the present invention, the first conduction type is N-type, the
Two conduction types are p-type, in an embodiment of the present invention, if not otherwise specified, the preferred doping of every kind of conduction type from
Son is all that can be changed to the ion with same conductivity type, is just repeated no more below.
Specifically, the substrate 1 is the carrier in integrated circuit, and the substrate 1 plays the role of support, the substrate 1
Also assist in the work of the integrated circuit.The substrate 1 can be silicon substrate 1, or Sapphire Substrate 1 can also be
Silicon carbide substrates 1, it might even be possible to be silicon Chu substrate 1, it is preferred that the substrate 1 is silicon substrate 1, this is because 1 material of silicon substrate
Have the characteristics that low cost, large scale, conductive, avoids edge effect, yield can be increased substantially.In reality of the invention
Apply in example, the substrate 1 is the substrate 1 of the first conduction type, and first conduction type is N-type, the doping of the substrate 1 from
Son is phosphorus or arsenic etc., and 1 doping concentration of substrate is highly doped.
Referring next to attached drawing, power device terminal structure described above is elaborated.
In some embodiments of the invention, as shown in Fig. 2, the power device terminal structure includes the first conduction type
Substrate 1；It is formed in the first epitaxial layer 2 of the first conduction type of 1 upper surface of substrate.The doping concentration of the substrate 1
It is different from the doping concentration of first epitaxial layer 2.Preferably, the doping concentration of the substrate 1 is higher than first epitaxial layer 2
Doping concentration, the resistivity of substrate 1 described in the resistivity ratio of first epitaxial layer 2 is high at this time, reduce dead resistance, thus
Improve the breakdown reverse voltage of device.
In some embodiments of the invention, as shown in Fig. 2, the power device terminal structure includes being sequentially formed in institute
State the first groove, second groove and third groove of the first epitaxial layer upper surface.Further, the first groove, described
The depth of two grooves and the third groove is roughly equal；The width of the first groove is greater than the width of the second groove,
The width of the second groove is greater than the width of the third groove.In some embodiments of the invention, outside described first
The upper surface for prolonging layer 2 prepares mask material, and the mask material is specially the first photoresist, leads on first photoresist layer
Over etching forms the first groove 9, the second groove 10 and the third groove 11 for running through first epitaxial layer 2,
First photoresist is removed again.Wherein, the method for etching includes dry etching and wet etching, it is preferred that the etching used
Method be dry etching, dry etching includes photoablation, gaseous corrosion, plasma etching etc., and dry etching is easily realized
Automation, treatment process are not introduced into pollution, cleannes height.In some embodiments of the invention, the first groove 9, described
The bottom surface of second groove 10 and the third groove 11 is not connected with the substrate 1.
In some embodiments of the invention, as shown in figure 4, the power device terminal structure includes being formed in described the
One groove, 9 side wall, 10 side wall of the second groove, the third groove 11 and 2 upper surface of the first epitaxial layer second
Second epitaxial layer 3 of conduction type.In some embodiments of the invention, in the first groove 9 and the second groove
10 side wall and bottom surface, the third groove 11,2 upper surface of the first epitaxial layer use extension or the method for diffusion formation institute
The 6th epitaxial layer 7 is stated, further, side wall and bottom surface, the third in the first groove 9 and the second groove 10
Any of boron element or phosphide element or aluminium element or three by extension or is spread in groove 11,2 upper surface of the first epitaxial layer
Combination forms the 6th epitaxial layer 7.Etch away the 6th extension of 10 bottom surface of the first groove 9 and the second groove
Layer 7 forms second epitaxial layer 3.
In some embodiments of the invention, as shown in figure 4, the power device terminal structure includes being formed in described the
Injection region 12 described in the injection region 12 of second conduction type of 10 bottom surface of one groove, 9 bottom surface and the second groove is at least partly
Surface exposure is in the upper surface of 10 bottom surface of 9 bottom surface of first groove and the second groove.The injection region 12 can pass through
It is epitaxially-formed, can also be formed by ion implanting and/or the method for diffusion.Further, the injection region 12 can be with
By being epitaxially-formed, ion implanting and/or diffusion boron element or phosphide element or aluminium element or times of three can also be passed through
Combined method of anticipating is formed.Preferably, the method that ion implanting can be used forms the injection region 12, passes through ion implanting shape
The accumulated dose, depth distribution and surface uniformity that impurity can be accurately controlled at the injection region 12, can prevent expanding again for original impurity
It dissipates, while can realize self-aligned technology, to reduce capacity effect.In 10 following table of the first groove 9 and the second groove
Face forms the injection region 12, in the case where not increasing epitaxy layer thickness, depletion region when device reverse operation can be improved
Area.
In some embodiments of the invention, as shown in fig. 6, the power device terminal structure includes being formed in described the
The third epitaxial layer 4 of first conduction type of 3 side wall of the second epitaxial layer in one groove 9；It is filled in the second groove
The fourth epitaxial layer 5 of first conduction type of 10 remainders.Further, the third epitaxial layer 4 and the fourth epitaxial
The ion concentration of layer 5 is higher than the ion concentration of first epitaxial layer 2.In some embodiments of the invention, described second
3 upper surface of epitaxial layer, 9 bottom surface of the first groove, 3 side wall of the second epitaxial layer in the first groove 9, described second
The 7th epitaxial layer 8 is formed using extension or the method for diffusion in groove 10, further, on second epitaxial layer 3
Surface, 9 bottom surface of the first groove, 3 side wall of the second epitaxial layer in the first groove 9, in the second groove 10
The 7th epitaxial layer 8 is formed by any combination of extension or diffusion P elements or arsenic element or both.Etch away described
Two epitaxial layers, 3 upper surface, 9 bottom surface of the first groove the 7th epitaxial layer 8 to described in the first groove 9
The side wall of second epitaxial layer 3 forms the third epitaxial layer 4 of the first conduction type, fills in the remainder of the second groove 10
The fourth epitaxial layer 5 of first conduction type.The epitaxial layer that different-thickness is arranged can maximize the anti-breakdown voltage for promoting device
Ability, while can reduce device area, reduce element manufacturing cost.
In some embodiments of the invention, as shown in fig. 6, the power device terminal structure includes being formed in described the
5th epitaxial layer 6 of the second conduction type of 9 remainder of one epitaxial layer, 2 upper surface and the first groove.Further, institute
The ion concentration for stating the 5th epitaxial layer 6 is higher than the ion concentration of second epitaxial layer 3.In some embodiments of the invention,
It is formed in the remainder of 2 upper surface of the first epitaxial layer and the first groove 9 using the method for extension or diffusion described
5th epitaxial layer 6, further, the remainder in 2 upper surface of the first epitaxial layer and the first groove 9 pass through extension
Or the method for any combination of diffusion boron element or phosphide element or aluminium element or three forms the 5th epitaxial layer 6.
In some embodiments of the invention, as shown in fig. 7, the power device terminal structure includes being formed in described the
The dielectric layer 13 of five epitaxial layers, 6 upper surface.The dielectric layer 13 is insulating layer, and sputtering or hot oxygen can be used in the dielectric layer 13
Change and is formed.In some embodiments of the invention, the dielectric layer 13 is the silicon oxide layer that thermal oxide is formed, in subsequent doping
In step, the silicon oxide layer is as protective layer, and by the interlayer insulating film as resulting devices.
In some embodiments of the invention, as shown in fig. 7, the power device terminal structure includes etching the medium
The first contact hole 14 that layer 13, the 5th epitaxial layer 6 are formed, first contact hole 14 and the third epitaxial layer 4 and institute
State the 5th epitaxial layer 6 connection in first groove 9；Etch the dielectric layer 13, the 5th epitaxial layer 6 and described first
The second contact hole 15 that second epitaxial layer 3 of 2 upper surface of epitaxial layer is formed, 15 lower surface of the second contact hole with it is described
The connection of first epitaxial layer, 2 upper surface.In some embodiments of the invention, first contact hole 14 runs through the dielectric layer
13, in the 5th epitaxial layer 6 Yu the third epitaxial layer 4 and the first groove 9 of 3 upper surface of the second epitaxial layer
5th epitaxial layer 6 connection, second contact hole 15 is outside described the second of 2 upper surface of the first epitaxial layer
Prolong layer 3 and the 5th epitaxial layer 6 is connect with 2 upper surface of the first epitaxial layer.
In some embodiments of the invention, as shown in figure 8, the power device terminal structure includes being formed in be given an account of
High resistance polysilicon layer 16 in 13 upper surface of matter layer, first contact hole 14 and second contact hole 15.In the medium
The height is formed by the method for extension or diffusion in 13 upper surface of layer, first contact hole 14 and second contact hole 15
Hinder polysilicon layer 16.Specifically, the extension or the method for diffusion include depositing operation.In some embodiments of the invention,
Depositing operation can be used to be formed in 13 upper surface of dielectric layer, first contact hole 14 and second contact hole 15
High resistance polysilicon layer 16, for example, depositing operation can be selected from electron beam evaporation, chemical vapor deposition, atomic layer deposition, sputtering
One of.Preferably, it is used in 13 upper surface of dielectric layer, first contact hole 14 and second contact hole 15
Low-pressure chemical vapor deposition (abbreviation LPCVD, i.e. Low Pressure Chemi ca l Vapor Depos it i on) shape
At the high resistance polysilicon layer 16, the purity is high of the high resistance polysilicon layer 16 of formation, uniformity is good.Such structure setting will
Second epitaxial layer 3, the third epitaxial layer 4 and the 5th epitaxial layer 6 pass through the high resistance polysilicon layer 16 and device
The terminal of part outermost end connects, and advantageously reduces the parasitic capacitance of device.
The technical scheme of the present invention has been explained in detail above with reference to the attached drawings, according to the technical solution of the present invention, proposes one
Kind of power device terminal structure forms first groove, second groove and third groove by etching groove, by three not
With being repeatedly epitaxially formed the second epitaxial layer, third epitaxial layer, fourth epitaxial layer and the 5th epitaxial layer in width groove, can with
Under the premise of the process compatible of device, make to divide the termination extension structure that region forms junction depth and concentration gradient.And traditional structure
It compares, simple process, junction depth and concentration can be controlled by extension width and concentration, and production cost is low.Junction depth and concentration gradient
Raising voltage dividing ability can be maximized, device area is reduced, reduces the cost of manufacture of device, promote the performance of device.Pass through height
Epitaxial layer is connect by resistance polysilicon layer with the terminal of device outermost end, advantageously reduces the parasitic capacitance of device.The terminal structure
In the case where minimizing terminal structure length, device depletion region area is increased, and not will increase the parasitic capacitance of device, mentioned
The high Performance And Reliability of power device terminal structure.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
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|---|---|---|---|---|
| CN114582959A (en) * | 2022-05-06 | 2022-06-03 | 绍兴中芯集成电路制造股份有限公司 | Trench type power MOS device and manufacturing method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1557022A (en) * | 2001-09-19 | 2004-12-22 | ��ʽ���綫֥ | Semiconductor device and manufacturing method thereof |
| US20060043480A1 (en) * | 2004-09-01 | 2006-03-02 | Kabushiki Kaisha Toshiba | Semiconductor device and fabrication method of the same |
| CN102412260A (en) * | 2010-09-25 | 2012-04-11 | 上海华虹Nec电子有限公司 | Terminal protection structure of super-junction semiconductor device and fabrication method thereof |
| CN107204372A (en) * | 2017-07-19 | 2017-09-26 | 无锡新洁能股份有限公司 | A kind of channel-type semiconductor device and manufacture method for optimizing terminal structure |
| WO2018107429A1 (en) * | 2016-12-15 | 2018-06-21 | 深圳尚阳通科技有限公司 | Super junction component and manufacturing method therefor |
| CN108288587A (en) * | 2018-01-29 | 2018-07-17 | 贵州芯长征科技有限公司 | The preparation method of high pressure super-junction structure |
-
2018
- 2018-10-29 CN CN201811266036.9A patent/CN109360854A/en not_active Withdrawn
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1557022A (en) * | 2001-09-19 | 2004-12-22 | ��ʽ���綫֥ | Semiconductor device and manufacturing method thereof |
| US20060043480A1 (en) * | 2004-09-01 | 2006-03-02 | Kabushiki Kaisha Toshiba | Semiconductor device and fabrication method of the same |
| CN102412260A (en) * | 2010-09-25 | 2012-04-11 | 上海华虹Nec电子有限公司 | Terminal protection structure of super-junction semiconductor device and fabrication method thereof |
| WO2018107429A1 (en) * | 2016-12-15 | 2018-06-21 | 深圳尚阳通科技有限公司 | Super junction component and manufacturing method therefor |
| CN107204372A (en) * | 2017-07-19 | 2017-09-26 | 无锡新洁能股份有限公司 | A kind of channel-type semiconductor device and manufacture method for optimizing terminal structure |
| CN108288587A (en) * | 2018-01-29 | 2018-07-17 | 贵州芯长征科技有限公司 | The preparation method of high pressure super-junction structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114582959A (en) * | 2022-05-06 | 2022-06-03 | 绍兴中芯集成电路制造股份有限公司 | Trench type power MOS device and manufacturing method thereof |
| CN114582959B (en) * | 2022-05-06 | 2022-08-02 | 绍兴中芯集成电路制造股份有限公司 | Trench type power MOS device and manufacturing method thereof |
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