CN109344109A - The system and method for accelerating artificial intelligence to calculate in big data based on solid state hard disk - Google Patents
The system and method for accelerating artificial intelligence to calculate in big data based on solid state hard disk Download PDFInfo
- Publication number
- CN109344109A CN109344109A CN201811236270.7A CN201811236270A CN109344109A CN 109344109 A CN109344109 A CN 109344109A CN 201811236270 A CN201811236270 A CN 201811236270A CN 109344109 A CN109344109 A CN 109344109A
- Authority
- CN
- China
- Prior art keywords
- artificial intelligence
- hard disk
- solid state
- state hard
- big data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000013473 artificial intelligence Methods 0.000 title claims abstract description 49
- 239000007787 solid Substances 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims description 21
- 238000004364 calculation method Methods 0.000 claims description 8
- 238000012545 processing Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Power Sources (AREA)
Abstract
The present invention provides the systems for accelerating artificial intelligence to calculate in a kind of big data based on solid state hard disk, including solid state hard disk, IC chip is set in the solid state hard disk, its innovative point is: the IC chip is integrated by central microprocessor and hardware algorithm module, and the hardware algorithm module is realized using embedded programmable logic gate array module.The present invention is in solid state hard disk in main control chip, hardware-accelerated artificial intelligence operation is realized in the way of embedded field programmable gate array, first can solve to show card as high power consumption problem caused by artificial intelligence operation, second solves the problems, such as with low elasticity caused by pure hardware realization intelligent algorithm, and third solves the problems, such as high speed serialization computer expansion bus high bandwidth requirements caused by executing artificial intelligence operation at main frame end.
Description
Technical field
It is artificial the present invention relates to accelerating in intelligent Computation Technology field more particularly to a kind of big data based on solid state hard disk
The system of intelligence computation, and it is related to the method that artificial intelligence is accelerated to calculate in a kind of big data of solid state hard disk.
Background technique
Existing intelligent algorithm common are 1. and do artificial intelligence operation by display adapter, and 2. using firmly
Artificial intelligence operation is done in part acceleration, and it is that power consumption is excessively huge that method 1, which has a major defect, because display adapter is not special needle
It is specially designed to artificial intelligence operation.2 major defect of method is then to cause due to algorithm is followed the string with hardware implementation in people
Work intelligence is limited on.In addition method 1 and 2 then has common disadvantage, due to needing to big data data access simultaneously
It calculates, it is known that the bus bandwidth of huge amount high speed serialization computer expansion bus (PCIe) will be occupied, this is beyond the clouds in operation
It then will be greatly reduced the efficiency of whole system.
In the prior art, Chinese patent CN103413164B discloses one kind and uses embedded programmable in intelligent chip
The method that logic gate array realizes encryption and decryption functions, the technical solution are mentioned, a kind of device for realizing data encrypting and deciphering function, institute
Stating device includes system bus, channel, embedded microcontroller and smart card interface module, wherein described device further include by
The hardware enciphering and deciphering algoritic module of deciphering module and encrypting module composition, the device of the realization data encrypting and deciphering function,
In, using embedded programmable logic gate array module as the hardware encryption algorithm module.The technical solution discloses its master
It is to solve the speed of service slow problem when using software realization data (encryption and decryption) algorithm, and is not mentioned in the technical solution
To the acceleration for how carrying out hardware algorithm.
Traditional embedded programmable logic gate array module is made of combinatorial logic unit and sequential logic unit
Minimum unit into the Gate Array module generated after combination.The above-mentioned main operating basis of technical solution listed of documents 1
Combinatorial logic unit, therefore, the use of above scheme will almost inoperative sequential logic unit from embedded programmable
It is removed in logic gate array module, to reach the area for reducing embedded programmable logic gate array module, improves storage resource.
Chinese patent CN100369017C discloses a kind of encryption dress of static RAM programmable gate array chip
It sets and encryption method, the encryption device of the invention includes a piece of FLASH fpga chip and in FLASH FPGA and SRAM
The handshake circuit realized in FPGA and in FLASH fpga chip, by remaining logic for realizing the part in system function
Low-speed logic, to further increase the safety of system.The invention is the programmable gate core based on Static RAM
Therefore the encryption method of piece inevitably has the defect of Static RAM, such as when its power down, inside
The information of storage is just lost, and needs to re-start the load of information herein after powering on, this can virtually increase it is encrypted
The time of journey is not suitable for the data communication system of high speed.
Summary of the invention
To overcome power consumption existing in the prior art excessively huge and causing due to algorithm is followed the string with hardware implementation
Artificial intelligence on by limitation the problem of, the present invention provides accelerate people in a kind of big data based on solid state hard disk
The system and method for work intelligence computation.
The technical solution adopted by the present invention are as follows: accelerate that artificial intelligence calculates in a kind of big data based on solid state hard disk is
IC chip is arranged in the solid state hard disk in system, including solid state hard disk, it is characterised in that: the IC chip by
Central microprocessor and hardware algorithm module are integrated, and the hardware algorithm module uses embedded programmable logic gate array module
It realizes.
In one embodiment of the invention, the system also includes a main frame, the main frame is according to institute
It states embedded programmable logic gate array module resource and generates configuration file.
In one embodiment of the invention, the IC chip further includes a data cell and a program unit, institute
State the read-write operation that central microprocessor carries out data to the data cell and described program unit.
In one embodiment of the invention, the embedded programmable logic gate array of the hardware algorithm module use
Module realizes that it is written into high speed algorithm, to carry out the complicated data processing mode of high speed.
Accelerate based on artificial intelligence it is a further object to provide a kind of using by the big data of solid state hard disk
The method that the artificial intelligence of the system of calculation calculates, it is characterised in that: the following steps are included:
Artificial intelligence client software in main frame end is transferred to solid state hard disk by high speed serialization computer bus and is intended to
The characteristic of search；
The IC chip of the solid state hard disk then stores the data cell and described program unit in inside big
Data access does timely operation；
Then the client for the characteristic met directly being returned to calculator host by high speed serialization computer bus is soft
Part.
In one embodiment of the invention, the embedded programmable logic gate array module realizes hardware artificial intelligence fortune
It calculates, and the maximum flexibility of artificial intelligence's algorithm is provided, different algorithms and calculation magic arts are written according to different application demand
Data.
In one embodiment of the invention, the IC chip is by central microprocessor and hardware algorithm module collection
At the hardware algorithm module is realized using embedded programmable logic gate array module.
Compared with prior art, the beneficial effects of the present invention are: the present invention is in (SSD) solid state hard disk in main control chip,
Hardware-accelerated artificial intelligence operation is realized in the way of embedded field programmable gate array (eFPGA), first can solve
Using display card as high power consumption problem caused by artificial intelligence operation, second solves to realize manually with pure hardware (pure ASIC)
Low elasticity problem caused by intelligent algorithm, third solve to go here and there at a high speed caused by executing artificial intelligence operation at main frame end
Row computer expansion bus (PCIe) high bandwidth requirements problem.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is intelligent algorithm schematic diagram common in the art；
Fig. 2 is intelligent algorithm schematic diagram of the present invention；
Fig. 3 is that integrated chip of the present invention constitutes schematic diagram.
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.It should be noted that in the absence of conflict, following embodiment and implementation
Feature in example can be combined with each other that the present invention will be described in further detail.It should be appreciated that specific reality described herein
Example is applied only to explain the present invention, is not intended to limit the present invention.
Existing intelligent algorithm, common are:
First does artificial intelligence operation by display adapter；It is that power consumption is excessively huge that method one, which has a major defect, because of display
Adapter is not specially designed particular for artificial intelligence operation.
Second does artificial intelligence operation using hardware-accelerated；Two major defect of method is then to be lost because of algorithm with hardware implementation
Elasticity and lead to being limited in artificial intelligence.
In addition, method one and second having common disadvantage, due to needing to big data data access and calculating, it is known that will
The bus bandwidth for occupying huge amount high speed serialization computer expansion bus (PCIe), then will be greatly reduced in operation whole beyond the clouds
The efficiency of a system.Existing common intelligent algorithm either by display adapter auxiliary operation or is specifically designed hardware
Operation requires to read mass data by the storage device in big data, expends a large amount of high speed serialization computer expansion bus
(PCIe) bandwidth, and lack flexibility and expend electricity (as shown in Figure 1.)
For above-mentioned standing state, the present invention utilizes embedded field programmable door in the main control chip of (SSD) solid state hard disk
Array (eFPGA) mode realizes hardware-accelerated artificial intelligence operation, and first can solve to show card as artificial intelligence fortune
High power consumption problem caused by calculation, second solves to realize low elasticity caused by intelligent algorithm with pure hardware (pure ASIC)
Problem, third solve high speed serialization computer expansion bus (PCIe) caused by executing artificial intelligence operation at main frame end
High bandwidth requirements problem.
Specifically, the present invention discloses the system for accelerating artificial intelligence to calculate in a kind of big data based on solid state hard disk,
Including solid state hard disk, IC chip is set, and as shown in Figure 3: the IC chip is by center in the solid state hard disk
Microprocessor and hardware algorithm module are integrated, and the hardware algorithm module is real using embedded programmable logic gate array module
It is existing.This chip architecture, while there is the high-speed computation characteristic of " specific integrated circuit (ASIC) ", with " embedded programmable patrols
The high resiliency of volume Gate Array module array (FPGA) ".The part of ASIC realizes high speed solid hard disk master control design, the portion of eFPGA
Part provides the maximum flexibility of artificial intelligence's algorithm then to realize hardware artificial intelligence operation, according to different application demand
And different algorithms and calculation magic arts data are written.Further, which further includes a main frame, the calculating owner
Machine generates configuration file according to the embedded programmable logic gate array module resource.
The IC chip may also include a data cell and a program unit, and the central microprocessor is to the number
The read-write operation of data is carried out according to unit and described program unit.The embedded programmable logic that hardware algorithm module uses
Gate Array module realizes that it is written into high speed algorithm, to carry out the complicated data processing mode of high speed.
Accelerate based on artificial intelligence it is a further object to provide a kind of using by the big data of solid state hard disk
The method that the artificial intelligence of the system of calculation calculates, specifically, as shown in Figure 2: the following steps are included:
Artificial intelligence client software in main frame end is transferred to solid state hard disk by high speed serialization computer bus and is intended to
The characteristic of search；
The IC chip of the solid state hard disk then stores the data cell and described program unit in inside big
Data access does timely operation；
Then the client for the characteristic met directly being returned to calculator host by high speed serialization computer bus is soft
Part.Visual demand is updated intelligent algorithm by so design by the present invention, supports more artificial intelligence applications, and
Mass data transmission bandwidth and power consumption are saved, efficiency is promoted.
Above-mentioned embedded programmable logic gate array module realizes the operation of hardware artificial intelligence, and provides artificial intelligence's calculation
Different algorithms and calculation magic arts data are written according to different application demand for the maximum flexibility of method.The IC chip by
Central microprocessor and hardware algorithm module are integrated, and the hardware algorithm module uses embedded programmable logic gate array module
It realizes.
In conclusion the present invention utilizes embedded field programmable gate array in (SSD) solid state hard disk main control chip
(eFPGA) mode realizes hardware-accelerated artificial intelligence operation, and first can solve to show that card is made as artificial intelligence operation
At high power consumption problem, second solve the problems, such as with pure hardware (pure ASIC) realize intelligent algorithm caused by low elasticity,
Third solves high speed serialization computer expansion bus (PCIe) high band caused by executing artificial intelligence operation at main frame end
Wide needs of problems.
In the description of the present invention, it is to be understood that, term " coaxial ", " bottom ", " one end ", " top ", " middle part ",
The orientation or positional relationship of the instructions such as " other end ", "upper", " side ", " top ", "inner", " front ", " center ", " both ends " is
It is based on the orientation or positional relationship shown in the drawings, is merely for convenience of description of the present invention and simplification of the description, rather than instruction or dark
Show that signified device or element must have a particular orientation, be constructed and operated in a specific orientation, therefore should not be understood as pair
Limitation of the invention.
In the present invention unless specifically defined or limited otherwise, term " installation ", " setting ", " connection ", " fixation ",
Terms such as " being screwed on " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integral；It can be with
It is mechanical connection, is also possible to be electrically connected；It can be directly connected, two can also be can be indirectly connected through an intermediary
The interaction relationship of connection or two elements inside a element, unless otherwise restricted clearly, for the common of this field
For technical staff, the specific meanings of the above terms in the present invention can be understood according to specific conditions.
The preferred embodiment of the present invention has shown and described in above description, as previously described, it should be understood that the present invention is not office
Be limited to form disclosed herein, should not be regarded as an exclusion of other examples, and can be used for various other combinations, modification and
Environment, and can be changed within that scope of the inventive concept describe herein by the above teachings or related fields of technology or knowledge
It is dynamic.And changes and modifications made by those skilled in the art do not depart from the spirit and scope of the present invention, then it all should be appended by the present invention
In scope of protection of the claims.
Claims (7)
1. the system for accelerating artificial intelligence to calculate in a kind of big data based on solid state hard disk, including solid state hard disk, the solid-state
IC chip is set in hard disk main control chip, it is characterised in that: the IC chip is by central microprocessor and firmly
Part algoritic module is integrated, and the hardware algorithm module is realized using embedded programmable logic gate array module.
2. the system for accelerating artificial intelligence to calculate in the big data according to claim 1 based on solid state hard disk, feature
Be: the system also includes a main frame, the main frame is according to the embedded programmable logic gate array
Module resource generates configuration file.
3. the system for accelerating artificial intelligence to calculate in the big data according to claim 1 based on solid state hard disk, feature
Be: the IC chip further includes a data cell and a program unit, and the central microprocessor is to the data
Unit and described program unit carry out the read-write operation of data.
4. the system for accelerating artificial intelligence to calculate in the big data according to claim 2 or 3 based on solid state hard disk, special
Sign is: the embedded programmable logic gate array module that the hardware algorithm module uses realizes that it is written into height and calculates quickly
Method, to carry out the complicated data processing mode of high speed.
5. a kind of people using the system for accelerating artificial intelligence to calculate in the big data described in claim 1 based on solid state hard disk
The method of work intelligence computation, it is characterised in that: the following steps are included:
Artificial intelligence client software in main frame end is transferred to solid state hard disk by high speed serialization computer bus and is intended to
The characteristic of search；
The IC chip of the solid state hard disk then stores the data cell and described program unit in inside big
Data access does timely operation；
Then the client for the characteristic met directly being returned to calculator host by high speed serialization computer bus is soft
Part.
6. the method for accelerating artificial intelligence to calculate in the big data according to claim 5 based on solid state hard disk, feature
Be: the embedded programmable logic gate array module realizes the operation of hardware artificial intelligence, and provides artificial intelligence's algorithm
Maximum flexibility, be written according to different application demand different algorithms and calculation magic arts data.
7. the method for accelerating artificial intelligence to calculate in the big data according to claim 5 or 6 based on solid state hard disk, special
Sign is: the IC chip is integrated by central microprocessor and hardware algorithm module, and the hardware algorithm module uses
Embedded programmable logic gate array module is realized.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811236270.7A CN109344109B (en) | 2018-10-23 | 2018-10-23 | System and method for accelerating artificial intelligence calculation in big data based on solid state disk |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811236270.7A CN109344109B (en) | 2018-10-23 | 2018-10-23 | System and method for accelerating artificial intelligence calculation in big data based on solid state disk |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109344109A true CN109344109A (en) | 2019-02-15 |
| CN109344109B CN109344109B (en) | 2022-07-26 |
Family
ID=65311207
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811236270.7A Active CN109344109B (en) | 2018-10-23 | 2018-10-23 | System and method for accelerating artificial intelligence calculation in big data based on solid state disk |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109344109B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109947694A (en) * | 2019-04-04 | 2019-06-28 | 上海威固信息技术股份有限公司 | A kind of Reconfigurable Computation storage fusion flash memory control system |
| CN110069834A (en) * | 2019-04-01 | 2019-07-30 | 京微齐力(北京)科技有限公司 | A kind of system-in-a-package method of integrated fpga chip and artificial intelligence chip |
| CN110070187A (en) * | 2019-04-18 | 2019-07-30 | 山东超越数控电子股份有限公司 | A kind of design method of the portable computer towards artificial intelligence application |
| CN112580285A (en) * | 2020-12-14 | 2021-03-30 | 深圳宏芯宇电子股份有限公司 | Embedded server subsystem and configuration method thereof |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101339492A (en) * | 2008-08-11 | 2009-01-07 | 湖南源科创新科技股份有限公司 | Native SATA solid-state hard disk controller |
| CN101373493A (en) * | 2008-09-22 | 2009-02-25 | 浪潮电子信息产业股份有限公司 | A logic verification method for SOC chips dedicated to multimedia storage gateways |
| CN101634936A (en) * | 2008-07-23 | 2010-01-27 | 深圳市中深瑞泰科技有限公司 | Method for achieving interfaces between ARM architecture processor and hard disk through FPGA |
| CN102117183A (en) * | 2010-01-04 | 2011-07-06 | 翔晖科技股份有限公司 | Computer device and method for using solid state disk in computer device |
| CN104834484A (en) * | 2015-05-11 | 2015-08-12 | 上海新储集成电路有限公司 | Data processing system and processing method based on embedded type programmable logic array |
| CN105589938A (en) * | 2015-12-13 | 2016-05-18 | 公安部第三研究所 | Image retrieval system and retrieval method based on FPGA |
| CN105843753A (en) * | 2015-02-02 | 2016-08-10 | Hgst荷兰公司 | Logical block address mapping for hard disk drives |
| CN106228238A (en) * | 2016-07-27 | 2016-12-14 | 中国科学技术大学苏州研究院 | The method and system of degree of depth learning algorithm is accelerated on field programmable gate array platform |
| CN106598889A (en) * | 2016-08-18 | 2017-04-26 | 湖南省瞬渺通信技术有限公司 | SATA (Serial Advanced Technology Attachment) master controller based on FPGA (Field Programmable Gate Array) sandwich plate |
| CN107038134A (en) * | 2016-11-11 | 2017-08-11 | 济南浪潮高新科技投资发展有限公司 | A kind of SRIO interface solid hard disks system and its implementation based on FPGA |
| CN108090560A (en) * | 2018-01-05 | 2018-05-29 | 中国科学技术大学苏州研究院 | The design method of LSTM recurrent neural network hardware accelerators based on FPGA |
| CN207965873U (en) * | 2018-03-20 | 2018-10-12 | 深圳市腾讯计算机系统有限公司 | Artificial intelligence accelerator card and server |
-
2018
- 2018-10-23 CN CN201811236270.7A patent/CN109344109B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101634936A (en) * | 2008-07-23 | 2010-01-27 | 深圳市中深瑞泰科技有限公司 | Method for achieving interfaces between ARM architecture processor and hard disk through FPGA |
| CN101339492A (en) * | 2008-08-11 | 2009-01-07 | 湖南源科创新科技股份有限公司 | Native SATA solid-state hard disk controller |
| CN101373493A (en) * | 2008-09-22 | 2009-02-25 | 浪潮电子信息产业股份有限公司 | A logic verification method for SOC chips dedicated to multimedia storage gateways |
| CN102117183A (en) * | 2010-01-04 | 2011-07-06 | 翔晖科技股份有限公司 | Computer device and method for using solid state disk in computer device |
| CN105843753A (en) * | 2015-02-02 | 2016-08-10 | Hgst荷兰公司 | Logical block address mapping for hard disk drives |
| CN104834484A (en) * | 2015-05-11 | 2015-08-12 | 上海新储集成电路有限公司 | Data processing system and processing method based on embedded type programmable logic array |
| CN105589938A (en) * | 2015-12-13 | 2016-05-18 | 公安部第三研究所 | Image retrieval system and retrieval method based on FPGA |
| CN106228238A (en) * | 2016-07-27 | 2016-12-14 | 中国科学技术大学苏州研究院 | The method and system of degree of depth learning algorithm is accelerated on field programmable gate array platform |
| CN106598889A (en) * | 2016-08-18 | 2017-04-26 | 湖南省瞬渺通信技术有限公司 | SATA (Serial Advanced Technology Attachment) master controller based on FPGA (Field Programmable Gate Array) sandwich plate |
| CN107038134A (en) * | 2016-11-11 | 2017-08-11 | 济南浪潮高新科技投资发展有限公司 | A kind of SRIO interface solid hard disks system and its implementation based on FPGA |
| CN108090560A (en) * | 2018-01-05 | 2018-05-29 | 中国科学技术大学苏州研究院 | The design method of LSTM recurrent neural network hardware accelerators based on FPGA |
| CN207965873U (en) * | 2018-03-20 | 2018-10-12 | 深圳市腾讯计算机系统有限公司 | Artificial intelligence accelerator card and server |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110069834A (en) * | 2019-04-01 | 2019-07-30 | 京微齐力(北京)科技有限公司 | A kind of system-in-a-package method of integrated fpga chip and artificial intelligence chip |
| CN109947694A (en) * | 2019-04-04 | 2019-06-28 | 上海威固信息技术股份有限公司 | A kind of Reconfigurable Computation storage fusion flash memory control system |
| CN110070187A (en) * | 2019-04-18 | 2019-07-30 | 山东超越数控电子股份有限公司 | A kind of design method of the portable computer towards artificial intelligence application |
| CN112580285A (en) * | 2020-12-14 | 2021-03-30 | 深圳宏芯宇电子股份有限公司 | Embedded server subsystem and configuration method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109344109B (en) | 2022-07-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109344109A (en) | The system and method for accelerating artificial intelligence to calculate in big data based on solid state hard disk | |
| KR102368970B1 (en) | Intelligent high bandwidth memory appliance | |
| US20190303003A1 (en) | METHOD AND APPARATUS TO ENABLE INDIVIDUAL NON VOLATILE MEMORY EXPRESS (NVMe) INPUT/OUTPUT (IO) QUEUES ON DIFFERING NETWORK ADDRESSES OF AN NVMe CONTROLLER | |
| DE102020127924A1 (en) | SHARED STORAGE SPACE BELOW DEVICES | |
| CN103034295B (en) | The reconfigurable micro server that I/O capability strengthens | |
| CN109284250A (en) | A kind of calculating acceleration system and its accelerated method based on large-scale F PGA chip | |
| CN102737270B (en) | A kind of bank intelligent card chip secure coprocessor based on domestic algorithm | |
| CN114124389B (en) | A national secret algorithm FPGA deployment method and system based on reconfigurable computing | |
| WO2019190682A1 (en) | System, apparatus and method for handshaking protocol for low power state transitions | |
| CN112035902A (en) | Encryption module for high-speed high-concurrency application | |
| CN107402902A (en) | A kind of heterogeneous computing platforms and the accelerated method based on heterogeneous computing platforms | |
| CN214122946U (en) | High-speed national cryptographic algorithm password card based on FPGA | |
| US12174955B2 (en) | Integrated circuit side-channel mitigation mechanism | |
| DE102020130555A1 (en) | ADAPTIVE DATA SENDING BASED ON LOAD FUNCTIONS | |
| CN205507633U (en) | High performance operation PCI -e accelerator card based on FPGA | |
| DE112018004329T5 (en) | CONTROL BLOCKS FOR PROCESSOR POWER MANAGEMENT | |
| CN111581152A (en) | Reconfigurable hardware acceleration SOC chip system | |
| US11693940B2 (en) | Partitioned platform security mechanism | |
| CN110287142B (en) | Multifunctional space-borne supercomputing device and satellite | |
| CN112232523A (en) | Domestic artificial intelligence computing equipment | |
| CN204390237U (en) | A kind of encryption and decryption card of Based PC I-E bussing technique | |
| CN111159074A (en) | Super-large-scale data hash operation accelerator card based on FPGA | |
| Kim et al. | Compression accelerator for hadoop appliance | |
| US10416887B1 (en) | Hybrid storage device and system | |
| WO2020121359A1 (en) | System, method, and program for increasing efficiency of database queries |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20190215 Assignee: Zhongguancun Technology Leasing Co.,Ltd. Assignor: JIANGSU HUACUN ELECTRONIC TECHNOLOGY Co.,Ltd. Contract record no.: X2022980017352 Denomination of invention: System and method for accelerating AI calculation in big data based on SSD Granted publication date: 20220726 License type: Exclusive License Record date: 20220930 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: System and method for accelerating AI calculation in big data based on SSD Effective date of registration: 20221008 Granted publication date: 20220726 Pledgee: Zhongguancun Technology Leasing Co.,Ltd. Pledgor: JIANGSU HUACUN ELECTRONIC TECHNOLOGY Co.,Ltd. Registration number: Y2022980017514 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| EC01 | Cancellation of recordation of patent licensing contract |
Assignee: Zhongguancun Technology Leasing Co.,Ltd. Assignor: JIANGSU HUACUN ELECTRONIC TECHNOLOGY Co.,Ltd. Contract record no.: X2022980017352 Date of cancellation: 20241009 |
|
| EC01 | Cancellation of recordation of patent licensing contract | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Granted publication date: 20220726 Pledgee: Zhongguancun Technology Leasing Co.,Ltd. Pledgor: JIANGSU HUACUN ELECTRONIC TECHNOLOGY Co.,Ltd. Registration number: Y2022980017514 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right |