CN109327410A - A kind of improvement three-level CLOS routing algorithm intersected based on FPGA - Google Patents
A kind of improvement three-level CLOS routing algorithm intersected based on FPGA Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/15—Interconnection of switching modules
- H04L49/1515—Non-blocking multistage, e.g. Clos
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/101—Packet switching elements characterised by the switching fabric construction using crossbar or matrix
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/15—Interconnection of switching modules
- H04L49/1515—Non-blocking multistage, e.g. Clos
- H04L49/1523—Parallel switch fabric planes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
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- H04Q11/00—Selecting arrangements for multiplex systems
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Abstract
The present invention relates to a kind of improvement three-level CLOS routing algorithms intersected based on FPGA, the present invention is based on the internal chiasma abilities of FPGA, to realize that the input and output of fiber-optic signal route interleaving function, realize the routing nested algorithm of two layers of three-level CLOS network, first layer three-level CLOS network increases the layout strategy of intergrade merging, and 4 interface channels are increased to by 1 interface channel of conventional architectures between input and output grade and switching stage, increase route selection space, routing in second layer CLOS network query function FPGA piece, vertical cut mode is realized under the scene that this plate intersects, it is not take up switching stage resource, increase route selection space, to have the advantage for substantially reducing blocking rate under the scene of high capacity of switch.The present invention increases route selection space by the improvement on framework and algorithm, substantially reduces blocking rate, improves equipment performance advantage and user experience.
Description
Technical field
The present invention relates to a kind of improvement three-level CLOS routing algorithm intersected based on FPGA, for fiber-optic signal SDH and
10GE intersects with carrying out time slot and channel, by improving nested type three-level CLOS algorithm network routing, according to equipment input and output
Route request calculates the routing table of the every level-one of three-level CLOS, and route results are configured in FPGA and cross chips and realize light
The function that optical fiber signaling routing intersects.
Background technique
CLOS network is classical strictly non-blocking multistage interconnecting and switching network, and the network is extensive in optical communication network
It uses, it has the characteristics of scalability, fixed switching delay, the freedom and order of data transmission.Classical CLOS net
Network is the totally interconnected symmetrical network of three-level, and it includes input stage/intergrade/output stage three-level, input stage has r n*m intersection
Switch, intergrade have m r*r crossbar switch, and output stage has r m*n crossbar switch, network share N=n*r input and
Output, each intergrade switch and each input stage switch and output stage switch has and an only connecting link.It is mentioned from CLOS
Since out, people conduct in-depth research its topological structure and connection performance and its control routing algorithm, also achieve not
Few achievement, wherein having many research achievements to the routing policy etc. for how reducing blocking rate Optimal Routing Algorithm, such as in selecting
Intercaste unit makes to realize using strategies such as calculating the smallest optimal paths of routing blocking probability.The routing algorithm of traditional clos according to
The three-level CLOS network architecture establishes algorithm model, needs the cross-pair for the input and output realized as the defeated of algorithm model outer layer
Enter parameter, algorithm takes optimal routing policy to carry out three according to input stage/intergrade/output stage resource occupation/idle condition
Grade route selection provides the pathfinding of intermediate path as a result, the routing for completing to be input to output intersects.In current entire IP network stream
Under the trend that amount and scale constantly expand, to the high capacity of switch exchange capacity in optic communication, more stringent requirements are proposed, is energy
Realize that in the cross exchange capacity of Tbits rank, the requirement of resource is used for large capacity and clog-free rate and minimum for capacity,
Traditional input stage/output stage and the cross exchange energy that intergrade has and only a connecting link can no longer meet large capacity
Power, for 192 tunnel input and output high capacity of switch of three-level CLOS framework (m=32, r=12, n=16), conventional frame is to small
The time-slot cross of granularity still has blocking probability.
Summary of the invention
In view of the situation of the prior art, the present invention is inputted for 192 tunnels of three-level CLOS framework (m=32, r=12, n=16)
High capacity of switch application demand is exported, is needed for the time slot of realization optical communication field difference fiber-optic signal and the function of channel intersection
It asks, to large capacity fine granularity time-slot cross, there are still blocking probabilities in traditional three-level CLOS network architecture, defeated to increase input
Out grade to intergrade connecting link can routing resource, a connecting link of traditional input and output grade to intergrade is changed
For 4 connecting links, increase intergrade routing resource, reduces blocking rate, while in order to reduce intergrade resource high capacity of switch
The problem of resource anxiety under scene, devises nesting level three-level CLOS network, and first layer three-level CLOS has been calculated in routing algorithm
After network pathfinding path, the pathfinding path of the three-level CLOS network of nesting level is calculated, when input and output are all on nesting level
Three-level CLOS network on intersected, then the three-level CLOS routing algorithm for not needing to carry out first layer calculates, without using the
The intergrade resource of one layer of three-level CLOS network reduces the blocking probability under the intersection of large capacity fine granularity, while nesting level
It is upper directly to intersect switching, reduce signal cross propagation delay time.
The technical solution adopted by the present invention is that: a kind of improvement three-level CLOS routing algorithm intersected based on FPGA, feature
It is, this routing algorithm operation platform is Bits grades of intersection equipment of large capacity I, including 15 pieces of boards, wherein 12 pieces of boards are industry
It is engaged in plate, 2 pieces of boards are power board, 1 piece of master control borad, the road three-level CLOS of operation control scheduler program and this framework in master control borad
By algorithm, it is furnished with SOC chip zynq7030 and fpga chip on business board, is furnished with cross chips, each business on power board
FPGA on plate has 48*48 input and output crossing, which is divided into the three-level CLOS network rack of first layer
The cross matrix of input stage 16*32 cross matrix and output stage 32*16 in structure, intergrade realized by two pieces of power boards, every piece
There is the crossing of 4 48*48 on power board, the crossing of each 48*48 combines realization by 4 cross chips, because
Each cross chips have the crossing of 12*12, and 12 pieces of business boards have divided a part of crossing 16*32 as input stage,
A part of crossing 32*16 is then made of the unit of 8 48*48 as output stage, intergrade, therefore first layer three-level CLOS
Network architecture input stage has the crossbar switch of 12 16*32, and intergrade has the crossbar switch of 8 48*48, and output stage has 12
The crossbar switch of 32*16, wherein input stage and each unit of switching stage have four connecting links, and output stage and switching stage are each
Unit equally has four connecting links, therefore each unit of input stage 32 outputs are 4 connecting links and 8 switching stages respectively
The product of unit, 32 inputs of each unit of output stage are also that same calculate is got；
When calculating the triple routing access of input and output 192*192 cross matrix with the three-level CLOS framework that intergrade merges,
The input specified according to user or output unit number which unit of i.e. 12 inputs or output stage, select 16 in each unit
Which channel of a optical-fibre channel, if what is realized is not that channel intersects and needs to realize time-slot cross, user also needs to specify
Which time slot 64 time slots in the channel is needed to carry out intersection switching, optional time slot granularity includes VC-12/VC-4/VC-
16c/VC-64c；
The input and output cross-pair that three-level CLOS routing algorithm is then specified by user calculates input/defeated according to the network architecture
Out/intergrade routing table；
The newly-built crossbar logic implementation process of first layer three-level CLOS routing algorithm needs newly-built intersection column when user gives
Table, what algorithm first determined whether currently to create intersect whether with have the repetition intersected there are output port or time slot, if repeatedly
Then delete original cross-pair, then start to create current cross tabulating, first determine whether input-output unit number whether one
Sample, thinks to intersect on the same business board and carries out if the same, which is directly realized by FPGA, directly calculates the
The routing of two layers of CLOS network, without using the intergrade resource of first layer CLOS network, if number it is different if first determine whether be
No there are output stage duplications, i.e., have had routing to be output to corresponding output unit in the presence of the newly-built input signal of needs and be then multiplexed this
Routing, only in output unit, that creates the routing table of an output stage, updates all routing iinformations；If there is no output
Grade duplication then judges whether there is intergrade duplication, i.e., has had routing to be output to institute with the presence or absence of the newly-built input signal of needs
The intergrade unit of selection, and if so, newly-increased intergrade and output stage routing iinformation, if there is no then judging whether there is
Intergrade multiplexing, i.e., it is unused full with the presence or absence of the routing but its channel that have built up an intergrade, and remaining space can hold
It receives currently built cross time-slot size, exists, update intergrade and input stage routing table, otherwise calculate an idle road
By being supplied to current cross-reference；
The deletion crossbar logic implementation process of first layer three-level CLOS routing algorithm, when user gives the intersection column for needing to delete
Table, whether algorithm first determines whether the current input-output unit number for deleting intersection, equally then directly in second layer three-level
Input and output cross tabulating is updated in CLOS routing algorithm carries out intermediate router-level topology, it is different then first to delete output stage routing
Table, then judges whether intergrade routing is used multiple times, and does not delete intergrade routing if being used multiple times, judges defeated
Enter whether grade routing is used multiple times, do not delete input stage routing if being used multiple times, completes the deletion behaviour of the intersection
Make；
After the triple routing table of three-level CLOS network of first layer has been calculated in routing algorithm, due to input and output grade element number
Identical routing is the intersection completed on same business board in fact, and the routing of same input and output is merged, industry is worked as
When having the interleaving route of 10GE in the routing table on business plate, the channel interleaving route of 10GE is extracted as second layer three-level
The input of CLOS algorithm network routing, to calculate the triple routing table of the three-level CLOS network on each business board, the second layer
The framework of three-level CLOS network, input stage have the crossbar switch of 12 4*8, and intergrade has the crossbar switch of 8 12*12, output
Grade has a crossbar switch of 12 8*4, input stage output stage and intergrade has and an only connecting link, three-level CLOS net
Network is traditional three-level CLOS network, and strictly non-blocking, algorithm need to calculate the 10GE of second layer three-level CLOS network
The routing table that channel intersects carries out cross-over configuration according to the cross-over configuration register that configuration FPGA is provided；
Input and output on same business board are routed and are made by the routing algorithm logic that the channel of second layer three-level CLOS network intersects
For the input of algorithm, it is first determined whether the same input intersection established has had a routing there are output stage duplication
Access reaches output stage unit, is directly multiplexed the access at this time, only need to establish a routing table in output stage and complete that this is new
It builds, then judges whether there is intergrade duplication if there is no output stage duplication, that is, the same input intersection established has had
One access reaches intergrade, is directly multiplexed the access at this time, and only need to establish routing table in intergrade and output stage completes this
It is secondary newly-built, it is replicated if there is no intergrade, then calculates an idle routing access for this cross-reference, update simultaneously
It is newly-built to complete this for triple routing table；
The calculating that wherein first layer three-level CLOS network routes access of this routing algorithm frame is realized using python language, is led to
Cross the complex logic that algorithm is realized using the ability of matrix operation and the data processing of the language such as the numpy/pandas of python
And the storage and inquiry of data；
The routing data of calculating, which provide, obtains interface, calls for C++, and the calculating that second layer three-level CLOS network routes access uses
C++ is realized, is packaged into C++ algorithm functional module class and is carried out calling for Service control process code.
The beneficial effects of the present invention are: being handed at present in the channel of optical communication field three-level CLOS architecture combined FPGA and time slot
Fork ability is designed high capacity of switch exchange, and first layer three-level CLOS network design input stage/output stage is had with intergrade
A plurality of connecting link realizes the channel cross-reference first layer nesting level three-level CLOS framework of FPGA, realizes that this plate intersects feelings
The scheme that intergrade resource is not used under condition, in current optical communication field rarely this kind of design scheme.The present invention is to be based on
Under the time slot and channel crossing of FPGA, the improvement on algorithm framework has been carried out to traditional L 3 CLOS crossed network,
Using intergrade to merge in routing algorithm, this plate intersects the strategy for not using intergrade resource and two layers of CLOS crossover network is embedding
Set realizes the crossover network of large capacity, realizes and realizes that the routing of the large capacity of fiber-optic signal intersects energy in optical communication field
Power.
The present invention is optimized and improves to traditional three-level CLOS network architecture first, using two layers of three-level CLOS net
Network realizes the crossing of large capacity I Bits rank, in the cross exchange of the fiber-optic signal of processing access, can handle simultaneously
The channel 10GE intersects the time-slot cross of SDH, meets the high capacity of switch demand of current optical fiber signal, the analysis to fiber-optic signal
The technical support of effective preceding terminated line is provided with processing, efficiently solves demand of the client to high capacity of switch.
Bits grades of intersection equipment of the large capacity I have deployment to run in many places fiber cabling, efficiently solve client
Demand to high capacity of switch, the equipment are also that company creates certain profit on sales, are increasingly becoming the representative of company and produce
Product, and realize with function in equipment architecture design and obtain city-level innovation awards.
The crossing that device algorithm design architecture is realized based on FPGA itself simultaneously, increases three-level CLOS network expansion
Improved flexibility, the obstruction for constructing multilayer nest three-level CLOS network and intergrade being used to merge solution high capacity of switch are general
Rate is innovated in design and for the first time, and the same input-output unit, which intersects, can not use intergrade route resource, solves biography
The problem for three-level CLOS network intergrade routing resource anxiety of uniting, input stage and output stage and intergrade are had and are only had by traditional
One connecting link design has been improved to 4 interface channels, effectively increases the sky of input and output grade Yu intergrade route selection
Between.
Same output unit is intersected since without using intergrade route resource, algorithm flow shortens, so it is newly-built
The response speed of intersection significantly improves, and solves the problems, such as that the previous newly-built intersection user experience of similar cross equipment is bad.
In short, the present invention is under time slot and channel crossing based on FPGA, to traditional L 3 CLOS crossed network
The improvement on algorithm framework has been carried out, the plan that this plate intersection does not use intergrade resource is merged using intergrade in routing algorithm
Summary and two layers of CLOS crossover network nesting realize the crossover network of large capacity, and optical fiber is realized in realization in optical communication field
The routing crossing of the large capacity of signal.
Detailed description of the invention
Fig. 1 is hardware device aspect graph of the present invention；
Fig. 2 is first layer three-level CLOS network cross matrix figure of the present invention；
Fig. 3, which is that first layer three-level CLOS algorithm network routing of the present invention is newly-built, intersects flow chart；
Fig. 4 is that first layer three-level CLOS algorithm network routing of the present invention deletes intersection flow chart；
Fig. 5 is second layer three-level CLOS network cross matrix figure of the present invention；
Fig. 6 is the newly-built routing flow chart of second layer three-level CLOS algorithm network routing of the present invention.
Specific embodiment
Operation platform of the present invention is Bits grades of intersection equipment of large capacity I, and equipment need to stick with 12 pieces of business boards, 2 pieces of exchanges
Plate, 1 piece of master control borad control program starting after device power, on each board, board operating status lamp is shown on every piece of board,
Equipment is controlled and is interconnected between network management and equipment by cable or interchanger, is made the two in the same local area network, be can be carried out net
Network communication, first B/S network management establish device model, fill in device-dependent message such as ip address port equipment id etc., enter
The control interface of TBits grades of equipment, checks board situation in place, and click-to-call service view can newly be established diplomatic relations in service view
The operations such as fork/deletion intersection, click newly-built intersection, and pop-up intersection information input frame selects input/output board card number/input and output
Port numbers/output signal type/output granularity/output bandwidth are also to need selection input defeated if SDH intersects if fork of establishing diplomatic relations
Low-order and high-order time slot out after selection is completed, is clicked and is created, and pop-up creates the prompting frame that successfully fails, in list if success
Middle reality currently creates successfully routing, does not show if failure；Newly-built equipment operation program when issuing receives control and refers to
It enables, newly-built crosstab is passed to algoritic module, algoritic module calculates output first layer three-level CLOS network routing table and the second layer
Three-level CLOS network routing table, master control borad obtain routing table and information are issued to business board progress register configuration, configure FPGA
Routing channel or gap information, configure power board on cross chips routing iinformation, complete with postpone response is returned to step by step
B/S network management, which shows to create, successfully to fail and refreshes current routing table, using Error Detector equipment according to the inputoutput pair of routing table
Should be related to, connect input optical fibre and output optical fibre, configured input signal format carry out it is luminous, detect Error Detector in whether receive
Signal and without error code；Intersect if user deletes, choose the routing for needing to delete in route list frame, clicks to delete to intersect and press
Button, pop-up delete intersects successfully or failure result, when delete intersect instruction and issue when, deletion intersection content is passed to calculation by master control
Method, algorithm carry out delete operation, two layers of three-level CLOS network routing table are updated, configuration information is issued to business board
And cross board, register configuration is carried out to FPGA and cross chips；The signal for deleting input and output cross-pair is tested with Error Detector
It shows obstructed.
Concrete methods of realizing is as follows:
As shown in Figure 1, wherein 12 pieces of boards are business board, 2 pieces of boards are power board, 1 piece of master control borad comprising 14 pieces of boards.
Operation controls scheduler program and the three-level CLOS routing algorithm of this framework in master control borad, is furnished with SOC on business board
Chip zynq7030 and fpga chip are furnished with cross chips on power board.
FPGA on each business board has 48*48 input and output crossing, which is divided into first layer
The three-level CLOS network architecture in input stage 16*32 cross matrix and output stage 32*16 cross matrix, intergrade is by two pieces
Power board realizes that, with the crossing of 4 48*48 on every piece of power board, the crossing of each 48*48 is by 4 intersection cores
Piece combination is realized, because each cross chips have the crossing of 12*12.12 pieces of business boards have divided a part of crossing
16*32 is then made of the unit of 8 48*48 as input stage, a part of crossing 32*16 as output stage, intergrade, and three
The network architecture block diagram of grade CLOS framework (m=32, r=12, n=16) is as shown in Fig. 2, wherein input stage and each unit of switching stage
There are four connecting links, output stage and each unit of switching stage equally there are four connecting links, therefore each unit of input stage
32 outputs are the product of 4 connecting links and 8 switching stage units respectively, and 32 inputs of each unit of output stage are also same
Sample calculating is got.
The triple routing access of input and output 192*192 cross matrix is calculated with the three-level CLOS framework that intergrade merges
When, the more input specified of user or output unit is numbered i.e. 12 and is inputted or which unit of output stage, selects in each unit
Which channel of 16 optical-fibre channels is selected, if what is realized is not that channel intersects and needs to realize time-slot cross, user is also needed
Specified that the time slot of where writing of 64 time slots in the channel is needed to carry out intersection switching, optional time slot granularity includes VC-12/VC-
4/VC-16c/VC-64c.The input and output cross-pair that three-level CLOS routing algorithm is then specified by user, according to network architecture meter
Calculate input/output/intergrade routing table.
Newly-built crossbar logic implementation process such as Fig. 3 of first layer three-level CLOS routing algorithm, when user gives needs newly
The cross tabulating built, what algorithm first determined whether currently to create intersect whether with have the weight intersected there are output port or time slot
It is multiple, original cross-pair is deleted if repeating, then starts to create current cross tabulating, first determines whether input-output unit
Whether number, thinks to intersect on the same business board and carries out if equally, which is directly realized by FPGA,
The routing of second layer CLOS network is directly calculated, without using the intergrade resource of first layer CLOS network, if number is different
It is first determined whether there are output stages to replicate (newly-built input signal is needed to have routing to be output to corresponding output unit)
It is then multiplexed the routing, only that creates the routing table of an output stage in output unit, updates all routing iinformations；If no
Then judging whether there is intergrade duplication there are output stage duplication (needs newly-built input signal to have routing to be output to institute
The intergrade unit of selection), and if so, newly-increased intergrade and output stage routing iinformation, if there is no then judging whether there is
Intergrade multiplexing (has built up the routing of an intergrade but its channel is unused full, and remaining space can accommodate current institute
Build cross time-slot size) exist, intergrade and input stage routing table are updated, an idle routing is otherwise calculated and is supplied to
Current cross-reference.
Deletion crossbar logic implementation process such as Fig. 4 of first layer three-level CLOS routing algorithm, is deleted when user gives needs
Whether the cross tabulating removed, algorithm first determine whether the current input-output unit number for deleting intersection, equally then directly exist
Input and output cross tabulating is updated in second layer three-level CLOS routing algorithm carries out intermediate router-level topology, it is different, it first deletes defeated
Grade routing table out, then judges whether intergrade routing is used multiple times, and does not delete the intergrade road if being used multiple times
By judging whether input stage routing is used multiple times, not deleting input stage routing if being used multiple times.Complete the intersection
Delete operation.
After the triple routing table of three-level CLOS network of first layer has been calculated in routing algorithm, due to input and output grade unit
Numbering identical routing is the intersection completed on same business board in fact, and the routing of same input and output is merged,
When there is the interleaving route of 10GE in the routing table on business board, the channel interleaving route of 10GE is extracted as the second layer
The input of three-level CLOS algorithm network routing, to calculate the triple routing table of the three-level CLOS network on each business board, second
For the framework of the three-level CLOS network of layer as shown in figure 5, input stage has the crossbar switch of 12 4*8, intergrade has 8 12*12's
Crossbar switch, output stage have the crossbar switch of 12 8*4, and input stage output stage and intergrade have and an only connection chain
Road.Three-level CLOS network is traditional three-level CLOS network, and strictly non-blocking, algorithm need to calculate second layer three-level
The routing table that the channel 10GE of CLOS network intersects is intersected according to the cross-over configuration register that configuration FPGA is provided
Configuration.
The routing algorithm logic that the channel of second layer three-level CLOS network intersects is as shown in fig. 6, by same business board
Input and output route the input as algorithm, it is first determined whether the same input established intersects there are output stage duplication
There is a routing access to reach output stage unit, be directly multiplexed the access at this time, only need to establish a routing in output stage
Table is completed this time to create, and then judges whether there is intergrade duplication if there is no output stage duplication, that is, that is established is same
Input, which intersects, has had an access to reach intergrade, is directly multiplexed the access at this time, need to only establish in intergrade and output stage
Routing table is completed this time to create, and replicates if there is no intergrade, then calculates an idle routing access for this friendship
Fork uses, while updating triple routing table, and it is newly-built to complete this.
The calculating that wherein first layer three-level CLOS network routes access of this routing algorithm frame is come real using python language
Show, the complexity of algorithm is realized by the ability of matrix operation and the data processing of the language such as the numpy/pandas of utilization python
The storage and inquiry of logic and data.The routing data of calculating, which provide, obtains interface, calls for C++, second layer three-level CLOS
The calculating of network routing access is realized using C++, is packaged into C++ algorithm functional module class and is carried out tune for Service control process code
With.
Claims (1)
1. a kind of improvement three-level CLOS routing algorithm intersected based on FPGA, which is characterized in that this routing algorithm operation platform is
Bits grades of intersection equipment of large capacity I, including 15 pieces of boards, wherein 12 pieces of boards are business board, 2 pieces of boards are power board, 1 piece of master
Plate is controlled, operation controls scheduler program and the three-level CLOS routing algorithm of this framework in master control borad, is furnished with SOC chip on business board
Zynq7030 and fpga chip, are furnished with cross chips on power board, and the FPGA on each business board has 48*48 input defeated
Crossing out, the crossing be divided into input stage 16*32 cross matrix in the three-level CLOS network architecture of first layer and
The cross matrix of output stage 32*16, intergrade are realized by two pieces of power boards, with the intersection energy of 4 48*48 on every piece of power board
The crossing of power, each 48*48 combines realization by 4 cross chips, because each cross chips have the intersection energy of 12*12
Power, 12 pieces of business boards have divided a part of crossing 16*32 as input stage, a part of crossing 32*16 as output stage,
Intergrade is then made of the unit of 8 48*48, therefore first layer three-level CLOS network architecture input stage has the friendship of 12 16*32
Fork is closed, and intergrade has the crossbar switch of 8 48*48, and output stage has the crossbar switch of 12 32*16, wherein input stage and friendship
Changing each unit of grade has four connecting links, and output stage and each unit of switching stage equally have four connecting links, therefore defeated
Enter each unit of grade 32 output be respectively 4 connecting links and 8 switching stage units product, the 32 of each unit of output stage
A input is also that same calculate is got；
When calculating the triple routing access of input and output 192*192 cross matrix with the three-level CLOS framework that intergrade merges,
The input specified according to user or output unit number which unit of i.e. 12 inputs or output stage, select 16 in each unit
Which channel of a optical-fibre channel, if what is realized is not that channel intersects and needs to realize time-slot cross, user also needs to specify
Which time slot 64 time slots in the channel is needed to carry out intersection switching, optional time slot granularity includes VC-12/VC-4/VC-
16c/VC-64c；
The input and output cross-pair that three-level CLOS routing algorithm is then specified by user calculates input/defeated according to the network architecture
Out/intergrade routing table；
The newly-built crossbar logic implementation process of first layer three-level CLOS routing algorithm needs newly-built intersection column when user gives
Table, what algorithm first determined whether currently to create intersect whether with have the repetition intersected there are output port or time slot, if repeatedly
Then delete original cross-pair, then start to create current cross tabulating, first determine whether input-output unit number whether one
Sample, thinks to intersect on the same business board and carries out if the same, which is directly realized by FPGA, directly calculates the
The routing of two layers of CLOS network, without using the intergrade resource of first layer CLOS network, if number it is different if first determine whether be
No there are output stage duplications, i.e., have had routing to be output to corresponding output unit in the presence of the newly-built input signal of needs and be then multiplexed this
Routing, only in output unit, that creates the routing table of an output stage, updates all routing iinformations；If there is no output
Grade duplication then judges whether there is intergrade duplication, i.e., has had routing to be output to institute with the presence or absence of the newly-built input signal of needs
The intergrade unit of selection, and if so, newly-increased intergrade and output stage routing iinformation, if there is no then judging whether there is
Intergrade multiplexing, i.e., it is unused full with the presence or absence of the routing but its channel that have built up an intergrade, and remaining space can hold
It receives currently built cross time-slot size, exists, update intergrade and input stage routing table, otherwise calculate an idle road
By being supplied to current cross-reference；
The deletion crossbar logic implementation process of first layer three-level CLOS routing algorithm, when user gives the intersection column for needing to delete
Table, whether algorithm first determines whether the current input-output unit number for deleting intersection, equally then directly in second layer three-level
Input and output cross tabulating is updated in CLOS routing algorithm carries out intermediate router-level topology, it is different then first to delete output stage routing
Table, then judges whether intergrade routing is used multiple times, and does not delete intergrade routing if being used multiple times, judges defeated
Enter whether grade routing is used multiple times, do not delete input stage routing if being used multiple times, completes the deletion behaviour of the intersection
Make；
After the triple routing table of three-level CLOS network of first layer has been calculated in routing algorithm, due to input and output grade element number
Identical routing is the intersection completed on same business board in fact, and the routing of same input and output is merged, industry is worked as
When having the interleaving route of 10GE in the routing table on business plate, the channel interleaving route of 10GE is extracted as second layer three-level
The input of CLOS algorithm network routing, to calculate the triple routing table of the three-level CLOS network on each business board, the second layer
The framework of three-level CLOS network, input stage have the crossbar switch of 12 4*8, and intergrade has the crossbar switch of 8 12*12, output
Grade has a crossbar switch of 12 8*4, input stage output stage and intergrade has and an only connecting link, three-level CLOS net
Network is traditional three-level CLOS network, and strictly non-blocking, algorithm need to calculate the 10GE of second layer three-level CLOS network
The routing table that channel intersects carries out cross-over configuration according to the cross-over configuration register that configuration FPGA is provided；
Input and output on same business board are routed and are made by the routing algorithm logic that the channel of second layer three-level CLOS network intersects
For the input of algorithm, it is first determined whether the same input intersection established has had a routing there are output stage duplication
Access reaches output stage unit, is directly multiplexed the access at this time, only need to establish a routing table in output stage and complete that this is new
It builds, then judges whether there is intergrade duplication if there is no output stage duplication, that is, the same input intersection established has had
One access reaches intergrade, is directly multiplexed the access at this time, and only need to establish routing table in intergrade and output stage completes this
It is secondary newly-built, it is replicated if there is no intergrade, then calculates an idle routing access for this cross-reference, update simultaneously
It is newly-built to complete this for triple routing table；
The calculating that wherein first layer three-level CLOS network routes access of this routing algorithm frame is realized using python language, is led to
Cross the complex logic that algorithm is realized using the ability of matrix operation and the data processing of the language such as the numpy/pandas of python
And the storage and inquiry of data；
The routing data of calculating, which provide, obtains interface, calls for C++, and the calculating that second layer three-level CLOS network routes access uses
C++ is realized, is packaged into C++ algorithm functional module class and is carried out calling for Service control process code.
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