CN109326531B - Rewiring structure and method of manufacturing the same, and semiconductor device and method of manufacturing the same - Google Patents

Abstract

This invention provides a redistribution structure and its manufacturing method, as well as a semiconductor device and its manufacturing method. The manufacturing method of the redistribution structure includes: first, forming a first dielectric layer on a substrate having a first pad; then, forming a redistribution metal layer on the top surface of the first pad; finally, forming a second dielectric layer on the redistribution metal layer and the first dielectric layer, the second dielectric layer having multiple openings that expose different locations on the top surface of the redistribution metal layer, each opening exposing the redistribution metal layer at its bottom as a second pad. This increases the number and diversity of pads on the semiconductor device, thereby ensuring that each pad on the semiconductor device has the same clock response, and avoiding the problem of metal layer cracking at the bottom of the pad caused by spot testing and soldering on the same pad.

Description

Rewiring structure and method of manufacturing the same, and semiconductor device and method of manufacturing the same

technical field

The present invention relates to the field of integrated circuit manufacturing, in particular to a rewiring structure and its manufacturing method, and a semiconductor device and its manufacturing method.

Background technique

In the production process of semiconductor integrated circuits, it is usually necessary to use conductive materials such as aluminum (Al) or gold (Au) to form bonding pads (pads) as electrodes for connecting semiconductor devices (chips) with external circuits or using to test check. The general design requirement is that the bonding pads are regularly distributed around the semiconductor device (chip) to ensure that the distance from the center of the semiconductor device (chip) is the same, that is, the clock response is the same. In actual manufacturing, the position of the bonding pad (Pad) will be limited by the position of the copper metal layer below it (including the copper interconnection line Cu line and the copper pad Cu Pad), for example, when part of the copper pad Cu below it When the Pad is located close to the center of the semiconductor device (chip), part of the bonding pad (Pad) is also located close to the center of the semiconductor device (chip). Taking the aluminum pad (Al Pad) as an example, please refer to FIG. 1a and FIG. 1b for details. FIG. 1a is a schematic diagram of the position of the pad on the existing semiconductor device (chip), and FIG. 1b is the existing semiconductor device shown in FIG. 1a Schematic longitudinal cross-section of the pad on the (chip), as can be seen from Figures 1a and 1b, the Cu Pad (M1 in Figure 1b) is connected to the Al Pad (M2 in Figure 1b) and is located below the Al Pad , there is no interconnection line connection between Al Pad and Al Pad, and Cu Pad and Cu Pad are connected through Cu line (for example, interconnect line L1 in FIG. 1a connects Cu Pad P1 and P2). A part of Cu Pads (such as P1 in Figure 1a) are regularly arranged on the periphery of the upper surface of the chip, which will cause a corresponding part of AlPads (such as P3 and P4 in Figure 1a) to be regularly arranged on the periphery of the upper surface of the chip; another part Cu Pad (such as P2 in Figure 1a) is arranged on the upper surface of the chip near the center of the chip, which will cause another part of the corresponding Al Pad (such as P5 in Figure 1a) to be arranged on the upper surface of the chip close to the center of the chip. It can be seen that the position of the Cu pad on the chip defines the position of the AlPad, which leads to the limitation of the position of the AlPad on the chip; at the same time, it can be seen from 1b that the Cu Pad and the AlPad are in one-to-one correspondence. Therefore, the design of existing bond pads, such as Al Pad, leads to the following problems:

1. The same clock response cannot be achieved: To achieve the same clock response, it is necessary to ensure that each bonding pad (such as Al Pad) above the copper metal layer on the chip reaches the main circuit on the chip (the main circuit is in the middle of the chip) The same distance , that is, all bonding pads (eg Al Pad) are required to be regularly arranged on the periphery of the chip. However, the position of the Cupad in the copper metal layer restricts the position of the bonding pad (eg, the Al Pad), which cannot meet the above requirements, thereby making it impossible to achieve the same clock response.

2. Cu Pad cracks (crack): In addition, in the existing chip package structure, only one bonding pad (such as Al Pad) is set on a Cu Pad, and it is necessary to place the bonding pad (such as Al Pad) on the bonding pad (such as Al Pad). Probe and bonding are performed at the same time, so a large compressive stress will be generated, and the compressive stress will easily lead to cracking of the underlying Cu Pad, which in turn leads to a loss of chip yield.

In order to solve the above problems, it is necessary to break the limitation caused by the position of the existing Cu Pad to the position of the bonding pad (such as Al Pad), so as to increase the number of bonding pads (such as Al Pad) connected to the same Cu Pad As well as making the location of bond pads (eg Al Pads) more diverse. Therefore, how to increase the number of bonding pads (such as Al Pads) connected to the same Cu Pad and how to diversify the positions of the bonding pads (such as Al Pads) becomes an urgent problem to be solved.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a rewiring structure and a method for manufacturing the same, a semiconductor device and a method for manufacturing the same, so as to increase the number of pads on the semiconductor device and to diversify the positions thereof, so that each pad on the semiconductor device has The same clock response, and avoids the problem of cracking the metal layer on the bottom of the pad caused by spot testing and soldering on the same pad.

To achieve the above object, the present invention provides a method for manufacturing a rewiring structure, comprising:

providing a substrate with a first pad;

forming a first dielectric layer on the substrate, the first dielectric layer exposing part or all of the top surface of the first pad;

forming a redistribution metal layer on the top surface of the first pad, the redistribution metal layer also extending to a portion of the top surface of the first dielectric layer; and,

A second dielectric layer is formed on the redistribution metal layer and the first dielectric layer, the second dielectric layer has multiple layers exposing the top surface of the redistribution metal layer at different positions, respectively. openings, the redistribution metal layer exposed at the bottom of each opening serves as a second pad, and the redistribution metal layer is in electrical contact with the first pad, so that the second pad and the The first pad is electrically connected.

Optionally, the redistribution metal layer includes interconnect lines connected to the second pads, and the number of the second pads connected to each interconnect line is greater than or equal to two.

Optionally, the step of forming the first dielectric layer includes: first, depositing the first dielectric layer on the substrate, and the deposited first dielectric layer attaches the first dielectric layer to the substrate. A pad is completely buried inside; then, the top surface of the first dielectric layer is planarized by chemical mechanical polishing; finally, the first dielectric layer on the first pad is etched part to expose part or all of the top surface of the first pad.

Optionally, the step of forming the redistribution metal layer includes: first, forming a metal layer on the first pad and the first dielectric layer, and the metal layer connects the first dielectric layer. The material layer and the first pad are completely buried; then, the metal layer is patterned by photolithography and etching to form the redistribution metal layer.

Optionally, the step of forming the second dielectric layer includes: first, depositing a second dielectric layer on the redistribution metal layer and the first dielectric layer; then, etching the Portions of the second dielectric layer located at different positions of the redistribution metal layer form a plurality of openings respectively exposing the top surface of the redistribution metal layer at different positions.

The present invention also provides a rewiring structure, comprising:

a first dielectric layer on a substrate having a first pad, the first dielectric layer exposing part or all of the top surface of the first pad;

a redistribution metal layer on the top surface of the first pad, the redistribution metal layer also extending over a portion of the top surface of the first dielectric layer; and,

A second dielectric layer is located on the redistribution metal layer and the first dielectric layer, the second dielectric layer has multiple layers exposing the top surface of the redistribution metal layer at different positions, respectively. openings, the redistribution metal layer exposed at the bottom of each opening serves as a second pad, and the redistribution metal layer is in electrical contact with the first pad, so that the second pad and the The first pad is electrically connected.

Optionally, the redistribution metal layer includes interconnect lines connected to the second pads, and the number of the second pads connected to each interconnect line is greater than or equal to two.

Optionally, the material of the redistribution metal layer includes any one or more of aluminum, gold, silver, nickel, and titanium; the material of the first dielectric layer and the second dielectric layer It includes any one or more of silicon dioxide, silicon nitride, ethyl orthosilicate, borosilicate glass, phosphosilicate glass, and borophosphosilicate glass.

The present invention also provides a pad structure, comprising: a first pad and the rewiring structure provided by the present invention, the rewiring structure being located on the first pad.

The present invention also provides a semiconductor device, comprising: a substrate having a first pad, a metal interconnection structure, a third dielectric layer, and the rewiring structure provided by the present invention; the third dielectric layer is on the bottom surface of the redistribution structure, and the metal interconnection structure is formed in the third dielectric layer, and the top surface of the metal interconnection structure is in contact with the first bond of the redistribution structure The bottom surface of the pad is in electrical contact; the first pad also extends onto a portion of the top surface of the third dielectric layer.

The present invention also provides a method for manufacturing a semiconductor device, comprising: soldering on a second pad of the rewiring structure provided by the present invention, and simultaneously on another second pad of the rewiring structure Do a spot test.

Compared with the prior art, the technical scheme of the present invention has the following beneficial effects:

1. The manufacturing method of the redistribution structure of the present invention can form a first dielectric layer, a redistribution metal layer and a second dielectric layer in sequence on a substrate with a first pad, thereby forming a The plurality of second pads connected by the first pads increase the number of pads and their positions are more diverse, so that each pad has the same clock response and avoids making dots on the same pad Cracks in the metal layer at the bottom of the pad due to testing and soldering.

2. In the redistribution structure of the present invention, a second pad can be formed through the first dielectric layer, the redistribution metal layer and the second dielectric layer in the redistribution structure, and the second pad is more The number of the original first pads is increased, and the positions are more diverse, so that each pad has the same clock response, and avoids the metal layer at the bottom of the pad caused by spot measurement and welding on the same pad. cracked.

3. The pad structure of the present invention, due to the addition of the rewiring structure of the present invention, can form a plurality of second pads on the original first pad, thereby increasing the number of pads, and at the same time the position of the pads More variety, so that each pad has the same clock response, and the point test and soldering process can be operated separately on the two interconnected pads, avoiding the metal layer at the bottom of the pad caused by working on the same pad cracking problem.

4. In the semiconductor device of the present invention, by adding the rewiring structure of the present invention, a plurality of new second pads are formed on each original first pad in the semiconductor device, thereby enabling spot testing and soldering. The process can be operated separately on different pads connected to each other, avoiding the problem of cracking of the metal layer at the bottom of the pad caused by working on the same pad; and the diversification of the positions of the new pads also makes the semiconductor device. Each pad has the same clock reaction.

5. In the manufacturing method of the semiconductor device of the present invention, by performing soldering on a second pad of the rewiring structure of the present invention, and performing spot measurement on the other second pad of the rewiring structure of the present invention, it is avoided. The problem of cracking of the bottom metal layer caused by spot testing and soldering on the same second pad.

Description of drawings

Fig. 1a is a schematic diagram of the position of the pad on the existing semiconductor device (chip);

Fig. 1b is a schematic longitudinal cross-sectional view of the pad on the conventional semiconductor device (chip) shown in Fig. 1a;

2 is a flowchart of a method for manufacturing a rewiring structure according to an embodiment of the present invention;

3a-3g are schematic diagrams of devices in the manufacturing method of the rewiring structure shown in FIG. 2;

FIG. 4 is a schematic diagram of the positions of pads on a semiconductor device (chip) according to an embodiment of the present invention.

Wherein, the reference numerals in the accompanying drawings 1a to 4 are described as follows:

P1, P2, M1-Cu Pad; P3-P5, M2-Al Pad; P6-P10-Second pad; L1, L2, L3-Interconnect line; 10-Substrate; 11-First pad; 20 - first dielectric layer; 30 - redistribution metal layer; 40 - second dielectric layer; 50 - second pad; T1 - T4 - grooves.

Detailed ways

In order to make the purpose, advantages and features of the present invention clearer, the rewiring structure and its manufacturing method and the semiconductor device and its manufacturing method proposed by the present invention will be further described in detail below with reference to FIGS. 2 to 4 . It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

An embodiment of the present invention provides a method for manufacturing a redistribution structure. Referring to FIG. 2, FIG. 2 is a flowchart of a method for manufacturing a redistribution structure according to an embodiment of the present invention. The method for manufacturing the redistribution structure includes:

Step S2-A, providing a substrate with a first pad, forming a first dielectric layer on the substrate, the first dielectric layer exposing part or all of the first pad the top surface;

Step S2-B, forming a redistribution metal layer on the top surface of the first pad, and the redistribution metal layer also extends to a part of the top surface of the first dielectric layer;

Step S2-C, forming a second dielectric layer on the redistribution metal layer and the first dielectric layer, the second dielectric layer having different positions exposing the redistribution metal layer respectively A plurality of openings on the top surface of the opening, the redistribution metal layer exposed at the bottom of each opening acts as a second pad, and the redistribution metal layer is in electrical contact with the first pad, so that the second pad The pad is electrically connected to the first pad.

The manufacturing method of the rewiring structure provided in this embodiment will be described in more detail below with reference to FIGS. 3 a to 3 g . FIGS. 3 a to 3 g are schematic diagrams of devices in the manufacturing method of the rewiring structure shown in FIG. 2 .

First, referring to FIGS. 3 a to 3 c , according to step S2-A, a substrate 10 having a first pad 11 is provided, and a first dielectric layer 20 is formed on the substrate 10 . The first dielectric The material layer 20 exposes a part or all of the top surface of the first pad 11 . As can be seen from FIG. 3 a , the first pad 11 may be partially located in the substrate 10 and partially located on the top surface of the substrate 10 , and all the pads located on the top surface of the substrate 10 There may be a groove T1 in the first pad 11 . In addition, the top surface of the first pad 11 may also be a plane or a convex arc-shaped surface. As can be seen from FIG. 3b and FIG. 3c, when the groove T1 exists in the first pad 11, the step of forming the first dielectric layer 20 includes: first, depositing the first dielectric The dielectric layer 20 is on the substrate 10, and the deposited first dielectric layer 20 completely buries the first pad 11 (as shown in FIG. 3b); The top surface of the first dielectric layer 20 is planarized; finally, the portion of the first dielectric layer 20 located on the first pad 11 is etched, so that the portion of the first pad 11 is etched. or the entire top surface is exposed (Fig. 3c). In addition, the substrate 10 may further include other metal layers and dielectric layers, such as copper (Cu) metal layers and tetraethyl orthosilicate (TEOS) dielectric layers.

Then, referring to FIG. 3d and FIG. 3e, according to step S2-B, a redistribution metal layer 30 is formed on the top surface of the first pad 11, and the redistribution metal layer 30 also extends to the first dielectric on a portion of the top surface of the substratum 20 . As can be seen from FIG. 3d and FIG. 3e, the steps of forming the redistribution metal layer 30 include: first, forming a metal layer on the first pad 11 and the first dielectric layer 20, so The metal layer completely buries the first dielectric layer 20 and the first pad 11, and the method for forming the metal layer may be sputter deposition; then, the metal layer is formed by photolithography and etching. The metal layer is patterned to form the redistribution metal layer 30 . Since the first dielectric layer 20 formed in step S2-A exposes part or all of the top surface of the first pad 11, the A groove T2 will be formed on the top surface of the first pad 11 . Then, when the metal layer is formed on the top surface of the first pad 11 and the top surface of the first dielectric layer 20 , the thickness of the metal layer on the first pad 11 may be the same as the thickness of the metal layer on the top surface of the first dielectric layer 20 , so that above the first pad 11 A groove T3 is formed in the metal layer of the Another groove or grooves, such as groove T4 in FIG. 3e, are etched on the metal layer on a part of the top surface. Alternatively, by extending the deposition time on the first pad 11 , the top surface of the first pad 11 and the top surface of the first dielectric layer 20 can be The metal layer is flush, that is, a plane is formed, and then two or more grooves are simultaneously formed in the metal layer by means of photolithography and etching. In addition, in order to ensure that the formed grooves can be connected and conducted, the redistribution metal layer 30 also includes interconnect lines, such as interconnect lines L2 and L3 in FIG. 4 .

Finally, referring to FIG. 3f and FIG. 3g, according to step S2-C, a second dielectric layer 40 is formed on the redistribution metal layer 30 and the first dielectric layer 20. The second dielectric layer 40 is formed on the redistribution metal layer 30 and the first dielectric layer 20. The layer 40 has a plurality of openings respectively exposing the top surface of the redistribution metal layer 30 at different positions, and the redistribution metal layer 30 exposed at the bottom of each opening serves as a second pad 50. The layer 30 is in electrical contact with the first pad 11 so that the second pad 50 is electrically connected with the first pad 11 . As can be seen from FIG. 3f and FIG. 3g, the steps of forming the second dielectric layer 40 include: first, depositing a second dielectric layer 40 on the redistribution metal layer 30 and the first dielectric layer Then, the parts of the second dielectric layer 40 located at different positions of the redistribution metal layer 30 are etched to form the top surface respectively exposing the different positions of the redistribution metal layer 30 of multiple openings. The redistribution metal layer 30 includes interconnect lines connecting the second pads 50 , and the number of the second pads 50 connected to each interconnect line is greater than or equal to two. The second pad 50 is in direct electrical contact with the first pad 11 , or the interconnection wire is in direct electrical contact with the first pad 11 , so that the second pad 50 is in direct electrical contact with the first pad 11 . The first pad 11 is electrically connected, so that the connection between the second pad 50 and the first pad 11 is conducted. Since the second dielectric layer 40 is mainly used to protect the redistribution metal layer 30 , the sidewalls of the groove of the redistribution metal layer 30 where the second pad 50 is located are A certain thickness of the second dielectric layer 40 will still remain thereon.

Referring to FIG. 4, FIG. 4 is a schematic diagram of the position of the pad on the semiconductor device (chip) according to an embodiment of the present invention. As can be seen from FIG. 4, it is different from the Al Pad shown in FIG. The second pad 50 connected to the first pad 11) P3 is P6, and P6 is connected to P7 and P8 through the interconnection line L2; The second pad 50 connected to the first pad 11) P5 is P9, and P9 is connected to P10 through an interconnection line L3. When it is necessary to spot test and solder the pads on the semiconductor device (chip), if the design of the pads of the semiconductor device (chip) shown in Figure 1a is adopted, both spot measurement and soldering should be performed on P3. , the larger compressive stress may cause cracking of the Cu Pad M1 shown in Figure 1b; however, if the design of the pad on the semiconductor device (chip) shown in Figure 4 is used, a spot test can be made on P6, Do soldering on P7 or P8; you can do soldering on P9 and spot measurement on P10, so that the compressive stress on each pad is less, so as to avoid cracking of the Cu Pad M1. In addition, due to the connection between P9 and P10, the P9 located near the center of the semiconductor device (chip) can also be obtained through P10 located at the periphery of the semiconductor device (chip) and other solders located at the periphery of the semiconductor device (chip). the same clock reaction as the disc.

To sum up, the method for manufacturing a redistribution structure provided by the present invention includes: forming a first dielectric layer on a substrate having a first pad, the first dielectric layer exposing the first Part or all of the top surface of a pad; a redistribution metal layer is formed on the top surface of the first pad, and the redistribution metal layer also extends to part of the top surface of the first dielectric layer and, forming a second dielectric layer on the redistribution metal layer and the first dielectric layer, the second dielectric layer having tops respectively exposing different positions of the redistribution metal layer A plurality of openings on the surface, the redistribution metal layer exposed at the bottom of each opening serves as a second pad, and the redistribution metal layer is in electrical contact with the first pad, so that the second pad is is electrically connected to the first pad. Through the manufacturing method of the rewiring structure provided by the present invention, the number of the pads is increased and the positions are more diverse, so that the pads on the semiconductor device (chip) can have the same clock response and avoid being on the same pad. Cracks in the metal layer at the bottom of the pad caused by spot testing and soldering.

An embodiment of the present invention provides a redistribution structure. Referring to FIG. 3g, it can be seen from FIG. 3g that the redistribution structure includes: a first dielectric layer 20, a redistribution metal layer 30, and a second dielectric Layer 40. The first dielectric layer 20 is located on a substrate 10 having a first pad 11 , and the first dielectric layer 20 exposes a part or all of the top surface of the first pad 11 ; The redistribution metal layer 30 is located on the top surface of the first pad 11, and the redistribution metal layer 30 also extends to a part of the top surface of the first dielectric layer 20; and, the first Two dielectric layers 40 are located on the redistribution metal layer 30 and the first dielectric layer 20 , and the second dielectric layer 40 has tops respectively exposing different positions of the redistribution metal layer 30 A plurality of openings on the surface, the redistribution metal layer 30 exposed at the bottom of each opening serves as a second pad 50, and the redistribution metal layer 30 is in electrical contact with the first pad 11, so that the The second pad 50 is electrically connected to the first pad 11 .

The following describes the rewiring structure provided by this embodiment in more detail with reference to FIG. 3g:

(例如为

等)，位于所述衬底10上的所述第一介电质层20的厚度可以为

(例如为

等)。The first dielectric layer 20 is located on a substrate 10 having a first pad 11 , and the first dielectric layer 20 exposes part or all of the top surface of the first pad 11 . The first pad 11 may be partially located in the substrate 10 and the other part may be located on the top surface of the substrate 10, and the first pad 11 located on the top surface of the substrate 10 may be There is a groove T1. In addition, the top surface of the first pad 11 may also be a plane or a convex arc-shaped surface. The material of the first dielectric layer 20 may include silicon dioxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), tetraethyl orthosilicate (TEOS), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), the thickness of the first dielectric layer 20 on the top surface of the first pad 11 may be

(e.g. for

etc.), the thickness of the first dielectric layer 20 on the substrate 10 may be

(e.g. for

Wait).

(例如为

等)；The redistribution metal layer 30 is located on the top surface of the first pad 11 , and the redistribution metal layer 30 also extends to part of the top surface of the first dielectric layer 20 . The redistribution metal layer 30 further includes interconnect lines connecting the second pads 50 , and the number of the second pads 50 connected to each interconnect line is greater than or equal to two. The material of the redistribution metal layer 30 may include any one or more of aluminum (Al), gold (Au), silver (Ag), nickel (Ni), and titanium (Ti). 30 thickness can be

(e.g. for

Wait);

(例如为

等)。The second dielectric layer 40 is located on the redistribution metal layer 30 and the first dielectric layer 20 , and the second dielectric layer 40 has different exposures of the redistribution metal layer 30 A plurality of openings on the top surface of the position, the redistribution metal layer 30 exposed at the bottom of each opening serves as a second pad 50, and the redistribution metal layer 30 is in electrical contact with the first pad 11 to The second pad 50 is electrically connected to the first pad 11 . The redistribution metal layer 30 also includes interconnect lines connecting the second pads 50, and the number of the second pads 50 connected to each interconnect line is greater than or equal to 2, that is, to each of the first pads. The number of the second pads 50 that are connected and turned on is greater than or equal to 2. The material of the second dielectric layer 40 may include silicon dioxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), tetraethyl orthosilicate (TEOS), borosilicate glass (BSG), phosphosilicate glass Any one or more of (PSG) and borophosphosilicate glass (BPSG), the thickness of the second dielectric layer 40 on the first dielectric layer 20 may be

(e.g. for

Wait).

To sum up, the rewiring structure provided by the present invention includes a first dielectric layer on a substrate having a first pad, the first dielectric layer exposing the first pad part or all of the top surface; a redistribution metal layer on the top surface of the first pad, the redistribution metal layer also extending over part of the top surface of the first dielectric layer; and, on the redistribution metal layer and the second dielectric layer on the first dielectric layer, the second dielectric layer has a plurality of top surfaces respectively exposing different positions of the redistribution metal layer openings, the redistribution metal layer exposed at the bottom of each opening serves as a second pad, and the redistribution metal layer is in electrical contact with the first pad, so that the second pad is connected to the first pad. A pad is electrically connected. The rewiring structure provided by the present invention can form more than or equal to 2 new pads on each original pad, so that the number of pads is increased, and the positions of the pads are also more diversified, thereby making the semiconductor device (chip ) on the pads can have the same clock response, and avoid the cracking of the metal layer at the bottom of the pad caused by spot testing and soldering on the same pad.

An embodiment of the present invention provides a pad structure, the pad structure includes: a first pad and the rewiring structure provided by the present invention, and the rewiring structure is located on the first pad. By adopting the rewiring structure, second pads are formed on the first pads, and the number of the interconnected second pads formed on each of the first pads is greater than or equal to 2, The connected second pads may be located on the periphery of the semiconductor device (chip) at the same time, or partially located on the periphery of the semiconductor device (chip), and the other part is located near the center of the semiconductor device (chip), so as to achieve each solder joint. The disks have the same clock response, and the connected second pads can be partly used for spot testing and the other part used for soldering, avoiding the first spot testing and soldering on the same pad. The problem of cracking of the pad or the metal layer under the first pad.

An embodiment of the present invention provides a semiconductor device, the semiconductor device comprising: a substrate having a first pad, a metal interconnection structure, a third dielectric layer, and the rewiring structure provided by the present invention. The third dielectric layer is on the bottom surface of the redistribution structure, and the metal interconnect structure is formed in the third dielectric layer, and the top surface of the metal interconnect structure is in contact with the The bottom surface of the first pad of the redistribution structure is in electrical contact; the first pad also extends onto a portion of the top surface of the third dielectric layer. The material of the metal interconnect structure may include any one or more of copper (Cu), aluminum (Al), and cobalt (Co), and the material of the third dielectric layer may include silicon dioxide (SiO2). ₂ ), any one or more of tetraethyl orthosilicate (TEOS), borosilicate glass (BSG), phosphosilicate glass (PSG), and borophosphosilicate glass (BPSG). By adopting the rewiring structure, second pads are formed on the first pads, the second pads are connected to each other by interconnecting wires, and the second pads connected to each interconnecting wire are The number is greater than or equal to 2, so that soldering can be performed on a second pad of the re-wiring structure, and spot measurement can be performed on another second pad of the re-wiring structure at the same time, avoiding the same The problem of cracking of the first pad or the metal interconnection structure caused by spot testing and welding on the two pads; and the position of the second pad is more diverse, which makes the soldering on the semiconductor device more diverse. The discs have the same clock response.

An embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: performing soldering on a second pad of the redistribution structure provided by the present invention, and simultaneously on another second pad of the redistribution structure Doing spot testing on the above avoids the problem of cracking of the bottom metal layer caused by spot testing and welding on the same second pad.

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure all belong to the protection scope of the claims.

Claims (11)

1. a manufacturing method of rewiring structure, is characterized in that, comprises: providing a substrate with a first pad; forming a first dielectric layer on the substrate, the first dielectric layer exposing part or all of the top surface of the first pad; forming a redistribution metal layer on the top surface of the first pad, the redistribution metal layer also extending to a portion of the top surface of the first dielectric layer; and, A second dielectric layer is formed on the redistribution metal layer and the first dielectric layer, the second dielectric layer has multiple layers exposing the top surface of the redistribution metal layer at different positions, respectively. openings, the redistribution metal layer exposed at the bottom of each opening serves as a second pad, and the redistribution metal layer is in electrical contact with the first pad, so that the second pad and the a first pad is electrically connected; and, among the plurality of second pads electrically connected to each of the first pads, at least one of the second pads is located at the periphery of the semiconductor device and is located in the semiconductor device All the second pads on the periphery of the device are at the same distance from the center of the semiconductor device, and each of the second pads located near the center of the semiconductor device passes through the redistribution metal layer The interconnect lines in the semiconductor device are connected to the corresponding second pads located on the periphery of the semiconductor device, so that all the second pads have the same clock response, and the center position of the semiconductor device is formed with The main circuit of the semiconductor device. 2 . The method for manufacturing a redistribution structure according to claim 1 , wherein the number of the second pads connected to each interconnection line in the redistribution metal layer is greater than or equal to 2. 3 . 3. The method for manufacturing a rewiring structure as claimed in claim 1, wherein the step of forming the first dielectric layer comprises: first, depositing the first dielectric layer on the substrate , and the deposited first dielectric layer completely buries the first pad; then, the top surface of the first dielectric layer is planarized by chemical mechanical polishing; finally, the A portion of the first dielectric layer on the first pad is used to expose part or all of the top surface of the first pad. 4. The method for manufacturing a redistribution structure according to claim 1 or 2, wherein the step of forming the redistribution metal layer comprises: first, forming a metal layer on the first pad and the first pad On a dielectric layer, the metal layer completely buries the first dielectric layer and the first pad; then, the metal layer is patterned by photolithography and etching to form the redistribution metal layer. 5 . The method for manufacturing a redistribution structure according to claim 1 , wherein the step of forming the second dielectric layer comprises: first, depositing a second dielectric layer on the redistribution metal layer and the redistribution metal layer. 6 . on the first dielectric layer; then, etching the parts of the second dielectric layer located at different positions of the redistribution metal layer to form parts that expose different positions of the redistribution metal layer respectively Multiple openings in the top surface. 6. A rewiring structure, characterized in that, comprising: a first dielectric layer on a substrate having a first pad, the first dielectric layer exposing part or all of the top surface of the first pad; a redistribution metal layer on the top surface of the first pad, the redistribution metal layer also extending over a portion of the top surface of the first dielectric layer; and, A second dielectric layer is located on the redistribution metal layer and the first dielectric layer, the second dielectric layer has multiple layers exposing the top surface of the redistribution metal layer at different positions, respectively. openings, the redistribution metal layer exposed at the bottom of each opening serves as a second pad, and the redistribution metal layer is in electrical contact with the first pad, so that the second pad and the a first pad is electrically connected; and, among the plurality of second pads electrically connected to each of the first pads, at least one of the second pads is located at the periphery of the semiconductor device and is located in the semiconductor device All the second pads on the periphery of the device are at the same distance from the center of the semiconductor device, and each of the second pads located near the center of the semiconductor device passes through the redistribution metal layer The interconnect lines in the semiconductor device are connected to the corresponding second pads located on the periphery of the semiconductor device, so that all the second pads have the same clock response, and the center position of the semiconductor device is formed with The main circuit of the semiconductor device. 7 . The redistribution structure of claim 6 , wherein the number of the second pads connected to each interconnection line in the redistribution metal layer is greater than or equal to 2. 8 . 8. The redistribution structure according to claim 6 or 7, wherein the material of the redistribution metal layer comprises any one or more of aluminum, gold, silver, nickel, and titanium; The materials of a dielectric layer and the second dielectric layer include any one or more of silicon dioxide, silicon nitride, ethyl orthosilicate, borosilicate glass, phosphosilicate glass, and borophosphosilicate glass kind. 9 . A pad structure, comprising: a first pad and the rewiring structure according to any one of claims 6 to 8 , the rewiring structure being located on the first pad. 10 . 10. A semiconductor device, comprising: a substrate having a first pad, a metal interconnection structure, a third dielectric layer, and the rewiring structure according to any one of claims 6 to 8; The third dielectric layer is on the bottom surface of the redistribution structure, and the metal interconnect structure is formed in the third dielectric layer, and the top surface of the metal interconnect structure is in contact with the The bottom surface of the first pad of the redistribution structure is in electrical contact; the first pad also extends onto a portion of the top surface of the third dielectric layer. 11. A method of manufacturing a semiconductor device according to claim 10, comprising: soldering on a second pad of the redistribution structure, and at the same time soldering on another second pad of the redistribution structure Make a spot test on the pad.

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