CN109324828B - Method for realizing flash memory multi-command parallel execution in verification platform - Google Patents
Method for realizing flash memory multi-command parallel execution in verification platform Download PDFInfo
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- CN109324828B CN109324828B CN201811108370.1A CN201811108370A CN109324828B CN 109324828 B CN109324828 B CN 109324828B CN 201811108370 A CN201811108370 A CN 201811108370A CN 109324828 B CN109324828 B CN 109324828B
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- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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Abstract
The invention discloses a method for realizing the parallel execution of flash memory multiple commands in a verification platform, which simulates a flash memory device on the verification platform, wherein each LUN corresponds to a command execution thread, the main thread analyzes the commands and executes the data return of immediate commands, thereby realizing the parallel execution of the commands on different storage hierarchies on TARGET and LUN. The number of parameterized TARGET and LUN, i.e. the number of parameterized generation command execution threads, is convenient to be transplanted to verification platforms with different flash memory storage structures. Different commands correspond to different command execution processes, so that the transplanting and multiplexing of command operations are facilitated.
Description
Technical Field
The invention relates to a method for realizing flash memory multi-command parallel execution in a verification platform, belonging to the technical field of memories.
Background
When operating a real flash memory device, the flash memory (NAND FLASH) often needs to execute multiple commands in parallel, and the multiple commands executed in parallel do not affect each other, i.e. the first command is executed while the second command can be received and executed, so that the parallel execution of the first command and the second command is realized. According to the storage structure characteristics of the flash memory, the flash memory has three parallel command execution modes: parallel execution of commands between different TARGETs, parallel execution of commands between different LUNs of the same TARGET, and parallel execution of commands on the same LUNs of the same TARGET. The existing verification platform realizes flash memory multi-command parallel execution by using a parallel model (a model written in a non-object-oriented language), has the defects of complex signal function in the model, unfavorable model modification, new characteristic addition, model transplanting and the like, limits the use scene of the model, and cannot be simply and conveniently applied to the verification platform with different characteristic requirements.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a method for realizing the parallel execution of flash memory multi-command in an authentication platform, so as to realize the parallel execution of commands among different TARGETs, among different LUNs of the same TARGET and on the same LUN of the same TARGET.
In order to solve the technical problems, the invention adopts the following technical scheme: a method for implementing flash memory multi-command parallel execution in an authentication platform, comprising the steps of: s01), the verification platform generates a command execution thread for each LUN on each TARGET, each TARGET and each LUN are marked by unique marks, the command execution thread is in a waiting command triggering state, the verification platform main thread is in a waiting command input state, and the main thread and each command execution thread execute in parallel; s02), after the main thread of the verification platform receives the command, the main thread sends the command to a command analyzer for analysis, and the command to be executed, the TARGET for executing the command and the LUN number are analyzed; s03), if the command is an instant command, the command parser executes the command operation and puts output data into a data register for output, the main thread returns to a state of waiting for command input, and the command execution thread is not triggered; s04), if the command is a command with delay, the command parser triggers a corresponding command execution thread with a TARGET and a LUN number, and simultaneously outputs the command to the command execution thread, the main thread returns to a waiting command input state, the command execution thread receives event trigger, and the subsequent operation of the command is executed; s05), if the main thread receives a new command request during execution of a command execution thread of a TARGET or LUN, repeating steps S02, S03, and S04.
Further, before executing the method, a flash memory architecture is first established on the verification platform, wherein the flash memory architecture comprises a plurality of TARGET, a command parser and a data register, each TARGET comprises a plurality of LUNs, the command parser parses an input command and transmits the input command to the LUNs of the corresponding TARGET, and the data register registers and outputs data after command parsing.
Further, the method is applied to an object-oriented language-based verification platform.
The invention has the beneficial effects that: the method is simple and clear for realizing the parallel operation of the flash memory multi-command in the verification platform, the flash memory device is simulated on the verification platform, each LUN corresponds to a command execution thread, the main thread analyzes the command and executes the data return of the immediate command, and the parallel execution of the commands on different storage hierarchies on the TARGET and the LUN is realized. The number of parameterized TARGET and LUN, i.e. the number of parameterized generation command execution threads, is convenient to be transplanted to verification platforms with different flash memory storage structures. Different commands correspond to different command execution processes, so that the transplanting and multiplexing of command operations are facilitated.
Compared with the method for realizing the flash memory model by using a parallel model (a model written in a non-object-oriented language) in the verification platform, the method has the advantages that functional modules are mutually independent, model modification, new characteristic addition and model transplanting on different verification platforms are facilitated, and the method can be better applied to the verification platforms with different characteristic requirements.
Drawings
FIG. 1 is a schematic diagram of a memory structure of a flash memory device;
FIG. 2 is a schematic diagram of a flash model architecture in a verification platform;
FIG. 3 is a schematic diagram of a main thread execution process;
FIG. 4 is a schematic diagram of the execution of a command execution thread.
Detailed Description
The invention will be further described with reference to the drawings and the specific examples.
As shown in FIG. 1, a schematic storage structure of a flash memory device includes a plurality of TARGET, each TARGET includes a plurality of LUNs, a command is input into the flash memory, and after address resolution, data read-write operations are performed from the TARGET and the LUNs of the corresponding addresses. According to the storage structure of the flash memory, there are three parallel command execution modes, namely, parallel commands are executed among different TARGETs, parallel commands are executed on different LUNs of the same TARGET, and parallel commands are executed on the same LUNs of the same TARGET. According to the characteristics of the flash memory command, the flash memory command can be divided into an instant command and a command with delay, the flash memory immediately returns the requested data to complete the command operation after receiving the instant command, the flash memory is required to consume a certain time for completing the operation after receiving the command with delay, and a state signal on a flash memory interface is used for identifying whether the current command is completed. When commands are executed in parallel between different TARGET or on different LUNs of the same TARGET, the parallel execution command may be any command, and when commands are executed in parallel on the same LUN of the same TARGET, if the previous input command is a delayed command, the next command must be an immediate command.
The method is provided according to the characteristics of the flash memory.
The method for implementing flash memory multi-command parallel execution in the verification platform according to the embodiment comprises the following steps: s01), a flash memory architecture is built on the verification platform, as shown in fig. 2, where the flash memory architecture includes multiple TARGET, a command parser and a data register, each TARGET includes multiple LUNs, the command parser parses an input command and transmits the command to a LUN of a corresponding TARGET, and the data register registers and outputs data after command parsing.
S02), the verification platform generates a command execution thread for each LUN on each TARGET, each TARGET and each LUN are marked by unique marks, the command execution thread is in a waiting command triggering state, the verification platform main thread is in a waiting command input state, and the main thread and each command execution thread execute in parallel;
s03), after the main thread of the verification platform receives the command, the main thread sends the command to a command analyzer for analysis, and the command to be executed, the TARGET for executing the command and the LUN number are analyzed;
s04), if the command is an instant command, the command parser executes the command operation and puts output data into a data register for output, the main thread returns to a state of waiting for command input, and the command execution thread is not triggered;
s05), if the command is a command with delay, the command parser triggers a corresponding command execution thread with a TARGET and a LUN number, and simultaneously outputs the command to the command execution thread, the main thread returns to a state of waiting for command input, and the command execution thread receives event trigger and executes subsequent operation of the command;
s06), if the main thread receives a new command request during execution of a command execution thread of a TARGET or LUN, repeating steps S03, S04, and S05.
As shown in fig. 3, which is a schematic diagram of a main thread execution process, fig. 4 is an execution process of a command execution thread, where each LUN corresponds to a command execution thread, and the command execution thread executes in parallel with the main thread.
The method in this embodiment is simple and clear for implementing flash memory multi-command parallel operation in the verification platform, simulates a flash memory device on the verification platform, each LUN corresponds to a command execution thread, the main thread parses the command and executes the data return of the immediate command, and implements the parallel execution of commands on different storage hierarchies on the TARGET and the LUN. The number of parameterized TARGET and LUN, i.e. the number of parameterized generation command execution threads, is convenient to be transplanted to verification platforms with different flash memory storage structures. Different commands correspond to different command execution processes, so that the commands are convenient to transplant and multiplex.
Compared with the method for realizing the flash memory model by using a parallel model (a model written in a non-object-oriented language) in the verification platform, the method has the advantages that functional modules are mutually independent, model modification, new characteristic addition and model transplanting on different verification platforms are facilitated, and the method can be better applied to the verification platforms with different characteristic requirements.
The foregoing description is only of the basic principles and preferred embodiments of the present invention, and modifications and alternatives thereto will occur to those skilled in the art to which the present invention pertains, as defined by the appended claims.
Claims (2)
1. A method for realizing flash memory multi-command parallel execution in an authentication platform is characterized in that: the method comprises the following steps:
s01), firstly, establishing a flash memory architecture on a verification platform, wherein the flash memory architecture comprises a plurality of TARGET, a command parser and a data register, each TARGET comprises a plurality of LUNs, the command parser parses an input command and transmits the input command to the LUNs of the corresponding TARGET, and the data register registers and outputs data after command parsing; s02), the verification platform generates a command execution thread for each LUN on each TARGET, each TARGET and each LUN are marked by unique marks, the command execution thread is in a waiting command triggering state, the verification platform main thread is in a waiting command input state, and the main thread and each command execution thread execute in parallel; s03), after the main thread of the verification platform receives the command, the main thread sends the command to a command analyzer for analysis, and the command to be executed, the TARGET for executing the command and the LUN number are analyzed; s04), if the command is an instant command, the command parser executes the command operation and puts output data into a data register for output, the main thread returns to a state of waiting for command input, and the command execution thread is not triggered; s05), if the command is a command with delay, the command parser triggers a corresponding command execution thread with a TARGET and a LUN number, and simultaneously outputs the command to the command execution thread, the main thread returns to a state of waiting for command input, and the command execution thread receives event trigger and executes subsequent operation of the command; s06), if the main thread receives a new command request during execution of a command execution thread of a TARGET or LUN, repeating steps S03, S04, and S05.
2. The method for implementing flash multi-command parallel execution in an authentication platform according to claim 1, wherein: the method is applied to an object-oriented language-based verification platform.
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| JP4048382B1 (en) * | 2006-09-01 | 2008-02-20 | 富士ゼロックス株式会社 | Information processing system and program |
| US9268608B2 (en) * | 2009-02-26 | 2016-02-23 | Oracle International Corporation | Automatic administration of UNIX commands |
| CN102012791B (en) * | 2010-10-15 | 2013-06-19 | 中国人民解放军国防科学技术大学 | Flash based PCIE (peripheral component interface express) board for data storage |
| US8819328B2 (en) * | 2010-12-30 | 2014-08-26 | Sandisk Technologies Inc. | Controller and method for performing background operations |
| RU2454739C1 (en) * | 2011-01-12 | 2012-06-27 | Российская Федерация, от имени которой выступает Министерство обороны Российской Федерации | Method of programming nand flash memory ic and apparatus for realising said method |
| US10216625B2 (en) * | 2012-09-24 | 2019-02-26 | Sk Hynix Memory Solutions Inc. | Hardware integrity verification |
| US9934194B2 (en) * | 2013-12-20 | 2018-04-03 | Rambus Inc. | Memory packet, data structure and hierarchy within a memory appliance for accessing memory |
| US20170046102A1 (en) * | 2015-08-14 | 2017-02-16 | Marvell World Trade Ltd. | Flexible interface for nand flash memory |
| CN105788636A (en) * | 2016-04-05 | 2016-07-20 | 山东华芯半导体有限公司 | EMMC controller based on parallel multichannel structure |
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| CN1613120A (en) * | 2002-01-04 | 2005-05-04 | 英特尔公司 | Flash memory access using a plurality of command cycles |
| CN102890477A (en) * | 2012-09-26 | 2013-01-23 | 西安交通大学 | On-line active dynamic balance measurement and control device and on-line active dynamic balance measurement and control method |
| WO2016039774A1 (en) * | 2014-09-12 | 2016-03-17 | Intel Corporation | Facilitating dynamic parallel scheduling of command packets at graphics processing units on computing devices |
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