CN109302275B - Data output method and device - Google Patents
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Abstract
The invention provides a data output method and device. The method comprises the following steps: receiving a data stream to be recovered; under the condition that the frequency of the data stream is lower than or equal to the target frequency, oversampling is carried out on the received data stream to obtain oversampled data; performing edge detection on the oversampled data to obtain an edge detection result, wherein the edge detection result is used for indicating edge data bits in the data stream; determining target data of the data stream according to the edge detection result; under the condition that the frequency of the data stream is higher than the target frequency, sampling the received data stream to obtain sampling data; determining the sampling data as target data; and performing alignment output on the target data. The invention solves the problem of lower data recovery efficiency of the receiver of the SerDes in the related technology, thereby achieving the effect of improving the data recovery efficiency of the receiver of the SerDes.
Description
Technical Field
The invention relates to the field of data processing, in particular to a data output method and device.
Background
Since SerDes (seralizer-Deserializer) does not transmit clock signals, the receiving end integrates CDR (clock Data recovery) circuits for correctly recovering the Data information transmitted by analog signals, and the CDR can extract the clock from the edge information of the Data to find the optimal sampling boundary. However, the analog CDR cannot achieve wideband locking, i.e. it is difficult to perform high quality data recovery on low frequency data streams once analog operation at higher frequencies is required. How to accurately recover high-frequency and low-frequency analog signals simultaneously for a SerDes receiver becomes an urgent problem to be solved.
In view of the above problems, no effective solution has been proposed.
Disclosure of Invention
Embodiments of the present invention provide a data output method and apparatus, so as to at least solve the problem in the related art that a SerDes receiver has low data recovery efficiency.
According to an embodiment of the present invention, there is provided a data output method including: receiving a data stream to be recovered; under the condition that the frequency of the data stream is lower than or equal to a target frequency, oversampling is carried out on the received data stream to obtain oversampled data; performing edge detection on the oversampled data to obtain an edge detection result, wherein the edge detection result is used for indicating edge data bits in the data stream; determining target data of the data stream according to the edge detection result, wherein the target data is data sent by a sending end of the data stream; under the condition that the frequency of the data stream is higher than a target frequency, sampling the received data stream to obtain sampling data; determining the sampling data as target data, wherein the target data is data sent by a sending end of the data stream; and performing alignment output on the target data.
Optionally, oversampling the received data stream to obtain the oversampled data includes: acquiring an input frequency of the data stream; determining a target frequency which is N times of the input frequency as an oversampling frequency corresponding to the data stream, wherein N is a positive integer greater than 2; and sampling the data stream by adopting the clock with the oversampling frequency to obtain the oversampling data.
Optionally, performing edge detection on the oversampled data, and obtaining the edge detection result includes: dividing N continuous data in the over-sampling data into a phase block, wherein each phase block comprises data of N phases; performing exclusive-or operation on the data of each adjacent phase in the over-sampled data to obtain exclusive-or data; determining the sum of the XOR data on the corresponding phase in each phase block to obtain the phase and the phase sum with corresponding relation; and determining the phase corresponding to the maximum value in the phase sum as the boundary data bit of the data stream.
Optionally, determining the target data of the data stream according to the edge detection result includes: determining a target data bit in the data stream according to the boundary data bit; determining data in the target data stream located in the target data bits as the target data.
Optionally, determining the target data bit in the data stream according to the boundary data bit includes: determining a shift value according to the boundary data bits and N, wherein the shift value is used for indicating the phase number of the target data bit shifted relative to the boundary data bits; and determining the target data bit according to the shift value.
Optionally, determining the target data of the data stream according to the edge detection result includes: carrying out error code judgment on the edge detection result; under the condition that the error code exists in the edge detection result, correcting the edge detection result to obtain a correction result; determining the target data of the data stream according to the correction result; and under the condition that the edge detection result is judged to have no error code, determining the target data of the data stream according to the edge detection result.
According to another embodiment of the present invention, there is provided an output apparatus of data including: the receiving module is used for receiving the data stream to be recovered; the first determining module is used for performing oversampling on the received data stream to obtain oversampled data under the condition that the frequency of the data stream is lower than or equal to a target frequency; performing edge detection on the oversampled data to obtain an edge detection result, wherein the edge detection result is used for indicating edge data bits in the data stream; determining target data of the data stream according to the edge detection result, wherein the target data is data sent by a sending end of the data stream; the second determining module is used for sampling the received data stream to obtain sampling data under the condition that the frequency of the data stream is higher than the target frequency; determining the sampling data as target data, wherein the target data is data sent by a sending end of the data stream; and the output module is used for aligning and outputting the target data.
Optionally, the first determining module includes: an acquisition unit configured to acquire an input frequency of the data stream; a first determining unit, configured to determine a target frequency that is N times the input frequency as an oversampling frequency corresponding to the data stream, where N is a positive integer greater than 2; and the sampling unit is used for sampling the data stream by adopting the clock with the oversampling frequency to obtain the oversampling data.
According to a further embodiment of the present invention, there is also provided a storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the above method embodiments when executed.
According to yet another embodiment of the present invention, there is also provided an electronic device, including a memory in which a computer program is stored and a processor configured to execute the computer program to perform the steps in any of the above method embodiments.
By the invention, if the received data stream is a low-frequency data stream, the received low-frequency data stream is sampled by adopting an oversampling mode, then the edge detection is carried out on the sampled oversampled data, the edge data bit in the data stream is detected, the target data is determined according to the edge detection result, if the data stream is a high-frequency data stream, the data stream is directly sampled, and the sampled data is determined as the target data, so that the data sent by a sending end is recovered and output, the data recovery process can be suitable for both high-frequency data and low-frequency data, the high-quality data recovery can be carried out on the low-frequency data stream even if the receiver works at a higher frequency, and the high-frequency and low-frequency analog signals can be accurately recovered at the same time. Therefore, the problem of low data recovery efficiency of the SerDes receiver in the related art can be solved, and the effect of improving the data recovery efficiency of the SerDes receiver is achieved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
fig. 1 is a block diagram of a hardware configuration of a mobile terminal of a data output method according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method of outputting data according to an embodiment of the present invention;
FIG. 3 is a block diagram I of an output device for data according to an embodiment of the present invention;
FIG. 4 is a block diagram II of the structure of an output device of data according to an embodiment of the present invention;
FIG. 5 is a block diagram III of the structure of an output device of data according to an embodiment of the present invention;
fig. 6 is a block diagram of the structure of an output device of data according to an embodiment of the present invention;
fig. 7 is a block diagram of a fifth configuration of an output device of data according to an embodiment of the present invention.
Detailed Description
The invention will be described in detail hereinafter with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
Example 1
The method provided by the first embodiment of the present application may be executed in a mobile terminal, a computer terminal, or a similar computing device. Taking the example of the present invention running on a mobile terminal, fig. 1 is a block diagram of a hardware structure of the mobile terminal of a data output method according to an embodiment of the present invention. As shown in fig. 1, the mobile terminal 10 may include one or more (only one shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, and optionally may also include a transmission device 106 for communication functions and an input-output device 108. It will be understood by those skilled in the art that the structure shown in fig. 1 is only an illustration, and does not limit the structure of the mobile terminal. For example, the mobile terminal 10 may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
The memory 104 may be used to store computer programs, for example, software programs and modules of application software, such as computer programs corresponding to the data output method in the embodiment of the present invention, and the processor 102 executes various functional applications and data processing by running the computer programs stored in the memory 104, so as to implement the above-mentioned method. The memory 104 may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory located remotely from the processor 102, which may be connected to the mobile terminal 10 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 106 is used for receiving or transmitting data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the mobile terminal 10. In one example, the transmission device 106 includes a Network adapter (NIC), which can be connected to other Network devices through a base station so as to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is used for communicating with the internet in a wireless manner.
In the present embodiment, a data output method is provided, and fig. 2 is a flowchart of the data output method according to the embodiment of the present invention, as shown in fig. 2, the flowchart includes the following steps:
step S202, receiving a data stream to be recovered;
step S204, under the condition that the frequency of the data stream is lower than or equal to the target frequency, oversampling is carried out on the received data stream to obtain oversampled data; performing edge detection on the oversampled data to obtain an edge detection result, wherein the edge detection result is used for indicating edge data bits in the data stream; determining target data of the data stream according to the edge detection result, wherein the target data is data sent by a sending end of the data stream;
step S206, under the condition that the frequency of the data stream is higher than the target frequency, sampling the received data stream to obtain sampling data; determining the sampling data as target data, wherein the target data is data sent by a sending end of a data stream;
and step S208, aligning and outputting the target data.
Alternatively, the above-described data output method may be applied, but not limited, to a receiving end of SerDes data transmission, where a receiver of SerDes data transmits the received data to a controller, and the controller recovers the received data. The controller may be, but is not limited to, embedded in the receiver as a functional module, or may be a device separately connected to the receiver.
Alternatively, in the present embodiment, the frequency of oversampling may be, but is not limited to, an integer multiple of the frequency of the received data stream. For example: 3 times, 5 times, 7 times, etc.
Optionally, in this embodiment, if the received data stream is a high-speed data stream, the sampled data may be directly output as recovered data.
Alternatively, in the present embodiment, the clock of the oversampling process may be, but is not limited to, generated by a Voltage Controlled Oscillator (VCO) circuit.
Through the steps, if the received data stream is a low-frequency data stream, the received low-frequency data stream is sampled in an oversampling mode, edge detection is carried out on the sampled oversampling data, an edge data bit in the data stream is detected, target data is determined according to the edge detection result, if the data stream is a high-frequency data stream, the data stream is directly sampled, and the sampled data is determined to be the target data, so that the data sent by a sending end is recovered and output, the data recovery process can be suitable for both high-frequency data and low-frequency data, high-quality data recovery can be carried out on the low-frequency data stream even if the data stream works at a higher frequency, and a SerDes receiver can accurately recover high-frequency and low-frequency analog signals at the same time. Therefore, the problem of low data recovery efficiency of the SerDes receiver in the related art can be solved, and the effect of improving the data recovery efficiency of the SerDes receiver is achieved.
Alternatively, the frequency of the oversampling clock may be determined according to the frequency of the received data stream. For example: in the step S204, the input frequency of the data stream is obtained; determining a target frequency which is N times of an input frequency as an oversampling frequency corresponding to a data stream, wherein N is a positive integer greater than 2; and sampling the data stream by adopting a clock with an oversampling frequency to obtain oversampling data.
Alternatively, the received data stream may be stored in divided phase blocks, each phase block operating as a window to determine edge data bits in the data stream, each phase block may include, but is not limited to, a predetermined amount of data, such as: 150 bits, 200 bits, etc. For example: in the step S204, N consecutive data in the oversampled data are divided into one phase block, where each phase block includes data of N phases; performing exclusive-or operation on the data of each adjacent phase in the over-sampled data to obtain exclusive-or data; determining the sum of the XOR data on the corresponding phase in each phase block to obtain the phase and the phase sum with corresponding relation; and determining the phase corresponding to the maximum value in the phase sum as the boundary data bit of the data stream.
Alternatively, in the step S204, the target data bit in the data stream may be determined according to the boundary data bit; and determining the data positioned in the target data bit in the target data stream as the target data.
Alternatively, in this embodiment, the target data bit in the data stream may be determined by: determining a shift value according to the boundary data bits and N, wherein the shift value is used for indicating the phase number of the target data bits shifted relative to the boundary data bits; the target data bit is determined from the shift value.
For example: edge detection can be performed on a window (e.g., 150bit, 200bit, etc.) of n-bit data bit streams, and the detected boundary phase number plus the oversampling multiple X divided by 2 plus 1 phase value is output as an effective data bit.
Optionally, after the edge detection, the error code determination may be performed on the edge detection result, and the edge detection result is correspondingly processed according to the error code determination result, so as to improve the accuracy of data recovery. For example: in the step S204, performing error code determination on the edge detection result; under the condition that the error code exists in the edge detection result, correcting the edge detection result to obtain a correction result; determining the target data of the data stream according to the correction result; and under the condition that the edge detection result is judged to have no error code, determining the target data of the data stream according to the edge detection result.
Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.
In this embodiment, a data output device is further provided, and the data output device is used to implement the foregoing embodiments and preferred embodiments, and the description of the data output device is omitted for brevity. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.
Fig. 3 is a block diagram showing a structure of an apparatus for outputting data according to an embodiment of the present invention, as shown in fig. 3, the apparatus including:
a receiving module 32, configured to receive a data stream to be recovered;
a first determining module 34, configured to perform oversampling on the received data stream to obtain oversampled data when the frequency of the data stream is lower than or equal to the target frequency; performing edge detection on the oversampled data to obtain an edge detection result, wherein the edge detection result is used for indicating edge data bits in the data stream; determining target data of the data stream according to the edge detection result, wherein the target data is data sent by a sending end of the data stream;
a second determining module 36, configured to sample the received data stream to obtain sampled data when the frequency of the data stream is higher than the target frequency; determining the sampling data as target data, wherein the target data is data sent by a sending end of a data stream;
and an output module 38, configured to perform aligned output on the target data.
Alternatively, the above-mentioned output means of data may be applied, but not limited, to a receiving end of SerDes data transmission, and a receiver of SerDes data transmits the received data to a controller, and the controller recovers the received data. The controller may be, but is not limited to, embedded in the receiver as a functional module, or may be a device separately connected to the receiver.
Alternatively, in the present embodiment, the frequency of oversampling may be, but is not limited to, an integer multiple of the frequency of the received data stream. For example: 3 times, 5 times, 7 times, etc.
Optionally, in this embodiment, if the received data stream is a high-speed data stream, the sampled data may be directly output as recovered data.
Alternatively, in the present embodiment, the clock of the oversampling process may be, but is not limited to, generated by a Voltage Controlled Oscillator (VCO) circuit.
By the device, if the received data stream is a low-frequency data stream, the received low-frequency data stream is sampled in an oversampling mode, edge detection is carried out on the sampled oversampling data, an edge data bit in the data stream is detected, target data is determined according to the edge detection result, if the data stream is a high-frequency data stream, the data stream is directly sampled, and the sampled data is determined to be the target data, so that the data sent by a sending end is recovered and output, the data recovery process can be suitable for both high-frequency data and low-frequency data, high-quality data recovery can be carried out on the low-frequency data stream even if the data stream works at a higher frequency, and a SerDes receiver can accurately recover high-frequency and low-frequency analog signals at the same time. Therefore, the problem of low data recovery efficiency of the SerDes receiver in the related art can be solved, and the effect of improving the data recovery efficiency of the SerDes receiver is achieved.
Fig. 4 is a block diagram of a second structure of the data output apparatus according to the embodiment of the present invention, as shown in fig. 4, optionally, the first determining module 34 includes:
a receiving unit 42, configured to receive a data stream and obtain an input frequency of the data stream;
a first determining unit 44, configured to determine a target frequency that is N times an input frequency as an oversampling frequency corresponding to a data stream, where N is a positive integer greater than 2;
and the sampling unit 46 is configured to sample the data stream by using a clock with an oversampling frequency to obtain oversampled data.
Alternatively, the frequency of the oversampling clock may be determined according to the frequency of the received data stream.
Fig. 5 is a block diagram of a third structure of the data output apparatus according to the embodiment of the present invention, as shown in fig. 5, optionally, the first determining module 34 includes:
a dividing unit 52, configured to divide consecutive N data in the oversampled data into one phase block, where each phase block includes data of N phases;
an arithmetic unit 54, configured to perform an exclusive or operation on data of each adjacent phase in the oversampled data to obtain exclusive or data;
a second determining unit 56, configured to determine a sum of the xor data on corresponding phases in each phase block, so as to obtain a phase and a phase sum having a corresponding relationship;
a third determining unit 58, configured to determine a phase corresponding to the largest value in the phase sum as a boundary data bit of the data stream.
Alternatively, the received data stream may be stored in divided phase blocks, each phase block operating as a window to determine edge data bits in the data stream, each phase block may include, but is not limited to, a predetermined amount of data, such as: 150 bits, 200 bits, etc.
Fig. 6 is a block diagram of a fourth structure of the data output apparatus according to the embodiment of the present invention, as shown in fig. 6, optionally, the first determining module 34 includes:
a fourth determining unit 62 for determining a target data bit in the data stream according to the boundary data bit;
and a fifth determining unit 64 for determining data located at the target data bit in the target data stream as the target data.
Optionally, the fourth determining unit includes: a first determining subunit, configured to determine a shift value according to the boundary data bits and N, wherein the shift value is used to indicate a phase number by which the target data bit is shifted with respect to the boundary data bits; and a second determining subunit, configured to determine the target data bit according to the shift value.
For example: edge detection can be performed on a window (e.g., 150bit, 200bit, etc.) of n-bit data bit streams, and the detected boundary phase number plus the oversampling multiple X divided by 2 plus 1 phase value is output as an effective data bit.
Fig. 7 is a block diagram of a fifth structure of the data output apparatus according to the embodiment of the present invention, as shown in fig. 7, optionally, the first determining module 34 includes:
a judging unit 72, configured to perform error code judgment on the edge detection result;
the first processing unit 74 is configured to correct the edge detection result to obtain a corrected result when it is determined that the edge detection result has an error code; determining the target data of the data stream according to the correction result;
and a second processing unit 76, configured to determine target data of the data stream according to the edge detection result when it is determined that the edge detection result does not have an error code.
Optionally, after the edge detection, the error code determination may be performed on the edge detection result, and the edge detection result is correspondingly processed according to the error code determination result, so as to improve the accuracy of data recovery.
It should be noted that, the above modules may be implemented by software or hardware, and for the latter, the following may be implemented, but not limited to: the modules are all positioned in the same processor; alternatively, the modules are respectively located in different processors in any combination.
Reference will now be made in detail to the alternative embodiments of the present invention.
Usually, the cdr (clock Data recovery) uses a feedback circuit to perform edge detection and alignment on the bit stream of the input Data by using the receiving end clock, so as to recover the Data. For SerDes data transmission, it is possible to transmit high-bandwidth, i.e. high-frequency data streams, and there is a requirement for transmitting low-bandwidth data streams, and it is difficult for the VCO circuit at the receiving end to simultaneously achieve wideband locking of high-frequency and low-frequency data. An alternative embodiment of the present invention provides a data transmission method, which performs oversampling on a data bit stream by a high-frequency local clock and then performs an accurate data acquisition operation on the oversampled data by digital algorithm logic to recover a data stream actually transmitted by a SerDes in a CDR system. The data receiving error rate caused by jitter introduced by low-frequency locking of the VCO of the CDR can be effectively avoided.
Optionally, in this embodiment, the process includes the following steps:
step 1, a VCO generates a clock which is higher than the input frequency X (such as 3 times, 5 times, 7 times and the like) of an analog signal to perform oversampling of a data bit stream;
step 2, performing phase-divided (phase) block storage on the over-sampled data;
step 3, edge detection is carried out on n-bit data bit streams of a window (such as 150bit, 200bit and the like);
step 4, adding the oversampling multiple X to the detected boundary phase number and dividing the phase by 2 plus 1 to be used as an effective data bit for outputting;
step 5, carrying out error code judgment of adding a phase and subtracting the phase on the boundary of window switching;
and 6, aligning and outputting the selected data bit streams through the elastic FIFO.
Embodiments of the present invention also provide a storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the above method embodiments when executed.
Alternatively, in the present embodiment, the storage medium may be configured to store a computer program for executing the steps of:
s1, receiving a data stream to be recovered;
s2, under the condition that the frequency of the data stream is lower than or equal to the target frequency, oversampling the received data stream to obtain oversampled data; performing edge detection on the oversampled data to obtain an edge detection result, wherein the edge detection result is used for indicating edge data bits in the data stream; determining target data of the data stream according to the edge detection result, wherein the target data is data sent by a sending end of the data stream;
s3, under the condition that the frequency of the data stream is higher than the target frequency, sampling the received data stream to obtain sampling data; determining the sampling data as target data, wherein the target data is data sent by a sending end of a data stream;
and S4, aligning and outputting the target data.
Optionally, in this embodiment, the storage medium may include, but is not limited to: various media capable of storing computer programs, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.
Embodiments of the present invention also provide an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the steps of any of the above method embodiments.
Optionally, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.
Optionally, in this embodiment, the processor may be configured to execute the following steps by a computer program:
s1, receiving a data stream to be recovered;
s2, under the condition that the frequency of the data stream is lower than or equal to the target frequency, oversampling the received data stream to obtain oversampled data; performing edge detection on the oversampled data to obtain an edge detection result, wherein the edge detection result is used for indicating edge data bits in the data stream; determining target data of the data stream according to the edge detection result, wherein the target data is data sent by a sending end of the data stream;
s3, under the condition that the frequency of the data stream is higher than the target frequency, sampling the received data stream to obtain sampling data; determining the sampling data as target data, wherein the target data is data sent by a sending end of a data stream;
and S4, aligning and outputting the target data.
Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments and optional implementation manners, and this embodiment is not described herein again.
It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method for outputting data, comprising:
receiving a data stream to be recovered;
under the condition that the frequency of the data stream is lower than or equal to a target frequency, oversampling is carried out on the received data stream to obtain oversampled data; performing edge detection on the oversampled data to obtain an edge detection result, wherein the edge detection result is used for indicating edge data bits in the data stream; determining target data of the data stream according to the edge detection result, wherein the target data is data sent by a sending end of the data stream;
under the condition that the frequency of the data stream is higher than a target frequency, sampling the received data stream to obtain sampling data; determining the sampling data as target data, wherein the target data is data sent by a sending end of the data stream;
and performing alignment output on the target data.
2. The method of claim 1, wherein oversampling the received data stream to obtain the oversampled data comprises:
acquiring an input frequency of the data stream;
determining a target frequency which is N times of the input frequency as an oversampling frequency corresponding to the data stream, wherein N is a positive integer greater than 2;
and sampling the data stream by adopting the clock with the oversampling frequency to obtain the oversampling data.
3. The method of claim 2, wherein performing edge detection on the oversampled data to obtain the edge detection result comprises:
dividing N continuous data in the over-sampling data into a phase block, wherein each phase block comprises data of N phases;
performing exclusive-or operation on the data of each adjacent phase in the over-sampled data to obtain exclusive-or data;
determining the sum of the XOR data on the corresponding phase in each phase block to obtain the phase and the phase sum with corresponding relation;
and determining the phase corresponding to the maximum value in the phase sum as the boundary data bit of the data stream.
4. The method of claim 3, wherein determining the target data of the data stream according to the edge detection result comprises:
determining a target data bit in the data stream according to the boundary data bit;
determining data in the target data stream located in the target data bits as the target data.
5. The method of claim 4, wherein determining the target data bit in the data stream according to the boundary data bit comprises:
determining a shift value according to the boundary data bits and N, wherein the shift value is used for indicating the phase number of the target data bit shifted relative to the boundary data bits;
and determining the target data bit according to the shift value.
6. The method of claim 1, wherein determining the target data of the data stream according to the edge detection result comprises:
carrying out error code judgment on the edge detection result;
under the condition that the error code exists in the edge detection result, correcting the edge detection result to obtain a correction result; determining the target data of the data stream according to the correction result;
and under the condition that the edge detection result is judged to have no error code, determining the target data of the data stream according to the edge detection result.
7. An apparatus for outputting data, comprising:
the receiving module is used for receiving the data stream to be recovered;
the first determining module is used for performing oversampling on the received data stream to obtain oversampled data under the condition that the frequency of the data stream is lower than or equal to a target frequency; performing edge detection on the oversampled data to obtain an edge detection result, wherein the edge detection result is used for indicating edge data bits in the data stream; determining target data of the data stream according to the edge detection result, wherein the target data is data sent by a sending end of the data stream;
the second determining module is used for sampling the received data stream to obtain sampling data under the condition that the frequency of the data stream is higher than the target frequency; determining the sampling data as target data, wherein the target data is data sent by a sending end of the data stream;
and the output module is used for aligning and outputting the target data.
8. The apparatus of claim 7, wherein the first determining module comprises:
an acquisition unit configured to acquire an input frequency of the data stream;
a first determining unit, configured to determine a target frequency that is N times the input frequency as an oversampling frequency corresponding to the data stream, where N is a positive integer greater than 2;
and the sampling unit is used for sampling the data stream by adopting the clock with the oversampling frequency to obtain the oversampling data.
9. A computer-readable storage medium, in which a computer program is stored, wherein the computer program is arranged to perform the method of any of claims 1 to 6 when executed.
10. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and wherein the processor is arranged to execute the computer program to perform the method of any of claims 1 to 6.
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