CN109300982A - High frequency triode and method of making the same - Google Patents
High frequency triode and method of making the same Download PDFInfo
- Publication number
- CN109300982A CN109300982A CN201811119427.8A CN201811119427A CN109300982A CN 109300982 A CN109300982 A CN 109300982A CN 201811119427 A CN201811119427 A CN 201811119427A CN 109300982 A CN109300982 A CN 109300982A
- Authority
- CN
- China
- Prior art keywords
- polysilicon
- layer
- emitter
- conduction type
- impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 197
- 229920005591 polysilicon Polymers 0.000 claims abstract description 196
- 229910052751 metal Inorganic materials 0.000 claims abstract description 121
- 239000002184 metal Substances 0.000 claims abstract description 121
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 76
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 239000012535 impurity Substances 0.000 claims description 67
- 238000000034 method Methods 0.000 claims description 40
- 238000005530 etching Methods 0.000 claims description 36
- 230000008569 process Effects 0.000 claims description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 238000000137 annealing Methods 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 11
- 238000009792 diffusion process Methods 0.000 claims description 10
- 230000026267 regulation of growth Effects 0.000 claims description 9
- 238000007669 thermal treatment Methods 0.000 claims description 6
- 230000035515 penetration Effects 0.000 claims description 5
- 238000011049 filling Methods 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 abstract description 2
- 230000010354 integration Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 293
- 229920002120 photoresistant polymer Polymers 0.000 description 19
- 238000002347 injection Methods 0.000 description 10
- 239000007924 injection Substances 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 10
- 239000000126 substance Substances 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 229910052698 phosphorus Inorganic materials 0.000 description 8
- 239000011574 phosphorus Substances 0.000 description 8
- 229910021341 titanium silicide Inorganic materials 0.000 description 8
- 238000001039 wet etching Methods 0.000 description 8
- 239000000203 mixture Substances 0.000 description 7
- 239000000243 solution Substances 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 238000000407 epitaxy Methods 0.000 description 5
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052731 fluorine Inorganic materials 0.000 description 4
- 239000011737 fluorine Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 229910052787 antimony Inorganic materials 0.000 description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 3
- WEAMLHXSIBDPGN-UHFFFAOYSA-N (4-hydroxy-3-methylphenyl) thiocyanate Chemical compound CC1=CC(SC#N)=CC=C1O WEAMLHXSIBDPGN-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-AKLPVKDBSA-N silicon-31 atom Chemical compound [31Si] XUIMIQQOPSSXEZ-AKLPVKDBSA-N 0.000 description 2
- -1 titanium silicide Chemical compound 0.000 description 2
- 229910021355 zirconium silicide Inorganic materials 0.000 description 2
- 229910015900 BF3 Inorganic materials 0.000 description 1
- 108090000723 Insulin-Like Growth Factor I Proteins 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 102000013275 Somatomedins Human genes 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006735 deficit Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000003682 fluorination reaction Methods 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000007521 mechanical polishing technique Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D10/00—Bipolar junction transistors [BJT]
- H10D10/311—Thin-film BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D10/00—Bipolar junction transistors [BJT]
- H10D10/01—Manufacture or treatment
- H10D10/041—Manufacture or treatment of thin-film BJTs
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
本发明公开了一种高频三极管及其制作方法。所述制作方法获得的高频三极管包括衬底，位于所述衬底的上表面的外延层，所述外延层内形成有外基区和基区，所述基区内还形成有发射区；位于所述外延层的上表面的多晶硅岛，所述多晶硅岛包括第一基极多晶硅；位于所述外延层的上表面的介质层，所述介质层内形成有贯穿所述介质层的发射极接触孔，所述发射极接触孔内填充有发射极多晶硅，所述发射极多晶硅的上表面覆盖有第二金属硅化物层；位于所述介质层的上表面的基极和发射极；位于所述衬底的下表面的集电极。本发明所述高频三极管结构不仅具有超高的工作频率，而且具有更低的器件制作成本，更高的集成度，更强的电流能力。
The invention discloses a high-frequency triode and a manufacturing method thereof. The high-frequency triode obtained by the manufacturing method includes a substrate, an epitaxial layer located on the upper surface of the substrate, an outer base region and a base region are formed in the epitaxial layer, and an emission region is also formed in the base region; a polysilicon island located on the upper surface of the epitaxial layer, the polysilicon island comprising a first base polysilicon; a dielectric layer located on the upper surface of the epitaxial layer, the dielectric layer is formed with an emitter penetrating the dielectric layer contact holes, the emitter contact holes are filled with emitter polysilicon, the upper surface of the emitter polysilicon is covered with a second metal silicide layer; the base and the emitter are located on the upper surface of the dielectric layer; collector of the lower surface of the substrate. The high-frequency triode structure of the present invention not only has an ultra-high operating frequency, but also has lower device fabrication costs, higher integration, and stronger current capability.
Description
Technical field
The present invention relates to technical field of semiconductors, especially a kind of high-frequency triode and preparation method thereof.
Background technique
High-frequency triode be different from common triode feature be mainly its transistor feature size is small, breakdown potential is forced down,
Characteristic frequency is high, and manufacture craft difficulty is big.Generally, the high-frequency triode is applied in very high frequency(VHF) (Very High
Frequency, VHF), superfrequency (Ultra High Frequency, UHF), cable television network (Community Antenna
Television, CATV), wireless remote control, on the high-frequency widebands low-noise amplifier such as radio-frequency module, these use occasions are mostly used
Under low-voltage, small signal, low current, low noise conditions.
Referring to Fig. 1, conventional highfrequency triode include P type substrate 1 ', the 1 ' upper surface of substrate at N-type extension
Layer 2 ', forms in the epitaxial layer 2 ' and extends to the buried layer N+ type buried layer 3 ' formed in the substrate 1 '
Collector phosphorus bridge 4 ' in 3 ' through the epitaxial layer 2 ' and buried layer 3 ' and extends to two isolating trenches in the substrate 1 '
Slot 5 ', the epitaxial layer 2 ' surface formed base area 6 ', in the outer base area 7 ' of the 6 ' two sides of base area, in the base area 6 '
Surface emitter region 8 ', the 2 ' surface of epitaxial layer field oxide 9 ', the 2 ' surface of epitaxial layer and connection described in
The first side wall 10 ' and the second side wall 11 ' of base area 6 ', in the 2 ' surface of epitaxial layer and the emitter of the connection emitter region 8 '
Polysilicon 12 ', in the base polysilicon 13 ' of the 2 ' surface of epitaxial layer and the connection outer base area 7 ', the connection emitter
The emitter 14 ' of polysilicon 12 ', the base stage 15 ' for connecting the base polysilicon 13 ', the collection for connecting the collector phosphorus bridge 4 '
Electrode 16 '.
Conventional highfrequency audion is complex, during making the conventional highfrequency triode, not only needs
The field oxide 9 ' is made in order to form the outer base area 7 ', while also being needed using the double-deck isolation side walls etching technics shape
At first side wall 10 ' and second side wall 11 ', and in order to reduce collector resistance, it is also necessary to use buried layer technique system
Make the buried layer 3 ' of the connection collector phosphorus bridge 4 ', it is big so as to cause manufacture craft difficulty and at high cost.In addition,
The collector of conventional highfrequency triode, emitter, the spacing between base stage are larger, and structure is not compact enough, and integrated level is not high, electric current
Ability is on the weak side.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of compact-sized, lower high-frequency triodes of manufacture difficulty.
In order to solve the above technical problems, the present invention adopts the following technical solutions: the high-frequency triode, comprising:
The substrate of first conduction type；
Positioned at the epitaxial layer of the first conduction type of the upper surface of the substrate, the second conduction is formed in the epitaxial layer
The outer base area of type and connect the outer base area the second conduction type base area, the second conduction type is miscellaneous in the outer base area
The doping concentration of matter is higher than the doping concentration of the impurity of the second conduction type in the base area；First is also formed in the base area
The emitter region of conduction type；
Polysilicon island positioned at the upper surface of the epitaxial layer, the polysilicon island include connecting and mixing with the outer base area
First base polysilicon of the impurity of miscellaneous second conduction type；
Positioned at the epitaxial layer upper surface and thickness be greater than or equal to the polysilicon island height dielectric layer, it is described
The contact hole of the dielectric layer is formed through in dielectric layer, the contact hole includes the emitter contact of the corresponding emitter region
Hole, the emitter-polysilicon of the interior impurity filled with the first conduction type of doping of the emitter contact hole, the emitter are more
The upper surface of crystal silicon is covered with the second metal silicide layer；
Base stage and emitter positioned at the upper surface of the dielectric layer, the base stage is connect with the polysilicon island, described
Emitter is connect with the emitter-polysilicon；
Collector positioned at the lower surface of the substrate.
In addition, the present invention also provides the production methods of high-frequency triode claimed comprising following steps:
S01: the substrate of the first conduction type, and the extension of one conduction type of upper surface growth regulation in the substrate are provided
Layer；
S02: in one polysilicon layer of upper surface growth regulation of the epitaxial layer；
S03: the impurity for injecting the second conduction type to first polysilicon layer and the shape in first polysilicon layer
At polysilicon doped regions；
S04: partial penetration etching is carried out to first polysilicon layer and is formed positioned at the upper surface of the epitaxial layer
Polysilicon island；
S05: high-temperature heat treatment makes the impurity of the second conduction type in the polysilicon doped regions in first polycrystalline
The first base polysilicon of the impurity of the second conduction type of doping is spread and converted first polysilicon layer in silicon layer, together
The impurity diffusion of the second conduction type of Shi Suoshu is into the epitaxial layer and forms the second conductive-type being located in the epitaxial layer
The outer base area of type；
S06: locally adulterating the impurity of the second conduction type to the epitaxial layer, is formed and is located in the epitaxial layer and connects
The base area of second conduction type of the outer base area, the doping concentration of the impurity of the second conduction type is lower than described in the base area
The doping concentration of the impurity of second conduction type in outer base area；
S07: it is greater than or equal to the dielectric layer of the height of the polysilicon island in the upper surface growth thickness of the epitaxial layer；
S08: it etches the dielectric layer and forms the emitter contact hole for running through the dielectric layer, the emitter contact hole
The corresponding base area；
S09: the polysilicon of the first conductive type impurity of filling doping high concentration in the emitter contact hole, and shape
At the emitter-polysilicon being located in the emitter contact hole；
S10: the first metal layer is grown in the upper surface of the dielectric layer；
S11: the second metal silicide layer is formed in the upper surface of the emitter-polysilicon using rapid thermal treatment, and same
When formed be located at the base area in the first conduction type emitter region；
S12: the upper surface of the dielectric layer formed the base stage that is connect with the polysilicon island and with the emitter it is more
The emitter of crystal silicon connection；
S13: collector is grown in the lower surface of the substrate.
Compared with prior art, the present invention has following the utility model has the advantages that high-frequency triode structure of the present invention not only has
There is the working frequency of superelevation, and there is lower element manufacturing cost, higher integrated level, stronger current capacity.It compares
More traditional high-frequency triode, that eliminates buried layer techniques, eliminate the extremely complex double-deck isolation side walls etching technics of technique,
Field oxide is eliminated, device architecture is more compact to also eliminate the groove isolation construction of two sides, to have lower manufacture
Difficulty, lower production cost.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is the schematic diagram of the section structure of conventional highfrequency triode；
Fig. 2 is the schematic diagram of the section structure for the high-frequency triode that one embodiment of the invention provides；
Fig. 3 is the flow diagram of the production method for the high-frequency triode that one embodiment of the invention provides；
Fig. 4 to Figure 18 is the schematic diagram of the section structure of the forming process for the high-frequency triode that one embodiment of the invention provides.
Description of symbols:
3 ': buried layer；4 ': collector phosphorus bridge；5 ': isolated groove；9 ': field oxide；10 ': the first isolation side walls；11 ': the
Two isolation side walls；13 ': base polysilicon；1 ', 10: substrate；2 ', 20: epitaxial layer；7 ', 21: outer base area；6 ', 22: base area；8',
23: emitter region；30: polysilicon island；30a: the first polysilicon layer；30b: the first metal oxide layer；30c: polysilicon doped regions；
31: the first base polysilicons；40: dielectric layer；41: contact hole；411: emitter contact hole；412: base stage contact hole；42: the second
Polysilicon layer；12 ', 421: emitter-polysilicon；422: the second base polysilicons；43: the first metal layer；431: the second metallic silicons
Compound layer；432: third metal silicide layer；50: second metal layer；15 ', 51: base stage；14 ', 52: emitter；16 ', 53: collection
Electrode.
Specific embodiment
Present invention is generally directed to traditional high-frequency triode structures, and problem complex, that manufacture difficulty is high provides a kind of solution
Certainly scheme.
It is clear in order to be more clear the purpose of the present invention, technical solution and advantageous effects, below in conjunction with this hair
Attached drawing in bright embodiment, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described
Embodiment is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field
Those of ordinary skill's every other embodiment obtained without making creative work, belongs to protection of the present invention
Range.
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, or be somebody's turn to do
Invention product using when the orientation or positional relationship usually put, be merely for convenience of description of the present invention and simplification of the description, without
It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore not
It can be interpreted as limitation of the present invention.In addition, term " first ", " second ", " third " etc. are only used for distinguishing description, and cannot manage
Solution is indication or suggestion relative importance.
Referring to Fig. 2, a kind of high-frequency triode comprising:
The substrate 10 of first conduction type；
Positioned at the epitaxial layer 20 of the first conduction type of the upper surface of the substrate 10, is formed in the epitaxial layer 20
The outer base areas 21 of two conduction types and connect the outer base area 21 the second conduction type base area 22, the in the outer base area 21
The doping concentration of the impurity of two conduction types is higher than the doping concentration of the impurity of the second conduction type in the base area 22；The base
The emitter region 23 of the first conduction type is also formed in area 22；
Polysilicon island 30 positioned at the upper surface of the epitaxial layer 20, the polysilicon island 30 include and the outer base area 21
First base polysilicon 31 of the impurity of connection and the second conduction type of doping；
Positioned at the epitaxial layer 20 upper surface and thickness be greater than or equal to the polysilicon island 30 height dielectric layer
40, the contact hole 41 of the dielectric layer 40 is formed through in the dielectric layer 40, the contact hole 41 includes the corresponding hair
The emitter contact hole 411 in area 23 is penetrated, the hair of the impurity filled with the first conduction type of doping in the emitter contact hole 411
Emitter polysilicon 421, the upper surface of the emitter-polysilicon 421 are covered with the second metal silicide layer 431；
Base stage 51 and emitter 52 positioned at the upper surface of the dielectric layer 40, the base stage 51 and the polysilicon island 30
Connection, the emitter 52 are connect with the emitter-polysilicon 421；
Collector 53 positioned at the lower surface of the substrate 10.
In high-frequency triode of the present invention, the emitter-polysilicon 421 can reduce the surface recombination of emitter region 23
Speed increases current gain, can also form an ultra shallow emitter junction, promotes triode frequency；Under the outer base area 21 and emitter junction
The base area 22 of side connects, and reduces base resistance；It is compared to traditional high-frequency triode, high-frequency triode of the present invention
Collector 53 directly from the back side of the substrate 10 draw, eliminate buried layer and phosphorus bridge technique, save process costs and core
Piece area；Field oxide is eliminated in high-frequency triode of the present invention, and connects the first base stage polycrystalline of the outer base area 21
Silicon 31 it is smaller, the integrated level of the high-frequency triode is higher, and the current capacity of device is stronger under unit area.
Referring to Fig. 3, a kind of production method of high-frequency triode comprising following steps:
S01: the substrate 10 of the first conduction type is provided, and in one conduction type of upper surface growth regulation of the substrate 10
Epitaxial layer 20；
S02: in the one polysilicon layer 30a of upper surface growth regulation of the epitaxial layer 20；
S03: the impurity of the second conduction type is injected to the first polysilicon layer 30a and in first polysilicon layer
Polysilicon doped regions 30c is formed in 30a；
S04: carrying out partial penetration etching to the first polysilicon layer 30a and forms the upper table positioned at the epitaxial layer 20
The polysilicon island 30 in face；
S05: high-temperature heat treatment makes the impurity of the second conduction type in the polysilicon doped regions 30c described first
The first base of the impurity of the second conduction type of doping is spread and converted the first polysilicon layer 30a in polysilicon layer 30a
Pole polysilicon 31, while the impurity diffusion of second conduction type into the epitaxial layer 20 and is formed positioned at the epitaxial layer
The outer base area 21 of the second conduction type in 20；
S06: to the impurity of 20 the second conduction type of part doping of the epitaxial layer, formed be located in the epitaxial layer 20 and
The base area 22 of the second conduction type of the outer base area 21 is connected, the doping of the impurity of second conduction type is dense in the base area 22
Doping concentration of the degree lower than the impurity of the second conduction type in the outer base area 21；
S07: it is greater than or equal to Jie of the height of the polysilicon island 30 in the upper surface growth thickness of the epitaxial layer 20
Matter layer 40；
S08: it etches the dielectric layer 40 and forms the emitter contact hole 411 for running through the dielectric layer 40, the transmitting
The corresponding base area 22 of pole contact hole 411；
S09: the polysilicon of first conductive type impurity of filling doping high concentration in the emitter contact hole 411,
And form the emitter-polysilicon 421 being located in the emitter contact hole；
S10: the first metal layer 43 is grown in the upper surface of the dielectric layer；
S11: the second metal silicide layer is formed in the upper surface of the emitter-polysilicon 421 using rapid thermal treatment
431, and the emitter region 23 for the first conduction type being formed simultaneously in the base area 21；
S12: the upper surface of the dielectric layer 40 formed the base stage 51 that is connect with the polysilicon island 30 and with the hair
The emitter 52 that emitter polysilicon 421 connects；
S13: collector 53 is grown in the lower surface of the substrate 10.
In the production method of high-frequency triode of the present invention, using polysilicon technology and highly doped polycrystalline
Silicon forms the technology of outer base area, guarantees that the high-frequency triode can reach high frequency；The emitter contact hole 411 is logical
Cross directly individually etching formed, replace conventional double isolation side walls etching technics, reduce device technology difficulty and technique at
This.
With reference to the accompanying drawings, described high-frequency triode and preparation method thereof is elaborated.
Special to illustrate herein for convenience of subsequent description: first conduction type can be N-type, then, described second leads
Electric type is p-type, conversely, first conduction type may be p-type, correspondingly, second conduction type is N-type.?
In next embodiment, retouched so that first conduction type is N-type and second conduction type is p-type as an example
It states, but is defined not to this.
Referring to Fig. 4, executing step S01: providing substrate 10.Carrier of the substrate 10 as the high-frequency triode,
Primarily serve the effect of support.In the present embodiment, the substrate 10 is silicon substrate, and silicon is that most common, cheap and performance is stablized
Semiconductor material, can effectively reduce cost and promote yield.In other embodiments, the material of the substrate 10 may be used also
Think silicon carbide, germanium or germanium silicon etc..
In detail, the substrate 10 is the first conduction type.In the present embodiment, first conduction type is N-type, because
This described substrate 10 is N-type semiconductor.In other embodiments, first conduction type may be p-type, therefore, described
Substrate 10 is P-type semiconductor.The N-type substrate 10 can adulterate the elements such as phosphorus, arsenic, antimony by silicon and be formed, and not limit herein
It is fixed.
In more detail, the substrate 10 is highly doped semiconductor.In the present embodiment, the N-type substrate 10 is doping
The N+ substrate 10 of the N-type impurity of high concentration.Highly doped effect is the resistance for reducing the substrate 10, because the substrate 10
As electrode leads to client, reducing its resistance can be improved the response speed and current capacity of the high-frequency triode for lower surface, into
And the power of the high-frequency triode is promoted, increase its application range.Preferably, the resistivity of the N+ substrate 10 is less than 0.1
Ω·CM。
Further, in the surface grown epitaxial layer 20 of the substrate 10.Specifically institute is grown in the upper surface of the substrate 10
Epitaxial layer 20 is stated, the epitaxial layer 20 is silicon epitaxy layer.
In detail, the epitaxial layer 20 is the first conduction type.In the present embodiment, first conduction type is N-type,
Therefore epitaxial layer 20 is N-type semiconductor.In other embodiments, first conduction type may be p-type, therefore, described
Epitaxial layer 20 is P-type semiconductor.The N-type epitaxy layer 20 can adulterate the elements such as phosphorus, arsenic, antimony by silicon and be formed, herein not
It limits.
In more detail, the epitaxial layer 20 is the semiconductor being lightly doped.In the present embodiment, the N-type epitaxy layer 20 is
Adulterate the N- epitaxial layer 20 of the N-type impurity of low concentration.The purpose being lightly doped is to guarantee that the epitaxial layer 20 has biggish resistance
Value is so that it can bear biggish voltage, to promote the breakdown voltage of the high-frequency triode.Preferably, the extension
The resistivity of layer 20 is 0.5~10 Ω CM.Further, it is also possible to be promoted by the thickness for increasing the epitaxial layer 20 described outer
Prolong the ability that layer 20 bears voltage.Preferably, the epitaxial layer 20 with a thickness of 0.8~5 μm.
Specifically, the epitaxial layer 20 is grown in 10 upper surface of substrate using epitaxy method.The epitaxy method packet
Depositing operation is included, the depositing operation can be in electron beam evaporation, chemical vapor deposition, atomic layer deposition, sputtering
It is a kind of.Preferably, the epitaxial layer 20 is formed on the substrate 10 using chemical vapor deposition in the present embodiment.At other
In specific embodiment, the extension can also be formed on 10 surface of substrate by ion implanting and/or the method for diffusion
Layer 20.
Referring to Fig. 5, executing step S02: in the one polysilicon layer 30a of upper surface growth regulation of the epitaxial layer 20.It is described
First polysilicon layer 30a is made of undoped polysilicon.The thickness of the first polysilicon layer 30a is preferably 200~
500nm。
It specifically, can be using CVD method (Chemical Vapor Deposition, CVD) described outer
The upper surface for prolonging layer 20 deposits the first polysilicon layer 30a.
Further, in the one metal silicide layer 30b of upper surface growth regulation of the first polysilicon layer 30a.Described first
Metal silicide layer 30b is made of metal silicide, and the metal silicide can be silicide, such as titanium silicide, zirconium silicide, silicon
Change at least one of tantalum, tungsten silicide etc..In the present embodiment, the metal silicide is tungsten silicide.First metallic silicon
The thickness of compound layer 30b is preferably 50~200nm.In the present embodiment, after the first metal silicide layer 30b is for connecting
The first base polysilicon 31 and the second base polysilicon 422 formed during continuous, to form good Ohmic contact, substantially
Degree reduces base resistance.
It specifically, can be using CVD method in the upper surface of the first polysilicon layer 30a deposition described the
One metal silicide layer 30b.
Referring to Fig. 6, executing step S03: second that doping high concentration is formed in the first polysilicon layer 30a is conductive
The polysilicon doped regions 30c of type dopant.In the present embodiment, second conduction type is p-type, then second conductive-type
Type impurity is p type impurity comprising the substance of the elements such as boracic, indium or gallium.Preferably, the p type impurity is boron or fluorination
Boron.
Specifically, the polysilicon doped regions 30c, and described polysilicon doped regions 30c are formed by the way of injection
In the surface layer of the first polysilicon layer 30a.The first metal silicide layer 30b's and the first polysilicon layer 30a
Second conductive type impurity is injected on surface.In injection process, the depth of injection is greater than first metal silicide layer
The thickness of 30b, to guarantee that second conductive type impurity can penetrate the first metal silicide layer 30b, meanwhile, injection
Depth is less than the sum of the first metal silicide layer 30b and the first polysilicon layer 30a thickness again, avoids described second from leading
Electric type dopant penetrates the first polysilicon layer 30a, to form the polysilicon doping in the first polysilicon layer 30a
Area 30c.In detail, in injection process, being preferably injected dosage is 1E15~1E16CM-2, Implantation Energy is 30~180kev.
Referring to Fig. 7, executing step S04: partial penetration etches the first metal silicide layer 30b and described more than first
Crystal silicon layer 30a, and form the polysilicon island 30 for being located at the upper surface of the epitaxial layer 20.It is appreciated that the polysilicon island 30
It is made of the first metal silicide layer 30b and the first polysilicon layer 30a that are not etched away, in the first polysilicon layer 30a
Including the polysilicon doped regions 30c.In general, multiple three poles of the high frequency can be made on same wafer in the production process
Pipe, therefore, will form multiple polysilicon islands 30 in the upper surface of the epitaxial layer 20.In detail, the single polysilicon
Island 30 is preferably dimensioned to be 0.5~1.5um, and the spacing between multiple polysilicon islands 30 is preferably 0.5~1.0um.
Specifically, the polysilicon island 30 is formed to include the following steps: first the first metal silicide layer 30b's
Upper surface is laid with a layer photoresist layer (not shown), later using the mask plate with 30 figure of polysilicon island as exposure mask
The photoresist layer is exposed, then is developed, is formed and 30 figure one of polysilicon island on the photoresist layer
The window (not shown) of cause；Further, using the photoresist layer as exposure mask, from the photoresist layer by the way of etching
Window carries out substep to the first metal silicide layer 30b and the first polysilicon layer 30a and penetrates etching: the first step, carves
Lose the first metal silicide layer 30b；Second step etches the first polysilicon layer 30a.In detail, the side of the etching
Method includes dry etching and wet etching.In the present embodiment, it is preferred to use the method for dry etching.The quarter of the dry etching
Losing agent is plasma, using plasma and the substance reaction that is etched, forms volatile materials, or directly bombard the object that is etched
Matter is allowed to be corroded, and can be realized anisotropic etching, consequently facilitating ensure the shape and size of the polysilicon island 30
Precision, while in etching process, by accurately controlling etch amount, it is ensured that described in the corresponding region of the window
One polysilicon layer 30a is etched completely, avoids the epitaxial layer 20 to be carved as far as possible while locally exposure epitaxial layer 20
Erosion.In addition, dry etching easily realizes that automation, treatment process are not introduced into pollution, cleannes height.Produce the polysilicon island 30
Afterwards, the photoresist layer is first removed using cleaning solution.
Referring to Fig. 8, executing step S05: forming the outer base area 21 being located in the epitaxial layer 20.In detail, described outer
Base area 21 is the second conduction type.In the present embodiment, second conduction type is p-type, therefore the outer base area 21 is p-type
Semiconductor.In more detail, the outer base area 21 is highly doped semiconductor.It can be protected by the outer base area 21 for being arranged highly doped
Demonstrate,prove the frequency that the high-frequency triode can reach high.
Specifically, it forms the outer base area 21 and includes the following steps: that high-temperature heat treatment activates institute in the polysilicon island 30
The impurity for stating the second conduction type in the 30c of polysilicon doped regions makes the impurity part of second conduction type to described more
Regional diffusion other than doped polycrystal silicon area 30c, i.e., the impurity diffusion of described second conduction type to the first polysilicon layer 30a
And it further diffuses in the epitaxial layer 20.In high-temperature heat treatment process, the impurity of the second conduction type described first exists
Diffusion in the first polysilicon layer 30a, and the first polysilicon layer 30a is fully converted to the second conduction type of doping
First base polysilicon 31 of impurity, i.e., after high-temperature heat treatment, the polysilicon island 30 is by 31 He of the first base polysilicon
The first metal silicide layer 30b is constituted.With the propulsion of high-temperature heat treatment, the impurity of second conduction type is further
It diffuses into the epitaxial layer 20.Due to the second conduction type adulterated in the polysilicon doped regions 30c impurity it is dense
Degree is high, and during high-temperature heat treatment, the impurity of second conduction type is largely diffused in the epitaxial layer 20, and makes
Obtaining the local transoid of the epitaxial layer 20 becomes the outer base area 21.It is appreciated that the outer base area 21 and first base stage are more
Crystal silicon 31 connect, and the cross section of the outer base area 21 be greater than first base polysilicon 31 cross section, i.e., described first
View field of the base polysilicon 31 on the direction of the upper surface perpendicular to the substrate 10 is comprised in the outer base area 21
View field on the direction of the upper surface perpendicular to the substrate 10.
More specifically, the high-temperature heat treatment carries out in boiler tube.The temperature of the boiler tube is 800~950 DEG C, the height
The time of warm processing is 20~60min, and the junction depth of the outer base area 21 formed in the range is 0.1~0.5um.It is logical
Often, the junction depth of outer base area 21 is advisable be no more than the spacing of the polysilicon island 30 40%.
Referring to Fig. 9, executing step S06: forming the base area 22 being located in the epitaxial layer 20.In detail, the base area
22 be the second conduction type.In the present embodiment, second conduction type is p-type, therefore the outer base area 21 is that p-type is partly led
Body.In more detail, the base area 22 is connect with the outer base area 21, and the impurity of second conduction type is mixed in the base area 22
Doping concentration of the miscellaneous concentration lower than the impurity of the second conduction type in the outer base area 21.In the present embodiment, it described second leads
Electric type is p-type, then second conductive type impurity is p type impurity comprising the substance of the elements such as boracic, indium or gallium.It is excellent
Selection of land, the p type impurity are boron fluoride.
Specifically, forming the base area 22 includes the following steps: the upper surface from the epitaxial layer 20 to the epitaxial layer
20 carry out the impurity of the second conduction type of part doping.It is appreciated that 20 upper surface of epitaxial layer is formed with the polysilicon
Island 30 can pass through epitaxial layer locally exposed between the polysilicon island 30 when carrying out local adulterate to the epitaxial layer 20
20 surface is doped.The mode of the doping can be the mode of diffusion, be also possible to the mode of injection, in the present embodiment
In preferably using injection by the way of.The mode of the injection has purity is high, and good evenness can accurately control implantation dosage and depth
Degree, temperature is lower, is not susceptible to thermal defect, and it is more can to carry out selective area injection etc. as exposure mask using photoresist or metal
Weight advantage.
In more detail, in injection process, being preferably injected dosage is 1E13-5E13CM-2, Implantation Energy 10-50Kev,
Junction depth is injected within 0.1um.
Referring to Fig. 10, executing step S07: somatomedin layer 40.In the present embodiment, the thickness of the dielectric layer 40 is big
In the height of the polysilicon island 30, and the dielectric layer 40 be covered on the epitaxial layer 20 upper surface and the polysilicon island
30 upper surface.In other embodiments, the thickness of the dielectric layer may be set to be the height equal to the polysilicon island 30
Degree, the dielectric layer 40 are covered on the upper surface of the epitaxial layer 20.The effect of the dielectric layer 40 is to the epitaxial layer
20 and the polysilicon island 30 carry out insulation blocking.In detail, the dielectric layer 40 is the phosphorosilicate glass (BPSG) of boracic.At it
In his embodiment, the dielectric layer 90 can be the phosphorosilicate glass (PSG) of not boracic, be also possible to undoped silica glass
(USG), it can also be depositing silica at low pressure (LPTEOS).
Specifically, the dielectric layer 40 is formed to include the following steps: first using chemical vapour deposition technique in the extension
The upper surface of layer 20 and the upper surface of the polysilicon island 30 grow the dielectric layer 40, the dielectric layer 40 deposited
With a thickness of 500~1500nm；Further, planarization process carried out to the upper surface of the dielectric layer 40, after planarization process, position
It is at least 300nm in the thickness of the dielectric layer 40 of the upper surface of the polysilicon island 30.In detail, it is thrown using chemical machinery
The mode of light (Chemical Mechanical Polishing, CMP) carries out at planarization the upper surface of the dielectric layer 40
Reason.Chemical Mechanical Polishing Technique organically combines the mechanical abrasive action of abrasive grain with the chemical action of oxidant, can be real
The existing not damaged surface processing of ultraprecise, meets characteristic size in 0.35 μm of global planarizartion requirement below.It is specific real at other
It applies in mode, planarization process can also be carried out to the upper surface of the dielectric layer 40 by the way of dry etching.
Figure 11 is please referred to, step S08 is executed: through the etching dielectric layer 40, and forming contact hole 41, the contact hole
41 include emitter contact hole 411 and base stage contact hole 412.Wherein, the corresponding base area 22 of the emitter contact hole 411；
The corresponding polysilicon island 30 of the base stage contact hole 412.The emitter contact hole 411 be sized to it is smaller, with
Guarantee the frequency parameter of the high-frequency triode, the size of the preferably described emitter contact hole 411 is 0.15~0.4 μm.It is preferred that
The size of the base stage contact hole 412 is the half of the size of the polysilicon island 30.
Specifically, the emitter contact hole 411 is formed to include the following steps: first in the upper surface of the dielectric layer 40
It is laid with a layer photoresist layer (not shown), later using the mask plate with 411 figure of emitter contact hole as exposure mask
The photoresist layer is exposed, then is developed, is formed and 411 figure of emitter contact hole on the photoresist layer
The consistent window (not shown) of shape, view field of the window on the direction of the upper surface perpendicular to the substrate 10 is wrapped
It is contained in view field of the base area 22 on the direction of the upper surface perpendicular to the substrate 10；Further, with the photoetching
Glue-line penetrates etching to the dielectric layer 40 from the window of the photoresist layer by the way of etching as exposure mask, and etches
Shi Jinliang is performed etching along the direction on the surface perpendicular to the substrate 10.In detail, the etching is that dry anisotropic is carved
Erosion, etching gas is fluorine base gas, and the fluorine base gas is CF4, SF6, CHF3In any one.
Specifically, the base stage contact hole 412 is formed to include the following steps: to spread in the upper surface of the dielectric layer 40 first
If a layer photoresist layer (not shown), use has the mask plate of 412 figure of base stage contact hole as exposure mask to institute later
It states photoresist layer to be exposed, then develops, formed on the photoresist layer consistent with 412 figure of base stage contact hole
Window (not shown), view field of the window on the direction of the upper surface perpendicular to the substrate 10 be comprised in institute
State view field of the polysilicon island 30 on the direction of the upper surface perpendicular to the substrate 10；Further, with the photoresist
Layer is used as exposure mask, when penetrating etching to the dielectric layer 40 from the window of the photoresist layer by the way of etching, and etching
Direction as far as possible along the surface perpendicular to the substrate 10 performs etching.In detail, the etching is that dry anisotropic etches,
Etching gas is fluorine base gas, and the fluorine base gas is CF4, SF6, CHF3In any one.
It should be noted that form the emitter contact hole 411 synchronous can carry out with the base stage contact hole 412,
It can also carry out, be not limited thereto step by step.In addition, guaranteeing the choosing between etch media material and silicon materials as far as possible in etching
Ratio is selected, is hardly etched so that completing the base area 22 after the etching of the contact hole 41.
Please refer to Figure 12 and Figure 13, execute step S09: in the contact hole 41 and the upper surface of the dielectric layer 40 is raw
Long second polysilicon layer 42, wherein the contact hole 41 is fully filled with by the polysilicon being grown in the contact hole 41.It is described
Second polysilicon layer 42 is made of the polysilicon of the first conductive type impurity of doping high concentration.In the present embodiment, described
One conduction type is N-type, and first conductive type impurity is N-type impurity comprising the substance of the elements such as phosphorous, arsenic or antimony.
It is preferred that the N-type impurity is phosphorus or arsenic.In detail, the first conductive type impurity described in second polysilicon layer 42 is mixed
Miscellaneous concentration is 1E20~1E21CM-3.In more detail, the thickness of second polysilicon layer 42 is preferably 500~1000nm.
Specifically, it can use CVD method in the contact hole 41 and the upper surface of the dielectric layer 40 is heavy
Product second polysilicon layer 42.
Further, second polysilicon layer 42 is etched back, removal is located at the upper surface of the dielectric layer 40
Polysilicon simultaneously retains the polysilicon in the contact hole 41, to form the emitter being located in the emitter contact hole 411
Polysilicon 421 and the second base polysilicon 422 in the base stage contact hole 412.It is appreciated that the emitter polycrystalline
Silicon 421 and second base polysilicon 422 as second polysilicon layer 42, are led by the first of doping high concentration
The polysilicon of electric type dopant forms, and the emitter-polysilicon 421 connects the base area 22, second base polysilicon
422 connection the first metal silicide layer 30b.
Specifically, in the present embodiment, second polysilicon layer 42 is returned by the way of chemically mechanical polishing
Etching, chemically mechanical polishing can not only make the surface of second polysilicon layer 42 more flat, moreover it is possible to eliminate more than described second
The surface stress of crystal silicon layer 42.It in some other embodiments, can also be by the way of dry etching to more than described second
Crystal silicon layer 42 is etched back.It in other embodiments, can also be by way of wet etching to second polycrystalline
Silicon layer 42 is etched back.
Please refer to Figure 14, execute step S10: growth the first metal layer 43, the first metal layer 43, which is covered on, to be given an account of
The upper surface of the upper surface of matter layer 40 and the emitter-polysilicon 421 and second base polysilicon 422.In detail, institute
State the first metal layer 43 with a thickness of 20~100nm.In more detail, the first metal layer 43 can by Titanium, zirconium, tantalum,
At least one of tungsten etc. composition.In the present embodiment, the first metal layer 43 is made of Titanium.
Specifically, upper surface and the emitter-polysilicon of the CVD method in the dielectric layer 40 can be used
421 and the upper surface of second base polysilicon 422 deposit the first metal layer 43.
Figure 15 is please referred to, step S11 is executed: forming the second metal silicide layer 431 and third metal silicide layer 432,
Second metal silicide layer 431 is located at the upper surface of the emitter-polysilicon 421, the third metal silicide layer
432 are located at the upper surface of second base polysilicon 422.Second metal silicide layer 431 and the third metallic silicon
Compound layer 432 is made of metal silicide, and the metal silicide can be silicide, such as titanium silicide, zirconium silicide, silication
At least one of tantalum, tungsten silicide etc..In addition, second metal silicide layer 431 and the third metal silicide layer 432
It can be and be made of same metal silicide, be also possible to metal silicide composition not of the same race.In order to facilitate manufacture, in this implementation
In example, preferably described second metal silicide layer 431 and the third metal silicide layer 432 be can be by same metal silication
Object composition.In addition, the metal silicide of composition second metal silicide layer 431 and the third metal silicide layer 432
Can be identical with the metal silicide for forming the first metal silicide layer 30b, can not also be identical, it is not limited thereto.
In the present embodiment, the metal silicide of second metal silicide layer 431 and the third metal silicide layer 432 is formed
It is not identical as the metal silicide of composition the first metal silicide layer 30b.In the present embodiment, second metal is formed
The metal silicide of silicide layer 431 and the third metal silicide layer 432 is transformed by the first metal layer 43,
Therefore, the metal silicide is titanium silicide.
Meanwhile emitter region 23 is also formed, the emitter region 23 is located in the base area 22.In detail, the emitter region 23
For the first conduction type.In the present embodiment, first conduction type is N-type, therefore the emitter region 23 is that N-type is partly led
Body.
Specifically, it is formed simultaneously using the method for rapid thermal treatment (Rapid Thermal Processing, RTP) described
Second metal silicide layer 431, the third metal silicide layer 432 and the emitter region 23.The rapid thermal treatment includes
Three one-step rapid thermal anneals (Rapid Thermal Annealing, RTA).In detail, forming the outer base area 21 includes following step
It is rapid: to be first step quick thermal annealing process first, the temperature of the first step quick thermal annealing process is 640~740 DEG C, the time
For 10~30s.During first step quick thermal annealing process, silicon can with metal reaction and form metal silicide, i.e. institute
It states emitter-polysilicon 421 and is located at the first metal layer 43 of the upper surface of the emitter-polysilicon 421 on contact interface
It reacts, and forms the second metal silicide layer 431 for being located at 421 upper surface of emitter-polysilicon；Second base
Pole polysilicon 422 and the first metal layer 43 for the upper surface for being located at second base polysilicon 422 occur on contact interface
Reaction, and form the third metal silicide layer 432 for being located at the upper surface of second base polysilicon 422.It is appreciated that institute
State the first metal layer 43 be located at the dielectric layer 40 upper surface partially due to do not contact elemental silicon, therefore will not be converted to
Metal silicide, and the first metal layer 43 is located at the emitter-polysilicon 421 and second base polysilicon 422
Upper surface and metal silicide will not be converted to far from the part of contact interface.For unreacted in the first metal layer 43
Metal can be removed in the follow-up process by wet etching.In the present embodiment, because the first metal layer 43 by
Titanium composition, therefore second metal silicide layer 431 and the third metal silicide layer 432 that are formed are by titanium silicide
Composition.It is the slightly higher titanium silicide of C49 phase resistance rate that titanium silicide is formed by during first step quick thermal annealing process.It connects
Get off and carry out second step quick thermal annealing process, the temperature of the second step quick thermal annealing process is 750~850 DEG C.?
During the processing of two one-step rapid thermal anneals, it is lower that the slightly higher titanium silicide of the C49 phase resistance rate is converted into C49 phase resistance rate
Titanium silicide.Then third step quick thermal annealing process is carried out, the temperature of the third step quick thermal annealing process is 850~1100
DEG C, the time is 20~120s.During third step quick thermal annealing process, in the emitter-polysilicon 421 first
Conductive type impurity is by activated at and diffuses in the base area 22 connecting with the emitter-polysilicon 421.Although the base
Area 22 is the second conduction type, but since the doping concentration of the first conductive type impurity in the emitter-polysilicon 421 is high,
First conductive type impurity largely diffuses into the base area 22, and the local transoid in the base area 22 is made to become first
The emitter region 23 of conduction type.Since the emitter region 23 is impurity in the emitter-polysilicon 421 to external diffusion and shape
At, can avoid ion implanting and caused by residual impairment, while extremely shallow emitter junction can be made.The usual emitter junction
Depth be less than the base area 22 junction depth.
Figure 16 and Figure 17 are please referred to, step S12 is executed: being removed in wet etching unreacted in the first metal layer 43
After metal, the upper surface of the dielectric layer 40 and second metal silicide layer 431 and the third metal silicide layer 432
Upper surface grow second metal layer 50.The second metal layer 50 is preferably made of the preferable metal of electric conductivity.It needs herein
Illustrate, form the metal of the second metal layer 50 with form the first metal layer 43 metal can it is identical can also be with
It is not identical, it is not limited thereto.
Specifically, upper surface and second metal silication of the CVD method in the dielectric layer 40 can be used
The upper surface of nitride layer 431 and the third metal silicide layer 432 deposits the second metal layer 50.
Further, it etches the second metal layer 50 and forms base stage 51 and emitter 52, the base stage 51 connects described
Third metal silicide layer 432, the emitter 52 connect second metal silicide layer 431.
Specifically, it forms the base stage 51 and the emitter 52 includes the following steps: in the second metal layer 50
Upper surface covers a layer photoresist layer (not shown), is exposed to the photoresist layer, (figure is not for the first occlusion part of formation that develops
Show) and the second occlusion part (not shown), wherein first occlusion part is directed at the third metal silicide layer 432, described the
Two occlusion parts are directed at second metal silicide layer 431；The second metal layer 50 is performed etching, second gold medal is removed
Belong to the part not covered by first occlusion part and second occlusion part in layer 50, leaves corresponding first occlusion part
With the part of second occlusion part and be respectively formed base stage 51 and emitter 52.In detail, the method for the etching includes dry
Method etching and wet etching.In the present embodiment, it is preferred to use the method for wet etching.The wet etching is carved by chemistry
Erosion liquid and the substance that is etched, which occur to chemically react the substance that will be etched, to be stripped down, with preferable isotropic etching, because
This is convenient for the quick silicon nitride layer for removing the window's position.In addition, wet etching also have it is easy to operate, low for equipment requirements, easy
In realize produce in enormous quantities the characteristics of.After producing the base stage 51 and the emitter 52, first removed using cleaning solution described in
Photoresist layer.
In some other embodiment, in the case where the first metal layer 43 compares thick, described can also be retained
One metal layer 43, and the base stage 51 and the emitter 52 are formed by etching the first metal layer 43.Other one
The first metal layer 43 can also be retained in a little embodiments, and grow described second in the upper surface of the first metal layer 43
Metal layer 50, and the base stage 51 and the hair are formed by etching the first metal layer 43 and the second metal layer 50
Emitter-base bandgap grading 52, is not limited thereto.
Figure 18 is please referred to, step S13 is executed: in the substrate 10 in the following, the i.e. described substrate 10 is relatively described to prolong layer 20
One side surface deposits one layer of metal layer and constitutes collector 53.Preferably, the metal layer for constituting the collector 53 is TiNiAg
Complex metal layer.
In detail, the substrate 10 is first thinned before forming the collector 53.The substrate 10 is thinned, can not only have
There is lower collector resistance, while there can also be better heating conduction.In general, be thinned after the substrate 10 with a thickness of
80~200 μm.
The foregoing is merely one embodiment of the present of invention, are not intended to limit the invention, all in essence of the invention
Within mind and principle, any modification, equivalent substitution, improvement and etc. done be should be included within the scope of the present invention.
Claims (10)
1. a kind of high-frequency triode characterized by comprising
The substrate of first conduction type；
Positioned at the epitaxial layer of the first conduction type of the upper surface of the substrate, the second conduction type is formed in the epitaxial layer
Outer base area and connect the outer base area the second conduction type base area, the impurity of the second conduction type in the outer base area
Doping concentration is higher than the doping concentration of the impurity of the second conduction type in the base area；The first conduction is also formed in the base area
The emitter region of type；
Polysilicon island positioned at the upper surface of the epitaxial layer, the polysilicon island include that is connect and adulterated with the outer base area
First base polysilicon of the impurity of two conduction types；
Dielectric layer positioned at the upper surface and thickness of the epitaxial layer more than or equal to the height of the polysilicon island, the medium
The contact hole of the dielectric layer is formed through in layer, the contact hole includes the emitter contact hole of the corresponding emitter region,
The emitter-polysilicon of impurity filled with the first conduction type of doping in the emitter contact hole, the emitter-polysilicon
Upper surface be covered with the second metal silicide layer；
Base stage and emitter positioned at the upper surface of the dielectric layer, the base stage are connect with the polysilicon island, the transmitting
Pole is connect with the emitter-polysilicon；
Collector positioned at the lower surface of the substrate.
2. high-frequency triode according to claim 1, which is characterized in that the polysilicon island further includes being located at described first
First metal silicide layer of base polysilicon upper surface.
3. high-frequency triode according to claim 1, which is characterized in that the dielectric layer is covered on the epitaxial layer and institute
The upper surface of polysilicon island is stated, the contact hole further includes the base stage contact hole of the corresponding polysilicon island, the base stage contact
Second base polysilicon of the impurity filled with the first conduction type of doping in hole, the upper surface of second base polysilicon is covered
It is stamped third metal silicide layer.
4. a kind of production method of high-frequency triode, which comprises the following steps:
S01: the substrate of the first conduction type, and the epitaxial layer of one conduction type of upper surface growth regulation in the substrate are provided；
S02: in one polysilicon layer of upper surface growth regulation of the epitaxial layer；
S03: the impurity of the second conduction type is injected to first polysilicon layer and in the surface shape of first polysilicon layer
At polysilicon doped regions；
S04: carrying out partial penetration etching to first polysilicon layer and forms the polycrystalline positioned at the upper surface of the epitaxial layer
Silicon island；
S05: high-temperature heat treatment makes the impurity of the second conduction type in the polysilicon doped regions in first polysilicon layer
Middle diffusion simultaneously converts first polysilicon layer to the first base polysilicon for adulterating the impurity of the second conduction type, while institute
The impurity diffusion of the second conduction type is stated into the epitaxial layer and forms the second conduction type being located in the epitaxial layer
Outer base area；
S06: locally adulterating the impurity of the second conduction type to the epitaxial layer, is formed and is located in the epitaxial layer and described in connection
The base area of second conduction type of outer base area, the doping concentration of the impurity of the second conduction type is lower than the outer base in the base area
The doping concentration of the impurity of second conduction type in area；
S07: it is greater than or equal to the dielectric layer of the height of the polysilicon island in the upper surface growth thickness of the epitaxial layer；
S08: etching the dielectric layer and forms the emitter contact hole for running through the dielectric layer, and the emitter contact hole is corresponding
The base area；
S09: the polysilicon of the first conductive type impurity of filling doping high concentration in the emitter contact hole, and form position
Emitter-polysilicon in the emitter contact hole；
S10: the first metal layer is grown in the upper surface of the dielectric layer and the emitter-polysilicon；
S11: the second metal silicide layer, and shape simultaneously are formed in the upper surface of the emitter-polysilicon using rapid thermal treatment
At the emitter region for the first conduction type being located in the base area；
S12: the upper surface of the dielectric layer formed the base stage that is connect with the polysilicon island and with the emitter-polysilicon
The emitter of connection；
S13: collector is grown in the lower surface of the substrate.
5. the production method of high-frequency triode according to claim 4, which is characterized in that in S02 further include described
One metal silicide layer of upper surface growth regulation of first polysilicon layer, in S04 simultaneously to first metal silicide layer into
Row partial penetration etching.
6. the production method of high-frequency triode according to claim 4, which is characterized in that in S07, the dielectric layer
Thickness is greater than the height of the polysilicon island and is covered on the upper surface of the polysilicon island simultaneously, further includes etching in S08
The dielectric layer simultaneously forms the base stage contact hole for running through the dielectric layer, and the base stage contact hole corresponds to the polysilicon island；?
In S09 further include the polysilicon of the first conductive type impurity of filling doping high concentration in the base stage contact hole, and is formed
The second base polysilicon in the base stage contact hole；It further include the upper table in second base polysilicon in S11
Face forms third metal silicide layer.
7. the production method of high-frequency triode according to claim 4, which is characterized in that high-temperature heat treatment described in S05
Temperature be 800~950 DEG C, the time be 20~60min.
8. the production method of high-frequency triode according to claim 4, which is characterized in that rapid thermal treatment described in S11
Including three one-step rapid thermal anneals processing, wherein the temperature of first step quick thermal annealing process be 680~740 DEG C, the time be 10~
30s；The temperature of second step quick thermal annealing process is 750~850 DEG C；The temperature of third step quick thermal annealing process be 850~
110 DEG C, the time is 20~120s.
9. the production method of high-frequency triode according to claim 4, which is characterized in that the ruler of the emitter contact hole
Very little is 0.15~0.4 μm.
10. the production method of high-frequency triode according to claim 4, which is characterized in that in S13, described in growth
The thickness of the substrate is first thinned before collector from the lower surface of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811119427.8A CN109300982A (en) | 2018-09-25 | 2018-09-25 | High frequency triode and method of making the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811119427.8A CN109300982A (en) | 2018-09-25 | 2018-09-25 | High frequency triode and method of making the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109300982A true CN109300982A (en) | 2019-02-01 |
Family
ID=65164422
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811119427.8A Withdrawn CN109300982A (en) | 2018-09-25 | 2018-09-25 | High frequency triode and method of making the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109300982A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112151603A (en) * | 2020-09-28 | 2020-12-29 | 上海华虹宏力半导体制造有限公司 | Triode and forming method thereof |
| CN112864230A (en) * | 2021-03-12 | 2021-05-28 | 深圳市昭矽微电子科技有限公司 | Bipolar transistor and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07235647A (en) * | 1990-08-20 | 1995-09-05 | Natl Semiconductor Corp <Ns> | Longitudinal direction type fuse device |
| US5557131A (en) * | 1992-10-19 | 1996-09-17 | At&T Global Information Solutions Company | Elevated emitter for double poly BICMOS devices |
| CN1325548A (en) * | 1998-11-06 | 2001-12-05 | 国际商业机器公司 | Transistor array |
| CN108172515A (en) * | 2017-12-25 | 2018-06-15 | 深圳市晶特智造科技有限公司 | High-frequency triode and its manufacturing method |
-
2018
- 2018-09-25 CN CN201811119427.8A patent/CN109300982A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07235647A (en) * | 1990-08-20 | 1995-09-05 | Natl Semiconductor Corp <Ns> | Longitudinal direction type fuse device |
| US5557131A (en) * | 1992-10-19 | 1996-09-17 | At&T Global Information Solutions Company | Elevated emitter for double poly BICMOS devices |
| CN1325548A (en) * | 1998-11-06 | 2001-12-05 | 国际商业机器公司 | Transistor array |
| CN108172515A (en) * | 2017-12-25 | 2018-06-15 | 深圳市晶特智造科技有限公司 | High-frequency triode and its manufacturing method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112151603A (en) * | 2020-09-28 | 2020-12-29 | 上海华虹宏力半导体制造有限公司 | Triode and forming method thereof |
| CN112151603B (en) * | 2020-09-28 | 2023-08-18 | 上海华虹宏力半导体制造有限公司 | Triode and forming method thereof |
| CN112864230A (en) * | 2021-03-12 | 2021-05-28 | 深圳市昭矽微电子科技有限公司 | Bipolar transistor and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4338138A (en) | Process for fabricating a bipolar transistor | |
| EP0036082B1 (en) | A self-aligned process for providing an improved high performance bipolar transistor | |
| CN100508209C (en) | NPN type germanium-silicon heterogenous dual-pole transistor and its making method | |
| KR100307183B1 (en) | A Bipolar Device and A Method for Manufacturing the Bipolar Device | |
| US4446476A (en) | Integrated circuit having a sublayer electrical contact and fabrication thereof | |
| KR20020083107A (en) | Lateral transistor having graded base region, semiconductor integrated circuit and fabrication method thereof | |
| TWI480951B (en) | Wide trench terminal structure for semiconductor components | |
| US6686250B1 (en) | Method of forming self-aligned bipolar transistor | |
| US5086016A (en) | Method of making semiconductor device contact including transition metal-compound dopant source | |
| US6440810B1 (en) | Method in the fabrication of a silicon bipolar transistor | |
| CN109461767A (en) | A kind of super-junction structure and preparation method thereof | |
| CN109300982A (en) | High frequency triode and method of making the same | |
| CN109087942A (en) | A kind of groove-shaped triode and preparation method thereof | |
| CN108231583B (en) | Bipolar transistor and manufacturing method thereof | |
| JP2597631B2 (en) | Semiconductor device and method of manufacturing the same | |
| CN108133892B (en) | How to make a bipolar transistor | |
| CN110085669A (en) | A kind of triode and preparation method thereof | |
| CN112750695B (en) | Trench gate IGBT device and manufacturing method thereof | |
| JP2001196382A (en) | Semiconductor device and manufacturing method thereof | |
| US7049240B2 (en) | Formation method of SiGe HBT | |
| CN109411347A (en) | Triode and preparation method thereof | |
| JPH05283520A (en) | Manufacture of semiconductor device | |
| CN108461549B (en) | Silicon carbide diode device and preparation method thereof | |
| CN110098252A (en) | A kind of triode and preparation method thereof | |
| CN109449200A (en) | Horizontal triode and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20190201 |
|
| WW01 | Invention patent application withdrawn after publication |