CN109285576B - Memory device - Google Patents

Abstract

A memory device is described having a field of memory cells, wherein each column is associated with one bit line and each row is associated with one word line, wherein the columns comprise: a first column of memory cells storing valid data; and a second column type of columns of memory cells storing preset verification data, wherein memory cells of at least the second column type of columns of memory cells upon a read access place an associated bit line at a value corresponding to a logical combination of values stored by memory cells of the second column type of columns, the memory cells belonging to a row of memory cells addressed upon a read access; and a detection circuit designed to detect, upon a read access, whether a bit line associated with a column of memory cells of the second column type is set to a value corresponding to a logical combination of values stored by memory cells of the column of memory cells of the second column type, and the values of the memory cells belonging to different rows of memory cells.

Description

Memory device

Technical Field

Embodiments generally relate to memory devices.

Background technique

Electronic devices have to be protected against attacks in a large number of applications. Typical examples are chip cards, which process and store secret data (e.g. keys or passwords) or data that should be protected against manipulation (e.g. deposits on prepaid cards), or also control devices, e.g. in vehicles, the correct functioning of which is important for the safety of the user. A possible attack point on an electronic device is its memory, by tampering with which an attacker could learn secret data or impair the correct functioning of the electronic device. Effective mechanisms for protecting electronic memories are therefore desired.

Summary of the invention

According to one embodiment, a memory device is provided, the memory device having: a memory cell field, the memory cell field having memory cell columns and memory cell rows; bit lines and word lines, wherein each column is associated with a bit line, and each row is associated with a word line, wherein the memory cell columns include: a memory cell column of a first column type, which is designed to store valid data; and a memory cell column of a second column type, which is designed to store preset verification data. At least the memory cells of the memory cell column of the second column type are designed and connected to the bit lines so that the memory cells of a memory cell column set the bit lines associated with the column to the following value during a read access, the value corresponding to the logical combination of the values stored by the memory cells of the column, and these memory cells belong to the memory cell row addressed during the read access. The memory device has a detection circuit, the detection circuit being designed to: during a read access, detect whether the bit lines associated with a memory cell column of the second column type are set to the following value, the value corresponding to the logical combination of the values stored by the memory cells of the memory cell column of the second column type, and the values of these memory cells belong to different memory cell rows.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings do not depict actual size relationships, but should be used to illustrate the principles of different embodiments. In the following, different embodiments are described with reference to the following drawings.

FIG. 1 shows a memory cell field.

FIG. 2 shows two memory cells which are associated with the same bit line and are connected to it by means of corresponding pull-down transistors.

FIG. 3 shows the expansion of a memory cell field to store memory cells for storing verify data which is based on the simultaneous activation of a plurality of word lines.

FIG. 4 shows an example of two memory cell rows, each storing a pre-calculated bit pattern.

FIG5 shows a memory device.

The following detailed description relates to the attached drawings showing details and embodiments. The embodiments are described in detail so that those skilled in the art can implement the present invention. Other embodiments are also feasible, and the embodiments can be changed in structure, logic and electricity without departing from the subject matter of the present invention. Different embodiments do not have to be mutually exclusive, but different embodiments can be combined with each other to form new embodiments. Within the scope of this specification, the terms "connect", "connect" and "couple" are used to describe direct and indirect connections, direct or indirect connections and direct or indirect couplings.

Detailed ways

Electronic memories typically have a lattice (a two-dimensional field or array or matrix) of memory cells with rows addressed by word lines and columns addressed by bit lines.

FIG. 1 shows a memory cell field 100 .

The memory cell field has a plurality of memory cells 101 which are arranged in the form of a matrix having memory cell columns 102 and memory cell rows 103 .

Each memory cell column 102 is associated with one bit line 104 , and each memory cell row 103 is associated with one word line 105 .

By activating a word line 105 , all memory cells (or a portion thereof) of a row 103 addressed via said word line (ie the row 103 associated with said word line) can be read or written simultaneously by means of the bit lines 104 .

In order to achieve a memory structure that saves as much space as possible, all memory cells that can be addressed via the proposed bit line (i.e., all memory cells that are associated with a bit line, i.e., connected to the bit line) can be connected to the bit line via a special switching technology ("open drain" or "wired OR"). An example of such a switching technology is shown in FIG. 2.

FIG. 2 shows two memory cells 201 , 202 which are associated with the same bit line 203 and are connected to the bit line 203 by means of respective pull-down transistors 204 , 205 .

Each memory cell 202 , 203 is also connected to a corresponding word line 206 , 207 .

In this example, for example, during a read access, the bit line 203 is precharged to a high potential (by means of so-called "precharge"), one of the word lines 206, 207 is activated, and the memory cells 201, 202 associated with the activated word lines 206, 207, depending on whether they store 1 or 0, pull the bit line 203 down (to a low potential) or not.

If the stored 0 corresponds, for example, to the activation of the corresponding pull-down transistor 204 , 205 , the memory cell 201 , 202 pulls the bit line 203 to a low potential when it stores a 0, which is then interpreted as outputting a 0 on the bit line 203 .

If both word lines 206, 207 are now activated, it is sufficient that one of the two memory cells 201, 202 stores a 0 in order to pull the bit line 203 down. Conversely, the bit line 203 remains at a high potential only if both memory cells 201, 202 store a 1. Thus, in the case of simultaneous activation of multiple word lines, the bit line 203 is set to a logical combination of the stored values, in this example an AND combination (since the bit line remains at 1 only if both memory cells 201, 202 store a 1).

Depending on which voltage potential the stored 1 and the stored 0 are associated with and whether pull-up transistors are used instead of pull-down transistors 204 , 205 , a combination of the values stored by memory cells 201 , 202 can also be obtained as the value to which bit line 203 is set and which is output by bit line 203 .

The connection of a plurality of memory cells to one bit line by means of switching technology as described with reference to FIG. 2 allows for the saving of transistors and does not present functional limitations for the normal operation of the memory array. However, for an attacker, due to the fact that a logical combination of the memory contents is output to one bit line when a plurality of word lines are addressed simultaneously, the following possibilities for carrying out specific attacks are obtained:

If an attacker simultaneously activates a plurality of word lines of a memory cell field by an invasive attack during a read access to the memory (e.g. by a forced attack by means of a probe or by means of a laser), the switching technique implicitly causes the logical relationship of all simultaneously activated memory cells associated with this bit line to be read at the bit line. As explained above, depending on the switching technique and the structure of the memory cell field, the result of this implicit calculation is a logical AND combination or a logical OR combination of the simultaneously activated (i.e. word line addressed) memory cells associated with this bit line.

Similarly, an attacker, when he activates multiple word lines of a memory cell field simultaneously during a write access, places an undesired copy of the data to be stored at an otherwise unused position in the memory cell field. The attacker can then play this copy again at a later point in time during a read access by activating the appropriate word line and in this way generate a false system state (thus performing a so-called "clone" and "replay" attack). In this way, the attacker can prevent, for example, a counter representing a monetary value from expiring and triggering a security alarm, which counter represents a monetary value or which should identify a brute force attack on PINs and passwords.

For security applications, the memory cell field can be extended with address encoding of word lines so as to be able to identify occasional transient misaddressing of word lines or permanent defects in the cell field. For this, for example, a pre-calculated bit pattern is permanently inserted into the cell array. This can be done, for example, by technology such as in ROM memory cells or by appropriate changes to the memory cells used (for example, omitting contacts or omitting transistors of individual memory cells). Although the technology can realize the identification of faults with preset redundancy, it is typically not suitable for providing protection against active attackers. In addition, the linear code typically used for efficiency reasons is incompatible with the relationship of logical and or logical or by bit by multiple activated word lines. Linear codes are usually defined as vector spaces about finite fields, and only their characteristics about the associative mapping in the vector space are maintained. Invasive attackers can purposefully exploit the incompatibility of the associative mapping in the part of the cell field that encodes the address of the word line, so as to bypass the characteristics of the fault identification of the code used by activating multiple word lines at the same time. If the read data does not contain any other redundant information to verify its validity, such an attack cannot be identified.

Since the field (also called "array") of memory cells can be easily identified in the layout of the integrated circuit due to its size on the one hand, and can be easily analyzed and manipulated due to its regular, standardized structure on the other hand, it is necessary for integrated circuits for security applications to be able to verify during operation that data is read from the correct memory cell of the memory cell field addressed by the application or is written to the correct, addressed memory cell. In addition to checking the physical address of the memory cell actually used for reading or writing, this also includes, in particular, mechanisms to protect against attacks by simultaneously activating multiple word lines in the memory cell field.

Such a mechanism is described below and, according to an exemplary embodiment, is based on a specific data pattern which can be attached to the word lines of the memory array, for example, as a fixed (e.g. ROM) pattern and can be read via additional bit lines. The data pattern enables reliable detection of attacks that activate multiple word lines simultaneously, with the aid of a predefined redundancy of the alarm circuits for signaling a detected attack.

FIG. 3 shows a memory cell field for storing verification data, for example a code word or a data pattern, for the expansion of the memory cells for protection against attacks which are based on the simultaneous activation of a plurality of word lines.

Similar to the memory cell field 100 of FIG. 1 , the memory cell field 300 has a plurality of memory cells 301, which are arranged in the form of a matrix, the matrix having memory cell columns 302, 303 and memory cell rows 304, wherein in this example, the memory cell field 300 includes: a first memory cell column 302 (also referred to as a column of the first column type) for storing valid data (i.e., a "normal" memory cell that can be written to store data, the "normal" memory cell can be used normally, for example, by a processor of an electronic device, such as a chip card or a control device); and a second memory cell column 303 (also referred to as a column of the second column type) for storing verification data. Each memory cell column 302, 303 is associated with a bit line 305, and each memory cell row 304 is associated with a word line 306.

The second column 303 can be regarded as an extension of the memory cell field formed by the first column 302. In other words, according to one embodiment, the word lines of the memory cell field are extended and further memory cells and associated bit lines are added. In this way, a precalculated bit pattern can be inserted (for example permanently) into the memory cell field by means of the additional memory cells, namely the memory cells of the second column 303.

The precalculated bit pattern can be read out by means of a further bit line, namely the bit line 305 associated with the second column 303. The memory cells of the second column 303 are designed and connected to the associated bit line in such a way that, when a plurality of word lines 306 are activated simultaneously, the bit line is subjected to the same bitwise logical AND or OR relationship of all activated memory cells as the rest of the memory cell field, namely the bit lines associated with the first memory cell column 302.

In the examples that follow it is assumed that memory cells of a word line that are activated simultaneously and are associated with the same bit line set the bit line to a logical OR relationship of the bits stored thereby, but the bits can similarly be used for a logical AND relationship.

According to one embodiment, the memory cells of the second column 303 store a pre-calculated bit pattern, wherein all memory cells of a row 304 belonging to the second column 303 store the pre-calculated bit pattern, i.e. a pre-calculated bit pattern belongs to each memory cell row 304, and wherein it applies that:

A) All pre-calculated bit patterns have the same Hamming weight w>0, in order to enable the most efficient possible recognition in the absence of errors.

B) If two or more word lines are activated simultaneously, the resulting pattern has a Hamming weight of at least w+d, which results from a bitwise logical OR relationship of bit patterns belonging to the row of memory cells associated with the activated word lines, where d>0 is a preset constant for redundantly identifying the simultaneous activation of multiple word lines.

FIG. 4 shows an example of two memory cell rows 401 , 402 , which each store a precalculated bit pattern.

Each memory cell row 401 , 402 has first memory cells 403 , which form a first memory cell column for storing valid data, and second memory cells 404 for storing check data, which in this case is a precalculated bit pattern that is 6 bits long.

In this example, the first memory cell row 401 stores the bit pattern 000111 and the second memory cell row 402 stores the bit pattern 001011.

According to A), both bit patterns have the same Hamming weight w=3.

According to B), the resulting bit pattern resulting from the OR combination of the two bit patterns has a weight greater than 3, namely 4 (the weight of 001111, which is the bitwise OR combination of 000111 and 001011).

Based on A) and B), a detection circuit 307 connected to the bit line associated with the second column for detecting an attack based on the simultaneous activation of multiple word lines can be set as follows: the detection circuit determines the number x of bits with the value 1 in the resulting bit pattern output by the bit line associated with the second column 303, and compares the number with the Hamming weight w of the original pre-calculated bit pattern. If x>w, then this indicates that multiple word lines are activated simultaneously.

If, for example, the six bit lines connected to the second memory cell 404 of the example of Figure 4 provide the pattern 001111, then the detection circuit 307 can determine that the weight of the resulting pattern is greater than the weight of the precalculated bit pattern (4>3) and can react accordingly, for example, by outputting an alarm signal via the alarm signal output line 308 of the detection circuit 307, for example, to a processor of a corresponding electronic device or also to a reset circuit, which resets the electronic device (and, for example, in particular clears the memory) when an alarm occurs.

The value d can be regarded as a redundancy for identifying the simultaneous activation of multiple word lines. An attacker must falsify the resulting pattern at d bits in order to achieve simultaneous activation of multiple word lines without detecting this. In order to achieve the desired redundancy d as a whole (i.e. the desired redundancy of the total system consisting of memory and detection circuit), for example, a total of d detection circuits (and corresponding warning signal output lines 308) can be provided. Thus, d-fold redundancy is also obtained at the level of the detection circuit. As a result, an attacker must falsify d detection circuits in order to achieve simultaneous activation of multiple word lines without detecting this.

The detection based on the pre-calculated bit patterns with specific weights and the determination of the weights of the resulting (output) bit patterns as described above can be realized by means of a simple decoding of the resulting bit patterns (determining their weights). Therefore, the detection circuit 307 can be realized by a simple circuit for distinguishing whether a plurality of word lines or a single word line are activated simultaneously. The circuit only has to determine the Hamming weight of the bit pattern read from the second column 303 of the memory cell field and compare it with a preset reference value (Hamming weight w) and output an alarm signal according to the comparison result. The desired d-fold redundancy of the hardware of the detection circuit can be realized by a d-fold repetition circuit.

A bit pattern suitable for marking additional cells in the memory field can be obtained in a simple manner from the linear code. Below, a general construction method for generating a suitable bit pattern with the desired properties A) and B) is described. The following example is based on the fact that the logical combination is an OR combination. However, the bit pattern for the logical AND relationship can be determined in an analogous manner, wherein the Hamming weight of the bit pattern obtained when multiple word lines are activated simultaneously is correspondingly reduced compared to the Hamming weight of the precalculated bit pattern.

The construction method described below, on the one hand, proves the existence of a suitable bit pattern which satisfies A) and B) and, on the other hand, provides an upper limit for the length of a bit pattern which is suitable for marking a word line.

If a linear (n, k, d) code is given for GF ₂ (a finite field with two elements) of length n, dimension k and redundancy d, then there is a set of (2n, k, d) bit patterns of 2 ^k bit patterns of length 2n for marking wordlines, making it possible to identify simultaneous activation of multiple wordlines with d-fold redundancy: If x=( _xn , ..., _x1 ) is a codeword of the linear code, then the associated bit pattern y is given by y=( _yn , ..., _y1 ), where it applies that for 1≤i≤n, if _xi =0, then _yi =01, and if _xi =1, then _yi =10.

If each row of a memory cell field is marked with a bit pattern y generated in this way, then all marked bit patterns y have a Hamming weight HW(y)=n after construction. The properties of the linear code used also ensure that two different bit patterns are distinguished at at least d bit pairs _yi . If at least two word lines are now activated simultaneously, then at at least d bits, the bit pairs "01" and "10" are changed to the "11" pattern by a logical OR relationship. The Hamming weight of the resulting bit pattern is thereby increased by at least the required value d.

On the other hand, assuming that a marking pattern of length n contains exactly e 1 bits and (n-e) 0 bits, it applies that for each marking pattern y with redundancy d, in order to identify a plurality of activated word lines, there is at least one environment consisting of a U(n,e,d) pattern with e 1s and (n-e) 0s, which cannot be used as a marking pattern because it differs from the marking pattern y in less than d bits. It is thus possible to determine a lower limit for the length n of the marking pattern according to the invention.

If we consider the set of all bit sequences with a fixed number of bits having the value 1, we get an example of a bit pattern for marking a word line.

16 arbitrary elements of M = {000111, 001011, 001101, 001110, 010011, 010101, 010110, 011001, 011010, 011100, 100011, 100101, 100110, 101001, 101010, 101100, 110001, 110010, 110100, 111000} each result in a (6, 4, 1) marking pattern. Each two patterns differ in at least one position. It is generally applicable that such a bit pattern must satisfy the inequality

In another embodiment, 16 elements from the set M are selected so that the simplest possible decoding of the addresses of the marked word lines is achieved, i.e. each word line is associated in a simple manner one-to-one with a bit pattern, which enables the address of the activated word line to be reconstructed in an efficient manner from the value of the associated marking pattern in M: the set M contains, for example, 14 patterns 000111, 001011, 001101, 010011, 010101, 011001, 011100, 100011, 100101, 101001, 101100, 110001, 110100, 111000, the upper 4 bits of which indicate their binary serial number for the order in which the patterns are given. For the 16 bit patterns, two arbitrary patterns can be selected from the remaining 6 elements of the set M for the 0th bit pattern and the 15th bit pattern. The decoder for the address of the word line then only has to recognize the special cases for 0 and 15. In all other cases, the decoder outputs the upper 4 bits of the bit pattern. The marking pattern in this case also forms a (6, 4, 1) pattern for identifying the simultaneous activation of multiple word lines, which additionally enables a simple determination of the address of the word line from the associated bit pattern.

In another embodiment, the redundancy against intrusive fault attacks is increased by repeating the marking bit pattern. For example, if a 4-tuple of the bit pattern in M is considered, 272 bit patterns of length 24 can be found in this way, wherein the 4-tuple has the following property: each two 4-tuples differ in at least three of the four bit patterns in M. The bit patterns thus form a (24, 8, 3) bit pattern set. The construction method described above also provides a marking pattern of length 24 as an upper limit for a linear (12, 8, 3) code with respect to GF ₂ .

By repeating the bit mark pattern, a technique for efficiently decoding addresses can be combined with a feature for identifying multiple simultaneously activated word lines.

In summary, according to various embodiments, a memory device as shown in FIG. 5 is provided.

FIG. 5 shows a memory device 500 .

The memory device 500 has a memory cell field with columns 502 , 503 and rows 504 of memory cells 501 , bit lines 505 and word lines 506 , wherein each column 502 , 503 is associated with one bit line 505 and each row 504 is associated with one word line 506 .

The memory cell columns 502 , 503 include: a memory cell column of a first column type 502 , which is designed to store valid data; and a memory cell column of a second column type 503 , which is designed to store verification data.

The memory cells of at least a second column type 503 of the memory cell column are designed and connected to the bit line 505 so that, during a read access, a memory cell 501 of a memory cell column 502, 503 sets the bit line associated with the column 503 to a value corresponding to a logical combination of the values stored by the memory cells 501 of the column 503, which belong to the memory cell row addressed during the read access.

The memory device also has a detection circuit 507, which is designed to detect during a read access whether a bit line 505 associated with a memory cell column of the second column type 503 is set to a value that corresponds to a logical combination of values stored by memory cells of the memory cell column of the second column type 503, and the values of these memory cells belong to different memory cell rows.

In other words, according to various embodiments, memory cells with verification information are arranged in a memory cell field, wherein the memory cells of the memory cell field are designed and connected to the bit lines so that when a plurality of word lines are activated simultaneously, i.e. when memory cells of different rows are addressed simultaneously, a logical combination of the contents of the addressed memory cells connected to the bit lines is output at each bit line. Based on the previously known verification information, the detection circuit can verify whether a plurality of word lines are activated simultaneously during a read access or a write access.

The logical combination is, for example, a (bitwise) AND combination (i.e., AND relation) or a (bitwise) OR combination (i.e., OR relation). According to various embodiments, intuitively, the monotonicity of the logical relation AND or OR is used in order to achieve a change in the Hamming weight of the resulting bit pattern by the bitwise relation of the pre-calculated pattern, which is associated one-to-one with the word lines of the memory array according to one embodiment. In this case, in the case of multiple activation of word lines, the resulting Hamming weight is increased by at least the value d by the logical OR relation of the corresponding bit patterns. In the case of a logical AND relation, it is reduced by at least the value d.

The predefined verification data are stored, for example, in a secure environment in the memory cells of the memory cell column of the second column type. For example, the verification data can be stored in the memory cells of the memory cell column of the second column type in a non-volatile and possibly even non-overwritable manner during the manufacturing process.

The memory device provides a protection mechanism for electronic memory and can be used to protect different types of electronic memory, such as RAM (random access memory) memory cells, flash memory cells, RRAM (resistive random access memory) memory cells and FeRAM (ferroelectric random access memory) memory cells.

The memory device can be, for example, part of a memory having further memory components, such as an address decoder, etc. The memory can be arranged in an electronic device, for example in a chip card (having any form factor), in a control device (for example connected to a microcontroller), for example in a vehicle, etc.

Some embodiments are summarized below.

Embodiment 1 is a memory device as shown in FIG. 5 .

Embodiment 2 is a memory device according to embodiment 1, wherein the detection circuit has an alarm circuit and is designed to: if one or more bit lines respectively associated with a memory cell column of the second column type are set to the following values during a read access, the values corresponding to the logical combination of the values stored by the memory cells of the memory cell column of the second column type, and the values of these memory cells belong to different memory cell rows, then an alarm signal is output via the alarm circuit.

Embodiment 3 is the memory device according to embodiment 1 or 2, wherein the verification data has a preset bit pattern for each memory cell row, wherein the memory cells of the memory cell column of the second column type of the memory cell row are designed to store the preset bit pattern.

Embodiment 4 is a memory device according to one of embodiments 1 to 3, wherein the detection circuit is designed to detect whether the bit pattern of the bit line associated with the second column type of memory cell column is set to a derived bit pattern, and the derived bit pattern corresponds to a logical combination of bit patterns of different memory cell rows.

Embodiment 5 is a memory device according to embodiment 4, wherein the detection circuit has an alarm line and is designed to output an alarm signal via the alarm line if the resulting bit pattern corresponds to a logical combination of bit patterns of different memory cell rows.

Embodiment 6 is a memory device according to embodiment 4 or 5, wherein the preset bit patterns respectively have preset Hamming weights, and the detection circuit is designed to: verify based on the Hamming weight of the obtained bit pattern whether the obtained bit pattern corresponds to a logical combination of bit patterns of different memory cell rows.

Embodiment 7 is a memory device according to any one of embodiments 4 to 6, wherein the predetermined bit patterns of two different rows differ in positions corresponding to at least a number of predetermined redundancy values.

Embodiment 8 is the memory device according to embodiment 7, wherein the memory device has as many detection circuits as a preset redundancy value.

Embodiment 9 is the memory device according to one of embodiments 1 to 8, wherein the memory cells of the column of memory cells of the second column type are non-volatile memory cells.

Embodiment 10 is the memory device according to one of embodiments 1 to 9, wherein the memory cells of the column of memory cells of the second column type are read-only memory cells.

Embodiment 11 is the memory device according to one of embodiments 1 to 10, wherein the memory cells of the column of memory cells of the first column type are volatile memory cells.

Embodiment 12 is a memory device according to one of embodiments 1 to 11, wherein the detection circuit is configured to determine, based on information about the association of the verification data with the memory cell row, which word line or lines are activated during a read access.

It should be noted that all of the above-described embodiments can be combined with each other arbitrarily.

Although the present invention is shown and described with particular reference to specific embodiments, it will be appreciated by those skilled in the art that many changes may be made to the design and details without departing from the scope and concept of the present invention as defined by the specification. Therefore, the scope of the present invention is determined by the specification and is intended to cover all changes that fall within the literal meaning or equivalent range of the specification.

Claims (11)

1. A memory device, comprising: a memory cell field having columns and rows of memory cells, bit lines and word lines, wherein each column is associated with a bit line and each row is associated with a word line; The memory cell columns include: a first column type memory cell column, which is designed to store valid data; and a second column type memory cell column, which is designed to store preset verification data; wherein at least the memory cells of the memory cell column of the second column type are designed and connected to the bit line in such a way that the memory cells of a memory cell column of the second column type set the bit line associated with the memory cell column of the second column type during a read access to a value corresponding to a logical combination of predefined check data stored by the memory cells of the memory cell column of the second column type, which belong to a memory cell row addressed during a read access; and a detection circuit, the detection circuit being designed to detect, during a read access, whether a bit line associated with the memory cell column of the second column type is set to a value corresponding to a logical combination of preset verification data stored by memory cells of the memory cell column of the second column type, and the values of these memory cells belong to at least two different memory cell rows, The predetermined test data stored in each memory cell row of the second column type have corresponding predetermined bit patterns, which in each case have the same predetermined Hamming weight. 2. The memory device according to claim 1, The detection circuit has an alarm circuit and is designed to output an alarm signal via the alarm circuit if one or more bit lines respectively associated with a memory cell column of the second column type (i) are set to the following values during a read access, which correspond to a logical combination of preset verification data stored by the memory cells of the memory cell column of the second column type, and (ii) have different values, which belong to different memory cell rows addressed during a read access. 3. The memory device according to claim 1, The detection circuit has an alarm line and is designed to output an alarm signal via the alarm line if the resulting bit pattern corresponds to a logical combination of bit patterns of different memory cell rows. 4. The memory device according to claim 1, The predetermined bit patterns each have a predetermined Hamming weight, and the detection circuit is designed to check, based on the Hamming weights of the resulting bit patterns, whether the resulting bit pattern corresponds to a logical combination of bit patterns of different memory cell rows. 5. The memory device according to claim 1, The predetermined bit patterns of two different rows differ in at least one position which corresponds to a predetermined redundancy value. 6. The memory device according to claim 5, The memory device has as many detection circuits as a preset redundancy value. 7. The memory device according to claim 1, The memory cells of the second column type of memory cells are non-volatile memory cells. 8. The memory device according to claim 1, The memory cells of the second column type of memory cells are read-only memory cells. 9. The memory device according to claim 1, The memory cells of the first column type memory cell column are volatile memories. 10. The memory device according to claim 1, The detection circuit is designed in this case to determine, based on the information about the association of the verification data with the row of memory cells, which word line or word lines are activated during a read access. 11. The memory device according to claim 4, The detection circuit has an alarm line and is designed to output an alarm signal via the alarm line on the basis that the Hamming weight of the resulting bit pattern is greater than a Hamming weight of a different row of memory cells addressed during a read access.