CN109284243B - FPGA communication control device and method based on USB - Google Patents

Abstract

The present application provides a USB-based FPGA communication control device, including a polling arbitration module, the polling arbitration module including a controller and a plurality of buffer memories, the controller is connected to the plurality of buffer memories and a preset sending endpoint and receiving endpoint in a USB chip, and is used to schedule the uploading and/or downloading of information in the plurality of buffer memories according to the status of the plurality of buffer memories and the status of each endpoint in the USB chip, so as to realize the time-sharing utilization of the bandwidth between the FPGA and the USB chip, thereby improving the utilization rate of the bandwidth.

Description

FPGA communication control device and method based on USB

Technical Field

The present application relates to the field of electronic information, and in particular to a USB-based FPGA communication control device and method.

Background technique

Figure 1 is a schematic diagram of a Field-Programmable Gate Array (FPGA) communicating with a host computer through a Universal Serial Bus (USB) chip. The FPGA is provided with a USB module, which transmits data obtained from a data source device, such as ultrasound image data, to the USB chip through a USB physical layer interface. The host computer sends control signals to the FPGA through other transmission channels and receives response signals from the FPGA to the control signals.

Based on the above transmission method, when the data source does not generate data, there is no data transmission between the FPGA and the USB chip. Therefore, the bandwidth between the two is idle. It can be seen that the bandwidth utilization rate of the existing FPGA-based USB communication method is not high.

Summary of the invention

The present application provides a USB-based FPGA communication control device and method, aiming to solve the problem of how to improve the bandwidth utilization rate based on USB communication.

In order to achieve the above objectives, this application provides the following technical solutions:

A USB-based FPGA communication control device is provided in an FPGA, wherein the FPGA communicates with a USB chip, and the device comprises:

Polling arbitration module;

The polling arbitration module includes a controller and a plurality of buffer memories;

The controller is connected to the multiple buffer memories and the preset sending endpoints and receiving endpoints in the USB chip, and is used to schedule the uploading and/or downloading of information in the multiple buffer memories according to the status of the multiple buffer memories and the status of each endpoint in the USB chip.

Optionally, the plurality of buffer memories include:

Download control signal buffer memory, upload response signal buffer memory and upload data buffer memory;

The download control signal buffer memory is connected to the control signal sending endpoint of the USB chip through the controller, and is used for caching the control signal received by the controller from the USB chip;

The upload response signal buffer memory is connected to the response signal receiving endpoint of the USB chip through the controller, and is used for caching the response signal of the FPGA to the control signal to be sent to the USB chip through the controller;

The upload data buffer memory is connected to the data receiving endpoint of the USB chip through the controller, and is used for caching the data in the FPGA to be sent to the USB chip through the controller.

Optionally, the polling arbitration module further includes:

A register connected to the controller and corresponding to the upload data buffer memory;

The register is used to store an identification bit assigned by the controller. When the identification bit is a first value, it indicates that there is untransmitted data in the upload data buffer memory corresponding to the register.

Optionally, the number of the upload data buffer storage is multiple;

A plurality of upload data buffer memories are respectively connected to the data receiving endpoint of the USB chip through the controller, wherein the controller is used to sort the data in the plurality of upload data buffer memories according to a preset type and upload the data in the plurality of upload data buffer memories to the data receiving endpoint in sequence.

Optionally, the device further comprises:

Cache module;

The cache module includes a control signal buffer memory, a response signal buffer memory and a data buffer memory;

The control signal buffer memory is connected to the download control signal buffer memory and is used to exchange the control signal with the download control signal buffer memory;

The response signal buffer memory is connected to the upload response signal buffer memory, and is used to exchange the response signal with the upload response signal buffer memory;

The data buffer memory is connected to the upload data buffer memory and is used for exchanging data with the connected upload data buffer memory.

Optionally, when there are multiple upload data buffer memories, the number of the data buffer memories is the same as that of the upload data buffer memories, and the data buffer memories for storing the same type of data are connected to the upload data buffer memories accordingly.

Optionally, the device further comprises:

A parameter decoding module, connected to the analysis module in the FPGA through a bus, and used to receive the analysis signal sent by the analysis module, wherein the analysis module is connected to the control signal buffer memory, and used to obtain the analysis signal by receiving and analyzing the control signal in the control signal buffer memory;

The cross-clock domain conversion module is connected to the parameter decoding module and the polling arbitration module, and is used to access the register in the polling arbitration module according to the converted parsing signal after converting the clock frequency of the parsing signal into the local clock frequency.

A USB-based FPGA communication control method, wherein the FPGA communicates with a host computer via a USB chip, and the method comprises executing in any order:

When the download control signal condition is met, the control signal of the control signal sending end in the USB chip is downloaded to the download control signal buffer memory in the FPGA until the download control signal stop condition is met; wherein the download control signal condition includes: the control signal sending end is not empty and the download control signal buffer memory is not full; the download control signal stop condition includes: the control signal sending end is empty, or the download control signal buffer memory is full, or the control signal transmission is completed;

When an upload response signal condition is met, the response signal in the upload response signal buffer memory of the FPGA is uploaded to the response signal receiving end of the USB chip until an upload response signal stop condition is met; wherein the upload response signal condition includes: the response signal receiving end in the USB chip is not full and the upload response signal buffer memory in the FPGA is not empty; the upload response signal stop condition includes: the response signal receiving end is full, or the upload response signal buffer memory is empty, or the response signal transmission is completed;

When the data upload condition is met, the data in the upload data buffer memory of the FPGA is uploaded to the data receiving end of the USB chip until the data upload stop condition is met; wherein the data upload condition includes: the data receiving end in the USB chip is not full and the upload data buffer memory in the FPGA is not empty; the data upload stop condition includes: the data receiving end is full, or the upload data buffer memory is empty, or the data transmission is completed.

Optionally, the data includes multiple types of data stored in different upload data buffer memories;

When the data upload condition is met, uploading the data in the upload data buffer memory of the FPGA to the data receiving end of the USB chip until the data upload stop condition is met, includes:

According to any type sorting, it is determined whether each type of data meets the data upload condition, and the data of the type meeting the data upload condition is uploaded to the data receiving end until the data upload stop condition is met.

Optionally, also include:

In the process of uploading the data, when the data uploading stop condition is met and the data uploading is stopped, if the data is not completely uploaded, it is recorded that the data is not completely uploaded.

Optionally, when the data upload condition is met, uploading the data in the upload data buffer memory of the FPGA to the data receiving end of the USB chip until the data upload stop condition is met, the method further includes:

Upload the recorded but untransmitted data.

The USB-based FPGA communication control device described in the present application includes a polling arbitration module, which includes a controller and multiple buffer memories. The controller is connected to the multiple buffer memories and the preset sending endpoints and receiving endpoints in the USB chip, and is used to schedule the upload and/or download of information in the multiple buffer memories according to the status of the multiple buffer memories and the status of each endpoint in the USB chip, so as to realize time-sharing utilization of the bandwidth between the FPGA and the USB chip, thereby improving the utilization rate of the bandwidth.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

Figure 1 is a schematic diagram of FPGA communicating with a host computer via a USB chip;

FIG2 is a schematic diagram of the structure of a USB-based FPGA communication control device disclosed in an embodiment of the present application;

FIG3 is a flow chart of a USB-based FPGA communication control method disclosed in an embodiment of the present application.

Detailed ways

The USB-based FPGA communication control method and device disclosed in the embodiments of the present application aim to implement the scheduling transmission of different information by FPGA to fully utilize the bandwidth. In the case of transmitting multiple types of information, the integrity of the information can be further guaranteed.

The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

FIG2 is a USB-based FPGA communication control device disclosed in an embodiment of the present application, including: a polling arbitration module 21 , and optionally, a cache module 22 , a parameter decoding module 23 and a cross-clock domain conversion module 24 .

The polling arbitration module 21 is used to store information interacting with the USB chip (the information includes control signals, response signals and data) and to implement scheduling for information transmission.

Specifically, the polling arbitration module 21 includes a download control signal buffer memory 211, an upload response signal buffer memory 212, an upload data buffer memory 213, a controller 214 and a register (not shown in FIG. 2).

The controller 214 is connected to the multiple buffer memories (including 211, 212 and 213) in the polling arbitration module 21, and is connected to the preset sending endpoint and receiving endpoint in the USB chip, so as to schedule the uploading and/or downloading of information in the multiple buffer memories in the polling arbitration module 21 according to the status of the multiple buffer memories in the polling arbitration module 21 and the status of each endpoint in the USB chip. Downloading refers to receiving information (usually control signals) sent by the USB chip, and uploading refers to sending information (usually response signals and data) to the USB chip.

Further, the download control signal buffer memory 211 is connected to the control signal sending endpoint in the USB chip (in FIG. 2, the EP2 endpoint is taken as an example) through the controller 214. The upload response signal buffer memory 212 is connected to the response signal receiving endpoint in the USB chip (in FIG. 2, the EP4 endpoint is taken as an example) through the controller 214. The upload data buffer memory 213 is connected to the data receiving endpoint of the USB chip (in FIG. 2, the EP6 endpoint is taken as an example) through the controller 214.

The download control signal buffer memory 211 is used to cache the control signal received by the controller 214 from EP2 of the USB chip. The control signal is a signal sent by the host computer to control the FPGA. The upload response signal buffer memory 212 is used to cache the response signal of the FPGA to the control signal, and the response signal will be sent to EP4 of the USB chip through the controller 214.

The upload data buffer memory 213 is used to cache the data in the FPGA to be sent to the EP6 of the USB chip, and the data will be sent to the EP6 of the USB chip through the controller 214.

Further, the number of the upload data buffer memories 213 can be multiple. When there are multiple types of data to be sent, any type of data has at least one upload data buffer memory 213 for storing the data of that type. In FIG. 2 , three types of data to be uploaded are taken as an example, and therefore, three upload data buffer memories 213 are set. The three upload data buffer memories 213 are respectively connected to EP6 of the USB chip through the controller 214. The controller 214 can sort the data in the multiple upload data buffer memories 213 according to the preset types and upload the data in the multiple upload data buffer memories 213 to EP6 in sequence.

Each upload data buffer memory is correspondingly set to a register. The register is used to store a flag bit assigned by the controller 214. When the flag bit is a first value (e.g., 1), it indicates that there is uncompleted data in the upload data buffer memory corresponding to the register. When the flag bit is a second value (e.g., 0), it indicates that there is no uncompleted data in the upload data buffer memory corresponding to the register.

The cache module 22 is used to cache information (including control signals, response signals and data) interacting with other modules inside the FPGA and hardware devices that provide data (ie, data sources).

Specifically, the cache module 22 includes a control signal buffer memory 221 , a response signal buffer memory 222 and a data buffer memory 223 .

Among them, the control signal buffer memory 221 is connected to the download control signal buffer memory 211, and is used to exchange control signals with the download control signal buffer memory 211, that is, after the download control signal buffer memory 211 receives the control signal, the FPGA sends the control signal to the control signal buffer memory 221, and further, the FPGA sends the control signal in the control signal buffer memory 221 to other modules.

The response signal buffer memory 222 is connected to the upload response signal buffer memory 212, and is used to exchange response signals with the response signal buffer memory 222. That is, after the response signal buffer memory 222 receives the response signal of the FPGA to the control signal (the response signal is sent by the response module of the control signal), the FPGA sends the response signal to the upload response signal buffer memory 212.

The data buffer memory 223 is connected to the upload data buffer memory 213 and is used to exchange data with the upload data buffer memory 213. That is, the data buffer memory 223 receives data from the data source, and when it is full, the FPGA sends the data to the upload data buffer memory 213.

Specifically, when there are multiple upload data buffer memories 213 , the number of data buffer memories 223 is the same as that of the upload data buffer memories 213 , and the data buffer memories 223 and the upload data buffer memories 213 for storing the same type of data are connected to each other accordingly.

In FIG2 , the data is exemplified by ultrasound image data (represented by Img), heart rate data (represented by Ecg) and hardware status data (represented by Inf). The control signal is represented by cmd, and the response signal is represented by status. Based on the example of FIG2 , the buffer memory storing Img in the cache module 22 is connected to the buffer memory storing Img in the polling arbitration module 21, the buffer memory storing cmd in the cache module 22 is connected to the buffer memory storing cmd in the polling arbitration module 21, and the buffer memory storing status in the cache module 22 is connected to the buffer memory storing status in the polling arbitration module 21.

Typically, the FPGA includes a parsing module, which is connected to the control signal buffer memory 221 and is used to obtain a parsing signal by receiving and parsing the control signal in the control signal buffer memory 221 .

In FIG. 2 , the parameter decoding module 23 is connected to the analysis module via a bus (in FIG. 2 , bus represents a bus) and is used to receive the analysis signal sent by the analysis module.

The cross-clock domain conversion module 24 is connected to the parameter decoding module 23 and the polling arbitration module 24, and is used to convert the clock frequency of the parsed signal into the local clock frequency, and then access the register in the polling arbitration module according to the converted parsed signal. It should be noted that the register in the polling arbitration module described here may include but is not limited to the cache status register in the polling arbitration module, wherein the cache status register is used to store the status signal of each cache, and the status signal is used to indicate whether the current state of the cache is normal or abnormal.

For example, the parsing signal obtained by the parsing module parsing the control signal indicates: obtaining the current status of all the upload data buffer memories 213 in the polling arbitration module, then the cross-clock domain conversion module 24 converts the clock frequency of the parsing signal into the local clock frequency, and reads the status signal of the cache status register in the polling arbitration module 21 according to the converted parsing signal, and uses the read status signal as a response signal, which is sent by the FPGA to the response signal buffer memory 222. After it is full, it is transmitted to the upload response signal buffer memory 212, and then sent to the EP4 of the USB chip by the controller 214 of the polling arbitration module.

The specific functional implementation of the parameter decoding module 23 and the cross-clock domain conversion module 24 is the same as the prior art (i.e., the technology of FPGA transmitting a data type based on USB), and will not be repeated here. In addition to the above modules, in Figure 2, fifo represents the queue, and USB-reg represents the signal in the register used by the polling arbitration 21 module.

The following is an example of a scenario in which the FPGA obtains data from a hardware device under the control of a host computer and sends the data to the host computer through a USB chip, and the process of the controller 214 shown in FIG. 2 executing USB-based FPGA communication control is described in detail.

Assume that the FPGA is connected to a heart rate monitor to obtain heart rate data, connected to an ultrasound device to obtain ultrasound image data, and obtains status parameters of hardware devices (including a heart rate monitor and an ultrasound device). In this embodiment, the heart rate data, ultrasound image data, and status parameters are collectively referred to as data.

The FPGA stores the acquired heart rate data in a buffer memory (referred to as Ecg data cache) in the cache module 22, stores the acquired ultrasound image data in another buffer memory (referred to as Img data cache) in the cache module 22, and stores the status parameters in another buffer memory (referred to as Status data cache) in the cache module 22.

FIG3 is a flow chart of a USB-based FPGA communication control method disclosed in an embodiment of the present application, which is executed by the controller 214 and aims to schedule transmission of control signals, response signals and data in a certain polling order. FIG3 includes the following steps:

S301: Determine whether the download control signal condition is met: that is, determine whether the EP2 endpoint is not empty and whether the download control signal buffer memory 211 is not full. If so, execute S302, otherwise, execute S304.

S302: Download the control signal of the EP2 endpoint to the download control signal buffer memory 211.

S303: During the process of downloading the control signal, determine whether the download control signal stop condition is met: that is, determine whether the control signal transmission is completed, or whether the EP2 endpoint is empty, or whether the download control signal buffer memory 211 is full. If the judgment result of any one of the conditions is yes, execute S304, otherwise, execute S302.

S304: Determine whether the upload response signal condition is met: that is, determine whether the EP4 endpoint is not full and whether the upload response signal buffer memory 212 is not empty. If yes, execute S305; otherwise, execute S307.

S305: Upload the response signal in the upload response signal buffer memory 212 to the EP4 endpoint.

S306: During the process of uploading the response signal, determine whether the upload response signal stop condition is met: that is, determine whether the response signal transmission is completed, or whether the EP4 endpoint is full, or whether the upload response signal buffer memory 212 is empty. If the judgment result of any one of the conditions is yes, execute S307, otherwise, execute S305.

S307: Determine whether there is any data that has not been transmitted. If not, execute S308; if yes, execute S321.

Specifically, if the controller 214 does not complete the data transmission during the last data transmission, the type of data that is not completed can be recorded, and the controller 214 determines that the last data transmission is not completed based on the record. Specifically, the identifier of the cache of the data that is not completed is recorded. For example, assuming that the cache for storing ultrasound image data in the polling arbitration module 21 is numbered 1, the cache for storing status data is numbered 2, and the cache for storing heart rate data is numbered 3, then if the ultrasound image data is not completely transmitted during the last data transmission, the controller 214 records the number 3 of the cache for storing heart rate data. Alternatively, as described above, a register is set for each cache for storing data. If the data in any cache is not completely transmitted during a data transmission process, the flag bit in the register of the cache is set to 1. The controller 214 determines whether there is uncompleted data based on the flag bits in the registers corresponding to each cache.

S308: Determine whether the data upload condition is met: that is, determine whether the EP6 endpoint is not full and whether the upload data buffer memory 213 storing ultrasound image data is not empty. If so, execute S309, otherwise, execute S312.

S309: Upload the ultrasound image data in the upload data buffer memory 213 storing the ultrasound image data to the EP6 endpoint.

S310: During the process of uploading ultrasound image data, determine whether the data uploading stop condition is met: that is, determine whether the EP6 endpoint is full, or whether the cache storing ultrasound image data is empty. If the judgment result of any condition is yes, execute S311, otherwise, execute S309.

S311: Determine whether the ultrasound image data transmission is completed. If yes, execute S312; otherwise, execute S320.

S312: Determine whether the EP6 endpoint is not full and whether the cache storing the status data is not empty. If so, execute S313; otherwise, execute S316.

S313: Upload the status data in the upload data buffer memory 213 storing the status data to the EP6 endpoint.

S314: During the process of uploading the status data, determine whether the EP6 endpoint is full or whether the status data cache is empty. If the determination result of any one of the conditions is yes, execute S315; otherwise, execute S313.

S315: Determine whether the current status data transmission is completed, if so, execute S316, otherwise, execute S320.

S316: Determine whether the EP6 endpoint is not full and whether the cache storing the heart rate data is not empty. If so, execute S317; otherwise, execute S301.

S317: Upload the heart rate data in the upload data buffer memory 213 storing the heart rate data to the EP6 endpoint.

S318: During the process of uploading the heart rate data, determine whether the EP6 endpoint is full or whether the cache of the heart rate data is empty. If the judgment result of any one of the conditions is yes, execute S319; otherwise, execute S317.

S319: Determine whether the current heart rate data transmission is completed, if so, execute S301, otherwise, execute S320.

S320: Record the data that has not been completely transmitted.

The specific recording method is as described above and will not be repeated here.

S321: Transmit the data that was not completed last time.

After completing the transmission of the data that was not completed last time, the controller 214 returns to execute S308 to perform the current data transmission.

As can be seen from the process shown in FIG3 , the polling arbitration module polls the status of the local cache and the endpoint of the USB chip in the order of the control signal, the response signal, and the data, and transmits information when the conditions on both sides are met, so that the transmission of multiple types of information can be taken into account. Furthermore, for multiple types of data, polling transmission can also be performed in a preset order, so the transmission of multiple types of data can be achieved by using the bandwidth in a time-sharing manner. Compared with the existing method of using a separate FPGA chip to transmit data, one FPGA chip can take into account the transmission of multiple types of data, that is, multiple types of data can be transmitted in a time-sharing manner using the bandwidth allocated to one FPGA, which can improve the utilization rate of bandwidth.

Furthermore, the polling order is set according to the dimension of the endpoint setting of the USB chip, so it is compatible with the USB transmission protocol and has high hardware compatibility.

Generally, compared with status parameters, the transmission volume of data (such as ultrasound image data) is larger. Therefore, if there is uncompleted data last time, the uncompleted data will be transmitted first. Therefore, the integrity and correctness of the data can be further guaranteed without causing data loss and errors due to the round-robin mechanism.

In this embodiment, the setting principle of the above judgment conditions is: the receiver of the information is not full and the sender of the information is not empty. Therefore, it can not only ensure that the information is lost due to the receiver being full, but also poll the next information in time, thereby improving the transmission efficiency of information.

It should be noted that if the host computer freezes and causes FPGA information blocking, the information will be stored in the internal queue of the FPGA first. When the internal queue is full, if the host computer is still in a freeze state, the information will be lost. Therefore, the following bandwidth relationship can be set: host computer bandwidth>USB bandwidth>FPGA bandwidth.

It should be noted that the polling order described in the process shown in FIG3: control signal, response signal and data is only an example and is not a limitation of the present application. Other preset orders can also be used for polling. Similarly, the polling order of ultrasound data image, status data and heart rate data is not a limitation.

It should be noted that in the process shown in Figure 3, the download control signal memory, upload response signal memory and upload data memory are not limited to the structure shown in Figure 2, and can also be existing memories in the FPGA, as long as they are only used to store data of the corresponding type. For example, the existing memory in the FPGA can be used only to store control signals, that is, a download control signal memory.

If the functions described in the method of the embodiment of the present application are implemented in the form of software functional units and sold or used as independent products, they can be stored in a storage medium readable by a computing device. Based on this understanding, the part of the embodiment of the present application that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions to enable a computing device (which can be a personal computer, server, mobile computing device or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims (9)

1. A USB-based FPGA communication control device, arranged in an FPGA, wherein the FPGA communicates with a USB chip, wherein the device comprises: Polling arbitration module; The polling arbitration module includes a controller and a plurality of buffer memories; The controller is connected to the multiple buffer memories and the preset sending endpoint and receiving endpoint in the USB chip, and is used to schedule the uploading and/or downloading of information in the multiple buffer memories according to the status of the multiple buffer memories and the status of each endpoint in the USB chip; The polling arbitration module further includes: a register connected to the controller; The device further comprises: a cache module, wherein the cache module comprises a control signal buffer memory; The device also includes: A parameter decoding module, connected to the analysis module in the FPGA through a bus, and used to receive the analysis signal sent by the analysis module, wherein the analysis module is connected to the control signal buffer memory, and used to obtain the analysis signal by receiving and analyzing the control signal in the control signal buffer memory; The cross-clock domain conversion module is connected to the parameter decoding module and the polling arbitration module, and is used to access the register in the polling arbitration module according to the converted parsing signal after converting the clock frequency of the parsing signal into the local clock frequency. 2. The device according to claim 1, wherein the plurality of buffer memories comprises: Download control signal buffer memory, upload response signal buffer memory and upload data buffer memory; The download control signal buffer memory is connected to the control signal sending endpoint of the USB chip through the controller, and is used for caching the control signal received by the controller from the USB chip; The upload response signal buffer memory is connected to the response signal receiving endpoint of the USB chip through the controller, and is used for caching the response signal of the FPGA to the control signal to be sent to the USB chip through the controller; The upload data buffer memory is connected to the data receiving endpoint of the USB chip through the controller, and is used for caching the data in the FPGA to be sent to the USB chip through the controller. 3. The device according to claim 2, characterized in that the register in the polling arbitration module corresponds to the upload data buffer memory; The register is used to store an identification bit assigned by the controller, and when the identification bit is a first value, it indicates that there is untransmitted data in the upload data buffer memory corresponding to the register. 4. The device according to any one of claims 2 to 3, characterized in that the number of the upload data buffer memory is multiple; A plurality of upload data buffer memories are respectively connected to the data receiving endpoint of the USB chip through the controller, wherein the controller is used to sort the data in the plurality of upload data buffer memories according to a preset type and upload the data in the plurality of upload data buffer memories to the data receiving endpoint in sequence. 5. The device according to claim 2, characterized in that The cache module includes a response signal buffer memory and a data buffer memory; The control signal buffer memory is connected to the download control signal buffer memory and is used to exchange the control signal with the download control signal buffer memory; The response signal buffer memory is connected to the upload response signal buffer memory, and is used to exchange the response signal with the upload response signal buffer memory; The data buffer memory is connected to the upload data buffer memory and is used for exchanging data with the connected upload data buffer memory. 6. The device according to claim 5 is characterized in that, when the number of the upload data buffer memories is multiple, the number of the data buffer memories is the same as that of the upload data buffer memories, and the data buffer memories used to store the same type of data are correspondingly connected to the upload data buffer memories. 7. A USB-based FPGA communication control method, wherein the FPGA communicates with a host computer via a USB chip, wherein the method comprises executing in any order: When the download control signal condition is met, the control signal of the control signal sending end in the USB chip is downloaded to the download control signal buffer memory in the FPGA until the download control signal stop condition is met; wherein the download control signal condition includes: the control signal sending end is not empty and the download control signal buffer memory is not full; the download control signal stop condition includes: the control signal sending end is empty, or the download control signal buffer memory is full, or the control signal transmission is completed; When an upload response signal condition is met, the response signal in the upload response signal buffer memory of the FPGA is uploaded to the response signal receiving end of the USB chip until an upload response signal stop condition is met; wherein the upload response signal condition includes: the response signal receiving end in the USB chip is not full and the upload response signal buffer memory in the FPGA is not empty; the upload response signal stop condition includes: the response signal receiving end is full, or the upload response signal buffer memory is empty, or the response signal transmission is completed; When the data upload condition is met, the data in the upload data buffer memory of the FPGA is uploaded to the data receiving end of the USB chip until the data upload stop condition is met; wherein the data upload condition includes: the data receiving end in the USB chip is not full and the upload data buffer memory in the FPGA is not empty; the data upload stop condition includes: the data receiving end is full, or the upload data buffer memory is empty, or the data transmission is completed; wherein the data includes multiple types of data stored in different upload data buffer memories; When the data upload condition is met, uploading the data in the upload data buffer memory of the FPGA to the data receiving end of the USB chip until the data upload stop condition is met, includes: According to any type sorting, it is determined whether each type of data meets the data upload condition, and the data of the type meeting the data upload condition is uploaded to the data receiving end until the data upload stop condition is met. 8. The method according to claim 7, further comprising: In the process of uploading the data, when the data uploading stop condition is met and the data uploading is stopped, if the data is not completely transmitted, it is recorded that the data is not completely transmitted. 9. The method according to claim 8, characterized in that, when the data upload condition is met, uploading the data in the upload data buffer memory of the FPGA to the data receiving end of the USB chip until the data upload stop condition is met, the method further comprises: Upload the recorded but untransmitted data.