CN109273426A - Package structure and method for manufacturing the same - Google Patents

Abstract

The invention discloses a packaging structure and a manufacturing method thereof. The composite layer of the non-conductor inorganic material and the organic material is configured on the metal layer. The sealant is bonded on the composite layer of the non-conductor inorganic material and the organic material. The chip is embedded in the molding compound and has a plurality of electrode pads. The circuit layer structure is formed on the sealing compound and the wafer. The circuit layer structure comprises at least one dielectric layer and at least one circuit layer, wherein the dielectric layer is provided with a plurality of conductive blind holes, the circuit layer is positioned on the dielectric layer, and the circuit layer at the bottommost layer is electrically connected with the electrode pad through the conductive blind holes. The insulating protective layer is formed on the circuit layer structure. The insulating protection layer is provided with a plurality of openings, so that part of the surface of the circuit layer structure is exposed in the openings. The invention can strengthen the whole structure strength to prevent the generation of warping phenomenon.

Description

Package structure and manufacturing method thereof

Technical field

The present invention relates to a package structure and a method of fabricating the same.

Background technique

With the evolution of semiconductor packaging technology, in addition to the conventional wire bonding semiconductor packaging technology, semiconductor devices have been developed in different package types, such as directly embedded in a package substrate. And electrically integrated semiconductor wafers with integrated circuits to reduce the overall volume and enhance electrical functions.

In order to meet the trend of shortening the length of the wire, reducing the thickness of the overall structure, and responding to the trend of high frequency and miniaturization, a method of processing the embedded wafer substrate on a coreless carrier plate has been developed. However, since the carrier plate without the core layer lacks a rigid core plate for supporting, resulting in insufficient strength, the overall structure is prone to warpage.

Summary of the invention

In view of the above, it is an object of the present invention to provide a package structure and a method of manufacturing the same that can enhance the overall structural strength to prevent warpage.

In order to achieve the above object, according to an embodiment of the present invention, a package structure includes a metal layer, a composite layer of a non-conducting inorganic material and an organic material, a sealant, a wafer, a wiring layer structure, and an insulating protective layer. A composite layer of a non-conducting inorganic material and an organic material is disposed on the metal layer. The sealant is bonded to the composite layer of the non-conducting inorganic material and the organic material. The wafer is embedded in the sealant, and the wafer has a plurality of electrode pads, and the electrode pads are exposed to the sealant. The wiring layer structure is formed on the sealant and the wafer. The circuit layer structure comprises at least one dielectric layer and at least one circuit layer, the dielectric layer has a plurality of conductive blind holes, the circuit layer is located on the dielectric layer and extends into the conductive blind hole, and the bottommost circuit layer passes through the conductive blind The holes are electrically connected to the electrode pads. An insulating protective layer is formed on the wiring layer structure. The insulating protective layer has a plurality of openings such that a portion of the surface of the wiring layer structure is exposed in the opening.

In one or more embodiments of the present invention, the wafer has a bottom surface of the wafer, and the bottom surface of the wafer is exposed to the sealant.

In one or more embodiments of the present invention, the material of the composite layer of the non-conducting inorganic material and the organic material includes a composite material composed of a ceramic material and a polymer material.

In one or more embodiments of the present invention, the ceramic material includes zirconia, alumina, silicon nitride, silicon carbide, silicon oxide or a combination thereof, and the polymer material includes an epoxy resin and a polyimide. , liquid crystal polymer, methacrylate type resin, vinyl phenyl type resin, allyl type resin, polyacrylate type resin, polyether type resin, polyolefin type resin, polyamine type resin, polysiloxane type Resin or a combination of the foregoing.

In one or more embodiments of the present invention, the composite layer of the non-conducting inorganic material and the organic material is an imitation nacre.

According to another embodiment of the present invention, a method of fabricating a package structure includes the following steps. First, a carrier plate is provided, the carrier plate comprising a support layer having opposite surfaces, a release layer disposed on both surfaces, and a metal layer disposed on the release layer. Next, a composite layer of a non-conducting inorganic material and an organic material is disposed on the metal layer. Then, the embedded wafer substrate is combined on the composite layer of the non-conducting inorganic material and the organic material, wherein the embedded wafer substrate comprises a plurality of wafers and a sealant, the wafer is embedded in the sealant, and the wafer has a plurality of electrode pads and electrodes The mat is exposed to the sealant. Next, a wiring layer structure is formed on the embedded wafer substrate, wherein the wiring layer structure includes at least one dielectric layer and at least one wiring layer, wherein the dielectric layer has a plurality of conductive blind holes, and the circuit layer is located on the dielectric layer and extends To the conductive vias, and the bottommost circuit layer is electrically connected to the electrode pads through the conductive vias. Then, an insulating protective layer is formed on the wiring layer structure, wherein the insulating protective layer has a plurality of openings such that a part of the surface of the wiring layer structure is exposed in the opening. Finally, the support layer and the lift-off layer are removed to form two package substrates, and the package substrate is diced to obtain a plurality of package structures.

In one or more embodiments of the present invention, the sealant has a seal bottom surface, and the wafer has a wafer bottom surface, and the step of combining the embedded wafer substrates on the composite layer of each non-conductor inorganic material and the organic material includes The following steps. Grinding the bottom surface of the encapsulant to expose the bottom surface of the wafer to form the embedded embedded wafer substrate; and combining the polished embedded wafer substrate on the composite layer of the non-conducting inorganic material and the organic material.

In one or more embodiments of the present invention, the material of the composite layer of the non-conducting inorganic material and the organic material includes a composite material composed of a ceramic material and a polymer material.

In one or more embodiments of the present invention, the ceramic material includes zirconia, alumina, silicon nitride, silicon carbide, silicon oxide or a combination thereof, and the polymer material includes an epoxy resin and a polyimide. , liquid crystal polymer, methacrylate type resin, vinyl phenyl type resin, allyl type resin, polyacrylate type resin, polyether type resin, polyolefin type resin, polyamine type resin, polysiloxane type Resin or a combination of the foregoing.

In one or more embodiments of the present invention, the composite layer of the non-conducting inorganic material and the organic material is an imitation nacre.

In summary, the package structure and the manufacturing method thereof of the present invention form a package substrate on a composite layer of a non-conducting inorganic material and an organic material, that is, a composite layer of a non-conducting inorganic material and an organic material can be regarded as strengthening. The layer has a higher hardness than the general dielectric layer and the encapsulating material. Therefore, the package structure and the manufacturing method thereof of the present invention can strengthen the overall structural strength by a composite layer of a non-conducting inorganic material and an organic material to prevent warpage of the carrier sheet, thereby not only improving the process qualification rate but also improving the process qualification rate. Improve the reliability of the package structure.

The above description is only for explaining the problems to be solved by the present invention, the technical means for solving the problems, the effects thereof, and the like, and the specific details of the present invention will be described in detail in the following embodiments and related drawings.

DRAWINGS

The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood.

1A to 1G are cross-sectional views showing respective steps of a method of manufacturing a package structure according to an embodiment of the present invention.

2A-2B are cross-sectional views showing partial steps of a method of fabricating a package structure according to another embodiment of the present invention.

3 is a cross-sectional view showing a package structure obtained according to the manufacturing method of FIGS. 2A to 2B.

Detailed ways

The embodiments of the present invention are disclosed in the following drawings, and for the sake of clarity, the details of the invention are described in the following description. However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not necessary. In addition, some of the well-known structures and elements are shown in the drawings in a simplified schematic representation.

1A to 1G are cross-sectional views showing respective steps of a method of manufacturing a package structure 18 according to an embodiment of the present invention. First, as shown in FIG. 1A, a carrier board 10 is provided. The carrier board 10 includes a support layer 100 having opposite surfaces 100A, 100B, a release layer 102 disposed on the opposite surfaces 100A, 100B, and a release layer 102. Metal layer 104. The material of the support layer 100 may be, for example, an organic polymeric material such as a bimaleimide triazine (BT), and the support layer 100 may also be integrated with the opposite surfaces 100A and 100B. A copper foil substrate (CCL) (not shown) of an electrical material (for example, a prepreg). The release layer 102 can be a release film, or other techniques can be used to provide the release layer 102, such as a copper foil bonded release layer provided by companies such as Mitsui, Nippon-Denk, Furukawa, or Olin. The thickness of the metal layer 104 may be selected from the range of 1 micrometer to 10 micrometers, and the material of the metal layer 104 may be copper.

In some embodiments, another metal layer may be included between the opposite surfaces 100A, 100B of the support layer 100 and the release layer 102, and the thickness of the other metal layer may be selected from the range of 5 micrometers to 40 micrometers. The materials may be the same or different from the metal layer 104, such as copper.

Next, as shown in FIG. 1B, a composite layer 106 of a non-conducting inorganic material and an organic material is disposed on the metal layer 104.

Further, the material of the composite layer 106 of the non-conductive inorganic material and the organic material of the embodiment is, for example, a composite material composed of a ceramic material and a polymer material, wherein the ceramic material includes zirconia, aluminum oxide, silicon nitride, Silicon carbide, silicon oxide or a combination of the foregoing, and the polymer material includes an epoxy resin, a polyimide, a liquid crystal polymer, a methacrylate type resin, a vinyl phenyl type resin, an allyl type resin, a polyacrylate type A resin, a polyether resin, a polyolefin resin, a polyamine resin, a silicone resin, or a combination thereof. The ceramic material may be a ceramic layer or a ceramic powder, but the ceramic material of the embodiment is not limited thereto.

In the ceramic powder embodiment, the method for preparing the composite layer 106 of the non-conducting inorganic material and the organic material can be impregnated into the ceramic powder by a vacuum impregnation technique to prepare a composite composed of the ceramic powder and the polymer material. A composite layer 106 of a non-conducting inorganic material and an organic material composed of a material. In the embodiment in which the polymer material is, for example, a photosensitive resin composition of an epoxy resin or an imide resin, the non-conductive inorganic material and the organic material are irradiated by ultraviolet light and heating, for example, by thermocompression bonding or vacuum impregnation. The composite layer 106 is disposed on the metal layer 104.

In the embodiment of the ceramic layer sheet, the method for preparing the composite layer 106 of the non-conducting inorganic material and the organic material can be impregnated into the ceramic layer sheet by vacuum impregnation technology to prepare the ceramic layer sheet and the polymer material. A composite layer 106 of a non-conducting inorganic material and an organic material composed of a composite material composed of a composite material. However, the method for manufacturing the composite layer 106 of the non-conducting inorganic material and the organic material of the present embodiment is not limited thereto, and other methods for forming a composite material between the polymer material and the ceramic material may be employed. In the ceramic layer embodiment, in more detail, the composite layer 106 of the non-conducting inorganic material and the organic material comprises a composite composition of an organic substance and an inorganic substance (for example, a composite composition of a polymer material and a ceramic layer), and is based on an organic substance to the inorganic substance. The adhesion of the object, the ceramic layer of the composite layer 106 of the non-conducting inorganic material and the organic material has a micro-layered structure arranged in a sheet shape, a brick shape or a combination thereof, and the arrangement suppresses the conduction of the lateral rupture force, thereby significantly increasing Its hardness. In this way, the material is strong and elastic, which can improve the ceramic strength and improve the ceramic brittleness, while having excellent toughness. The composite layer 106 of non-conducting inorganic material and organic material may be an imitation nacreous layer.

Here, the Young's modulus of the composite layer 106 of the non-conducting inorganic material and the organic material is, for example, between 20 GPa and 100 GPa. The composite layer 106 of the non-conducting inorganic material and the organic material of the present embodiment has a pole compared to the well-known dielectric layer (having a Young's modulus of not more than 10 GPa) and the encapsulating material (having a Young's modulus of not more than 20 GPa). Good hardness can effectively strengthen the structural strength of the package structure.

Then, as shown in FIG. 1C, a buried wafer substrate 12 is embedded on the composite layer 106 of non-conducting inorganic material and organic material, wherein the embedded wafer substrate 12 includes a plurality of wafers 120 and a sealant 122, and the wafers 120 are embedded in In the sealant 122, each of the wafers 120 has a plurality of electrode pads 120P, and the electrode pads 120P are exposed to the sealant 122.

The method of embedding the wafer substrate 12 on the composite layer 106 of the non-conducting inorganic material and the organic material can be performed, for example, by an adhesive layer (not shown). Specifically, the adhesive layer may be adhered to the substrate bottom surface 12S of the embedded wafer substrate 12, and the embedded wafer substrate 12 may be bonded to the composite layer 106 of the non-conductive inorganic material and the organic material. The above adhesive layer may include a heat dissipating agent having high heat dissipation or high temperature resistance, but the invention is not limited thereto.

Next, as shown in FIGS. 1D-1E, a wiring layer structure 14 is formed on the embedded wafer substrate 12, wherein each wiring layer structure 14 includes at least one dielectric layer and at least one wiring layer, each dielectric layer having a plurality of conductive layers The blind holes are respectively disposed on the respective dielectric layers and extend into the conductive blind holes, and the bottommost circuit layer is electrically connected to the electrode pads 120P through the conductive blind holes.

The minimum unit constituting the circuit layer structure 14 is at least one dielectric layer and at least one circuit layer. Those skilled in the art can flexibly select the dielectric layer and the number of layers of the circuit layer according to actual needs. In the present embodiment, the circuit layer structure 14 includes two dielectric layers (the first dielectric layer 108 and the second dielectric layer 208) and two circuit layers (the first circuit layer 110 and the second circuit layer 210). ) as an example.

First, as shown in FIG. 1D, a first dielectric layer 108 is formed on the embedded wafer substrate 12, wherein each of the first dielectric layers 108 has a plurality of first conductive vias 108H. The material of the first dielectric layer 108 may comprise a resin and a glass fiber. The resin may be a phenol resin, an epoxy resin, a polyimide resin or a polytetrafluoroethylene. Alternatively, the material of the first dielectric layer 108 may also include a Photoimageable Dielectric (PID). The method of forming the first dielectric layer 108 may be, for example, lamination. The method for forming the first conductive via hole 108H includes, but is not limited to, laser ablation of the first dielectric layer 108, or the material of the first dielectric layer 108 is selected from a photosensitive dielectric material to form a first exposure and development. Conductive blind hole 108H.

Please continue to refer to Figure 1D. Then, a first circuit layer 110 is formed on the first dielectric layer 108, and the first circuit layer 110 extends into the first conductive via hole 108H, so that the first circuit layer 110 is electrically connected to the first conductive via hole 108H. Electrode pad 120P. For example, the first circuit layer 110 can be formed by first forming a photoresist layer (not shown) on the first dielectric layer 108, for example, a dry film, and the photoresist layer is patterned to expose a portion through a lithography process. A dielectric layer 108 is then formed by a plating process and a photoresist removal process to form the first wiring layer 110. The material of the first wiring layer 110 may be, for example, copper.

In some embodiments, a seed layer may be formed on the first dielectric layer 108 prior to forming the first wiring layer 110. The seed layer may be a single layer structure or a multilayer structure composed of sublayers of different materials, such as a metal layer comprising a titanium layer and a copper layer on the titanium layer. Methods of forming the seed layer include, but are not limited to, physical means such as sputtering of titanium copper, or chemical means such as palladium copper plus electroplated copper.

Next, as shown in FIG. 1E, a second dielectric layer 208 is formed on the first dielectric layer 108 and the first wiring layer 110, wherein the second dielectric layer 208 has a plurality of second conductive vias 208H. Then, a second circuit layer 210 is formed on the second dielectric layer 208, and the second circuit layer 210 extends into the second conductive via 208H, so that the second circuit layer 210 is electrically connected to the second conductive via 208H. The first circuit layer 110.

Thus, the wiring layer structure 14 is formed on the embedded wafer substrate 12, wherein the wiring layer structure 14 includes a first dielectric layer 108, a first wiring layer 110, a second dielectric layer 208, and a second wiring layer 210. The first dielectric layer 108 has a plurality of first conductive vias 108H. The first circuit layer 110 is electrically connected to the electrode pads 120P through the first conductive vias 108H. The second dielectric layer 208 has a plurality of second conductive vias 208H. The second circuit layer 210 is electrically connected to the first circuit layer 110 through the second conductive vias 208H. That is, the circuit layer structure 14 includes at least one dielectric layer (the first dielectric layer 108, the second dielectric layer 208) and at least one circuit layer (the first circuit layer 110 and the second circuit layer 210), each of which The electric layer has a plurality of conductive blind holes (a first conductive blind via 108H and a second conductive via via 208H), and each circuit layer is respectively located on each dielectric layer and extends into the conductive blind via and the bottommost trace layer ( The first circuit layer 110) is electrically connected to the electrode pad 120P through a conductive via hole (first conductive via hole 108H).

The forming method and material of the second dielectric layer 208, the second circuit layer 210, and the second conductive via 208H may be respectively associated with the first dielectric layer 108, the first wiring layer 110, and the first conductive blind via 108H, respectively. The forming method and material are the same and will not be described here. In addition, before the formation of the second circuit layer 210, the foregoing seed layer may be formed on the second dielectric layer 208, and details are not described herein.

Please continue to refer to Figure 1E. Then, an insulating protective layer 112 is formed on the wiring layer structure 14, wherein each of the insulating protective layers 112 has a plurality of openings 112O such that a part of the surface of the wiring layer structure 14 is exposed in the opening 112O. Specifically, as shown in FIG. 1E, a portion of the surface of the second wiring layer 210 of the outermost layer of the wiring layer structure 14 is exposed in the opening 112O.

The material of the insulating protective layer 112 may be a solder resist material or a resin material such as an epoxy resin. Alternatively, the material of the insulating protective layer 112 may be the same as the material of the first dielectric layer 108 or the second dielectric layer 208. The method of forming the insulating protective layer 112 may be a method of lamination, printing, or coating.

Next, as shown in FIG. 1F, the support layer 100 and the lift-off layer 102 are removed to form two package substrates 16. Therefore, the warping phenomenon is easily caused by the asymmetry of the structure as compared with the conventional one-sided fabrication. In the present embodiment, the two processes of the upper and lower symmetry are formed by performing the same process on the opposite surfaces 100A, 100B of the support layer 100 at the same time. 16, can avoid the warping phenomenon at both ends of the support layer 100, in order to improve the reliability of the overall package structure.

Finally, as shown in FIG. 1G, the package substrate 16 is diced to obtain a plurality of package structures 18. Therefore, if each of the package substrates 16 can generate N package structures 18, the two package substrates 16 formed by the manufacturing methods of FIGS. 1A to 1F can generate 2N package structures 18, thereby effectively improving The quantity of product produced.

Thus, the package structure 18 of the present embodiment is completed, which includes a metal layer 104, a composite layer 106 of a non-conducting inorganic material and an organic material, a sealant 122, a wafer 120, a wiring layer structure 14, and an insulating protective layer 112. A composite layer 106 of a non-conducting inorganic material and an organic material is disposed on the metal layer 104. The sealant 122 is bonded to the composite layer 106 of non-conducting inorganic material and organic material. The wafer 120 is embedded in the sealant 122, and the wafer 120 has a plurality of electrode pads 120P, and the electrode pads 120P are exposed to the sealant 122. The wiring layer structure 14 is formed on the encapsulant 122 and the wafer 120. The circuit layer structure 14 includes at least one dielectric layer and at least one circuit layer. The dielectric layer has a plurality of conductive blind vias, the circuit layer is on the dielectric layer and extends into the conductive blind vias, and the bottommost trace layer is electrically conductive. The blind via is electrically connected to the electrode pad 120P. An insulating protective layer 112 is formed on the wiring layer structure 14. The insulating protective layer 112 has a plurality of openings 112O such that a portion of the surface of the wiring layer structure 14 is exposed in the opening 112O.

The package structure 18 of the present invention and the manufacturing method thereof are formed on the composite layer 106 of a non-conducting inorganic material and an organic material, that is, the composite layer 106 of the non-conducting inorganic material and the organic material can be regarded as a strengthening layer. It has higher hardness than the general dielectric layer and packaging material. Therefore, the package structure 18 of the present invention and the manufacturing method thereof can strengthen the overall structural strength by the composite layer 106 of the non-conducting inorganic material and the organic material, thereby preventing the warpage of the carrier plate, thereby not only improving the process qualification, but also The reliability of the package structure 18 can be improved.

Moreover, since the bottom of the package structure 18 has the metal layer 104, the thermal energy generated by the wafer 120 can be removed by conduction of the metal layer 104, thereby achieving the effect of heat dissipation.

2A to 2B are cross-sectional views showing partial steps of a method of manufacturing the package structure 18A according to another embodiment of the present invention. 3 is a cross-sectional view of a package structure 18A obtained according to the manufacturing method of FIGS. 2A to 2B. The manufacturing method of the package structure 18A of the present embodiment is similar to the manufacturing method of the package structure 18 described above, and the difference between the two is that the step of combining the embedded wafer substrate 12 on the composite layer 106 of the non-conducting inorganic material and the organic material further includes Sub-step of grinding the seal bottom surface 122S to expose the wafer bottom surface 120S.

Please refer to FIG. 2A and FIG. 1C at the same time. The difference between the embodiment and the step shown in FIG. 1C is that before the embedded wafer substrate 12 is bonded to the composite layer 106 of the non-conductive inorganic material and the organic material, the seal bottom surface 122S is polished to expose the wafer bottom surface 120S to The embedded embedded wafer substrate 12A is formed. The method of grinding the seal bottom surface 122S may be, for example, Chemical-Mechanical Polishing (CMP).

Next, as shown in FIG. 2B, the ground embedded wafer substrate 12A is bonded to the composite layer 106 of the non-conductive inorganic material and the organic material. That is, when the ground embedded wafer substrate 12A is bonded to the composite layer 106 of the non-conductive inorganic material and the organic material, the wafer bottom surface 120S is exposed to the sealant 122.

The method of bonding the embedded embedded wafer substrate 12A on the composite layer 106 of the non-conducting inorganic material and the organic material can be performed, for example, by an adhesive layer (not shown). The specific steps can be referred to the previous embodiment. No longer.

Then, the steps of FIG. 1D to FIG. 1G are continued to obtain the package structure 18A as shown in FIG. In the present embodiment, since the wafer bottom surface 120S is exposed to the sealant 122, not only the metal layer 104 can more effectively conduct the heat energy generated by the wafer 120, but also the heat dissipation effect is further improved, and the thickness of the package structure 18A is also reduced. Conducive to the thin design of the product.

From the above detailed description of the specific embodiments of the present invention, it can be clearly seen that the package structure and the manufacturing method thereof of the present invention form a package substrate on a composite layer of a non-conducting inorganic material and an organic material, that is, The composite layer of the non-conducting inorganic material and the organic material can be regarded as a strengthening layer, which has higher hardness than the general dielectric layer and the packaging material. Therefore, the package structure and the manufacturing method thereof of the present invention can strengthen the overall structural strength by a composite layer of a non-conducting inorganic material and an organic material to prevent warpage of the carrier sheet, thereby not only improving the process qualification rate but also improving the process qualification rate. Improve the reliability of the package structure.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any person skilled in the art can make various changes and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the claims.

Claims (10)

1. a kind of encapsulating structure characterized by comprising

Metal layer；

The composite layer of non-conductor inorganic material and organic material is configured on the metal layer；

Sealing is incorporated on the composite layer of the non-conductor inorganic material and organic material；

Chip is embedded into the sealing, and the chip has multiple electrode pads, and the multiple electronic pads expose to the envelope Glue；

Line layer structure is formed on the sealing and the chip, wherein the line layer structure includes at least one Jie Electric layer and at least one line layer, the dielectric layer have multiple conductive blind holes, and the line layer is located on the dielectric layer, And it extends in the multiple conductive blind hole, and the line layer of the bottom is electrically connected at by the multiple conductive blind hole The multiple electronic pads；And

Insulating protective layer is formed in the line layer structure, wherein the insulating protective layer has multiple openings, so that described The part of the surface of line layer structure exposes in the multiple opening.

2. encapsulating structure as described in claim 1, which is characterized in that the chip has chip bottom surface, the chip bottom surface Expose to the sealing.

3. the encapsulating structure as described in any one of claims 1 to 2, which is characterized in that the non-conductor inorganic material with have The material of the composite layer of machine material includes the composite material as composed by ceramic material and high molecular material.

4. encapsulating structure as claimed in claim 3, which is characterized in that the ceramic material includes zirconium oxide, aluminium oxide, nitridation Silicon, silicon carbide, silica or combination above-mentioned, and the high molecular material includes epoxy resin, polyimide, polymerizable mesogenic Object, methacrylate type resin, Ethenylbenzene fundamental mode resin, allyl type resin, polyacrylate resin, polyether-type tree Rouge, polyolefin-type resin, polyamine type resin, polysiloxane type resin or combination above-mentioned.

5. encapsulating structure as described in claim 1, which is characterized in that the non-conductor inorganic material and organic material it is compound Layer is imitative nacre.

6. a kind of manufacturing method of encapsulating structure characterized by comprising

Loading plate is provided, the loading plate includes with the support layer on two surfaces relatively, the stripping being configured on each two surface Absciss layer, and the metal layer being configured on each peeling layer；

The composite layer of non-conductor inorganic material and organic material is configured on each metal layer；

It is combined on the composite layer of each non-conductor inorganic material and organic material and is embedded into wafer substrate, wherein each the multiple Being embedded into wafer substrate includes multiple chips and sealing, and the multiple chip is embedded into the sealing, and each chip tool There are multiple electrode pads, the multiple electronic pads expose to the sealing；

It is each it is described be embedded into wafer substrate formation line layer structure, wherein each line layer structure includes at least one dielectric Layer and at least one line layer, the dielectric layer have multiple conductive blind holes, and the line layer is located on the dielectric layer, and It extends in the multiple conductive blind hole, and the line layer of the bottom is electrically connected at institute by the multiple conductive blind hole State multiple electrode pads；

Insulating protective layer is formed in each line layer structure, wherein each insulating protective layer has multiple openings, so that The part of the surface of each line layer structure exposes in the multiple opening；

The support layer and the multiple peeling layer are removed to form two package substrates；And

Each package substrate is cut, to obtain multiple encapsulating structures.

7. manufacturing method as claimed in claim 6, which is characterized in that each sealing has sealing bottom surface, each chip With chip bottom surface, wherein described being embedded into chip in conjunction with each on the composite layer of each non-conductor inorganic material and organic material The step of substrate includes:

The sealing bottom surface is ground to the chip bottom surface is exposed outside, is embedded into wafer substrate after grinding to be formed；And

On the composite layer of each non-conductor inorganic material and organic material in conjunction with the grinding after be embedded into wafer substrate.

8. the manufacturing method as described in any one of claim 6 to 7, which is characterized in that each non-conductor inorganic material with The material of the composite layer of organic material includes the composite material as composed by ceramic material and high molecular material.

9. manufacturing method as claimed in claim 8, which is characterized in that the ceramic material includes zirconium oxide, aluminium oxide, nitridation Silicon, silicon carbide, silica or combination above-mentioned, and the high molecular material includes epoxy resin, polyimide, polymerizable mesogenic Object, methacrylate type resin, Ethenylbenzene fundamental mode resin, allyl type resin, polyacrylate resin, polyether-type tree Rouge, polyolefin-type resin, polyamine type resin, polysiloxane type resin or combination above-mentioned.

10. manufacturing method as claimed in claim 6, which is characterized in that each non-conductor inorganic material and organic material Composite layer is imitative nacre.