CN109270758B - Array substrate, display panel and cutting control method of array substrate - Google Patents
Array substrate, display panel and cutting control method of array substrate Download PDFInfo
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- CN109270758B CN109270758B CN201811284609.0A CN201811284609A CN109270758B CN 109270758 B CN109270758 B CN 109270758B CN 201811284609 A CN201811284609 A CN 201811284609A CN 109270758 B CN109270758 B CN 109270758B
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G02F1/133351—Manufacturing of individual cells out of a plurality of cells, e.g. by dicing
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136254—Checking; Testing
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Abstract
The invention discloses an array substrate, a display panel and a cutting control method of the array substrate. The array substrate is provided with a gap and comprises a display area and a gap non-display area, wherein the gap non-display area surrounds the gap, and the display area surrounds the gap non-display area; further comprising: the conductive routing is positioned in the gap non-display area and arranged along the edge of the gap; and the test boards are electrically connected with the conductive wires through connecting wires, wherein at least two test boards are electrically connected to the same conductive wire. The invention can realize the control of the cutting precision of the array substrate.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel and a cutting control method of the array substrate.
Background
In the conventional display device technology, the display panel is mainly divided into two mainstream technologies, namely a liquid crystal display panel and an organic self-luminous display panel. The liquid crystal display panel forms an electric field capable of controlling the deflection of liquid crystal molecules by applying voltage on the pixel electrode and the common electrode, and further controls the transmission of light rays to realize the display function of the display panel; the organic self-luminous display panel adopts an organic electroluminescent material, and when current passes through the organic electroluminescent material, the luminescent material can emit light, so that the display function of the display panel is realized.
With the application of display technology in smart wearable and other portable electronic devices, smooth user experience is continuously pursued in the design of electronic products, and meanwhile, sensory experience of users is also increasingly pursued, for example: the wide viewing angle, high resolution, narrow frame, high screen ratio and other performances become selling points of various electronic products. The prior art has the scheme that through holes are formed in a display panel, devices such as a camera and an inductor are arranged in a concentrated mode to reduce the space of a non-display area and improve the screen occupation ratio, the array substrate needs to be cut to form the through holes in the scheme, and the requirement for strict control of the cutting precision of the array substrate is met for reducing the cost and improving the yield of products.
Therefore, it is an urgent technical problem to be solved in the art to provide an array substrate, a display panel and a cutting control method of the array substrate capable of controlling the cutting accuracy of the array substrate.
Disclosure of Invention
In view of this, the present invention provides an array substrate, a display panel and a cutting control method for the array substrate, which solve the technical problem of controlling the cutting accuracy.
In order to solve the above technical problem, in a first aspect, the present invention provides an array substrate, where the array substrate has a notch, and the array substrate includes a display area and a notch non-display area, where the notch non-display area surrounds the notch, and the display area surrounds the notch non-display area; further comprising:
the conductive routing is positioned in the gap non-display area and arranged along the edge of the gap;
and the test boards are electrically connected with the conductive wires through connecting wires, wherein at least two test boards are electrically connected to the same conductive wire.
In a second aspect, the present invention provides a display panel including any one of the array substrates provided by the present invention.
In a third aspect, the present invention further provides a cutting control method for an array substrate, where the cutting control method is used to perform cutting control on any one of the array substrates provided by the present invention, and the cutting control method includes:
detecting a resistance value between two test boards electrically connected to the same conductive wire aiming at the cut array substrate to obtain a cut test value;
when the test value after cutting is a specific numerical value, the conductive routing is complete, and the cutting position of the array substrate does not deviate;
when the test value is infinite after cutting, the conductive routing is incomplete, and the cutting position of the array substrate deviates.
Compared with the prior art, the array substrate, the display panel and the cutting control method of the array substrate provided by the invention at least realize the following beneficial effects:
in the array substrate provided by the invention, the conductive wires are arranged around the notch of the array substrate, and the integrity of the conductive wires can be detected by testing the two test boards electrically connected with the conductive wires, so that the cutting precision is determined, and the follow-up processing is still carried out after the cutting precision exceeds the specification.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a schematic top view of an alternative embodiment of an array substrate according to an embodiment of the invention;
fig. 2 is a schematic diagram of another alternative embodiment of an array substrate according to an embodiment of the present invention;
fig. 3 is a schematic diagram of another alternative embodiment of an array substrate according to an embodiment of the present invention;
fig. 4 is a schematic diagram of another alternative embodiment of an array substrate according to an embodiment of the present invention;
fig. 5 is a schematic diagram of another alternative embodiment of an array substrate according to an embodiment of the present invention;
fig. 6 is a schematic diagram of another alternative embodiment of an array substrate according to an embodiment of the present invention;
fig. 7 is a schematic diagram of another alternative embodiment of an array substrate according to an embodiment of the present invention;
fig. 8 is a schematic view of another alternative embodiment of an array substrate according to an embodiment of the present invention;
fig. 9 is a schematic view of another alternative embodiment of an array substrate according to an embodiment of the present invention;
fig. 10 is a schematic view of another alternative embodiment of an array substrate according to an embodiment of the present invention;
fig. 11 is a schematic view of another alternative embodiment of an array substrate according to an embodiment of the present invention;
fig. 12 is a schematic view illustrating a film structure of the array substrate provided in the embodiment of fig. 11;
fig. 13 is a schematic view of another alternative embodiment of an array substrate according to an embodiment of the present invention;
fig. 14 is a schematic view of another alternative embodiment of an array substrate according to an embodiment of the present invention;
FIG. 15 is a schematic diagram illustrating a film structure of the array substrate provided in the embodiment of FIG. 14;
fig. 16 is a schematic view of another alternative embodiment of an array substrate according to an embodiment of the present invention;
fig. 17 is a schematic view illustrating a film structure of the array substrate provided in the embodiment of fig. 16;
FIG. 18 is a schematic view of a display panel according to the present invention;
fig. 19 is a flowchart of an alternative embodiment of a method for controlling cutting of an array substrate according to an embodiment of the present invention;
fig. 20 is a flowchart of another alternative embodiment of a cutting control method of an array substrate according to an embodiment of the present invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Fig. 1 is a schematic top view of an alternative embodiment of an array substrate according to an embodiment of the invention. As shown in fig. 1, the array substrate has a gap K, the array substrate includes a display area AA and a gap non-display area BAK, the gap non-display area BAK surrounds the gap K, and the display area AA surrounds the gap non-display area BAK. The display area AA corresponds to the display area in the display panel after the array substrate is assembled into the display panel. Various devices and wires for driving the pixels to emit light are arranged in the display area AA of the array substrate. The array substrate is cut to form a notch K, the notch K is a through hole, and the notch K penetrates through the array substrate in the direction perpendicular to the array substrate. Some wires can be arranged in the gap non-display area BAK surrounding the gap K, or the wires are reserved in an area where the frame glue is arranged when the display panel is assembled.
The array substrate further includes: and the conductive routing X is positioned in the gap non-display area BAK and is arranged along the edge M of the gap K, wherein the edge M of the gap K is the side wall of the gap K formed after the array substrate is cut. The conductive trace X is disposed along the edge M of the notch, which means that the conductive trace X located in the notch non-display area BAK has a certain distance from the edge M of the notch K, and the distance between the conductive trace X and the edge M is approximately a fixed value. One wire trace X may be a closed trace as shown in fig. 1, or may be a conductive trace X disposed along only a portion of the edge M of the notch K. The shape and position of the notches K in fig. 1 are also only schematically indicated.
And the test boards P are electrically connected with the conductive traces X through the connecting lines L, wherein at least two test boards P are electrically connected to the same conductive trace X. That is, one conductive trace X is connected to at least two test boards P, and the two test boards P are connected to different positions of the conductive trace X, respectively, thereby achieving the electrical connection between the test board P-wire trace X-test board P. Alternatively, three test boards P may be connected to one wire trace X, or four test boards P may be connected to one wire trace X. The material of the test board P may be metal or indium tin oxide.
The array substrate is generally manufactured on the whole surface, and when the array substrate having the notch is manufactured, the array substrate on the whole surface needs to be cut to form the notch. In the array substrate provided by the invention, the conductive wires are arranged around the notch of the array substrate, and the integrity of the conductive wires can be detected by testing the two test boards electrically connected with the conductive wires, so that the cutting precision is determined, and the follow-up processing is still carried out after the cutting precision exceeds the specification.
The conductive routing in the array substrate provided by the invention is a cutting warning line. Taking the array substrate shown in fig. 1 as an example, the conductive traces X are disposed around the gap K, and the two test boards P are respectively connected to the conductive traces X through the connecting lines L. And arranging a cutting line in the uncut array substrate, wherein the position of the cutting line is the edge M of the gap K. Before the array substrate is cut along the cutting line, the resistance value between the two test boards P is detected and recorded as an initial value. And then cutting the array substrate, and detecting the resistance value between the two test boards P again to be recorded as a cut test value. When the test value after cutting is infinite, the conductive trace X is cut, and the deviation of the cutting position can be directly judged; when the test value after cutting is the same as the initial value, the conductive trace X is complete, and the cutting position does not deviate; when the test value after cutting is different from the initial value, the conductive trace X is not complete, the cutting position can be judged to be deviated, and the wire trace X is cut by the cutting process. The array substrate with the deviated cutting position can be classified as a defective product, and subsequent process is not carried out.
The conductive routing in the array substrate provided by the invention is a closed routing arranged around the notch. One conductive trace may be electrically connected to two test boards as shown in fig. 1, or one conductive trace may also be electrically connected to three test boards, or may also be electrically connected to four test boards.
In an embodiment, fig. 2 is a schematic view of another alternative implementation of the array substrate according to an embodiment of the present disclosure. As shown in FIG. 2, one conductive trace electrically connects four test boards P1/P2/P3/P4 through a connecting line L. Before the array substrate is cut, an initial value can be obtained by detecting any two test boards, after the array substrate is cut, the test resistance values of the test boards are still tested in pairs to obtain a cut test value, and then whether the conductive wiring is complete or not is judged by comparing the cut test value with the initial value. In fig. 2, when only one of the four line segments is cut off, the cut test values of any two test boards are different from the initial values. When more than two of the four line segments are cut off, the position of the cut-off conductive wire can be roughly judged by comparing the test value after cutting with the initial value, namely the offset position of the cutting process can be judged, and the parameters of the cutting process can be adjusted by taking the offset position as reference.
In some optional embodiments, in the array substrate provided by the present invention, at least two mutually insulated conductive traces are respectively routed along different positions of an edge of the notch, and the at least two mutually insulated conductive traces form a non-closed trace disposed around the notch. In the embodiment, whether the conductive wire is complete or not can be judged by testing the two test boards electrically connected with the conductive wire, so that the cutting precision is determined, and the follow-up manufacturing process is still carried out after the cutting precision exceeds the specification. When the cut wire routing exists, the cutting position of the wire routing can be determined, so that the offset position of the cutting process can be judged, and the cutting process parameters can be adjusted as reference.
In an embodiment, fig. 3 is a schematic view of another alternative implementation of the array substrate according to an embodiment of the present invention. As shown in fig. 3, two mutually insulated conductive traces X are respectively routed along different positions of the edge M of the notch K, and the two mutually insulated conductive traces X form a non-closed trace arranged around the notch K. Fig. 3 includes two wire traces 1X and 2X, where the wire trace 1X and the wire trace 2X are electrically connected to the two test boards through two connecting wires, respectively.
When the cut array substrate is tested for cutting accuracy, whether the conductive trace 1X is complete or not can be judged by detecting the resistance value between two test boards P electrically connected with the conductive trace 1X and recording the resistance value as a test value after cutting, and when the test value after cutting is a specific numerical value, the conductive trace 1X is complete; when the test value after cutting is infinite, the conductive trace 1X is incomplete, and the cutting position of the array substrate is shifted to the direction in which the conductive trace 1X is located. Whether the conductive wire 1X is complete or not can be detected by the same method, and whether the cutting position of the array substrate deviates to the direction of the conductive wire 2X or not is judged. In addition, in the embodiment, when detecting whether the conductive trace is complete or not, only the cut array substrate needs to be tested, and the resistance value between the two test boards electrically connected with the conductive trace does not need to be tested in advance between the cutting of the array substrate, which is equivalent to simplifying the process of cutting precision detection, improving the efficiency and saving the production cost.
In an embodiment, fig. 4 is a schematic view of another alternative implementation of the array substrate according to an embodiment of the present disclosure. As shown in fig. 4, the four mutually insulated conductive traces X are respectively routed along different positions of the edge M of the notch K, and the four mutually insulated conductive traces X form a non-closed trace disposed around the notch K. Four wire traces X are connected with two test boards respectively through two connecting wires. The array substrate provided by this embodiment can determine whether the conductive trace is complete or not by using the same detection method as that in the embodiment corresponding to fig. 3, so as to determine the cutting accuracy. For the specific determination manner, reference may be made to the corresponding description of the embodiment in fig. 3, which is not described herein again.
In an embodiment, in the array substrate provided by the invention, in the non-display area of the notch, three mutually insulated wire traces X may be disposed to trace along different positions of the edge of the notch, respectively, and the three mutually insulated wire traces form a non-closed trace disposed around the notch. The method for detecting the cutting accuracy can be correspondingly described with reference to the embodiment of fig. 3.
In some alternative embodiments, at least two conductive traces are sequentially arranged in the gap non-display area in a direction from the gap to the display area. Fig. 5 is a schematic diagram of another alternative embodiment of the array substrate according to an embodiment of the present invention. As shown in fig. 5, only three conductive traces X are sequentially arranged in the gap non-display area BAK in the direction from the gap K to the display area AA. In the direction pointing to the display area from the gap, the distances between two adjacent conductive traces X may be the same or different. The embodiment can test the cut array substrate, the resistance value between two test boards electrically connected with the same conductive wire is detected to be a cutting test value, and the offset distance of the array substrate cutting is judged through the cutting test value.
Taking the embodiment shown in fig. 5 as an example, the method for detecting the cutting accuracy of the array substrate provided by the present invention is described as follows:
as shown in fig. 5, in the direction e pointing to the display area AA from the notch K, three conductive traces 1X/2X/3X are sequentially arranged in the notch non-display area BAK, and in the cut array substrate, the resistance values between two test boards electrically connected to the three conductive traces 1X/2X/3X are tested to obtain a test value data set consisting of resistance values R1, R2, and R3, where the resistance value between two test boards electrically connected to the conductive trace 1X is R1, the resistance value between two test boards electrically connected to the conductive trace 2X is R2, and the resistance value between two test boards electrically connected to the conductive trace 3X is R3.
When the resistance values R1, R2, and R3 are all specific values, it can be determined that all three conductive traces 1X/2X/3X are complete after the cutting, and the cutting offset distance of the array substrate is zero.
When the resistance value R1 is infinite and R2 and R3 are both specific values, it can be determined that the conductive trace 1X is cut off, the conductive traces 2X and 3X are both complete, and the cutting of the array substrate is deviated. The offset distance of the array substrate cutting is approximately the distance from the preset cutting line (i.e. the cutting line defined for the uncut array substrate, not the actual cutting line) to the conductive trace 1X.
When the resistance values R1 and R2 are infinite and R3 is a specific value, it can be determined that the conductive traces 1X and 2X are cut off, the conductive trace 3X is complete, and the cutting of the array substrate is deviated. The offset distance of the array substrate cutting is approximately the distance between the preset cutting line and the conductive trace 1X plus the distance between the conductive trace 1X and the conductive trace 2X.
When the resistance values R1, R2, and R3 are all infinite, it can be determined that the conductive traces 1X, 2X, and 3X are all cut off, and the cutting of the array substrate is severely deviated. The offset distance for cutting the array substrate is approximately: the distance between the preset cutting line and the conductive trace 1X, the distance between the conductive trace 1X and the conductive trace 2X and the distance between the conductive trace 2X and the conductive trace 3X are respectively set.
In this embodiment, the offset distance of the cutting can be determined according to the test value data set and the distance between two adjacent conductive traces in the direction from the notch to the display area. Thereby being capable of more accurately adjusting the cutting process parameters.
With reference to fig. 5, in the direction pointing to the display area AA from the notch K, the distance between two adjacent conductive traces X is d, where d is greater than or equal to 3 μm and less than or equal to 10 μm. The distance between two adjacent electrically conductive lines X can be the same or different, if the distance d undersize can be stricter to the manufacturing process requirement of electrically conductive line, increase the cost of manufacture, if the distance d is too big, the electrically conductive line of arranging in the breach non-display area has increased the space in non-display area, is unfavorable for improving the design demand that the screen accounts for the ratio.
The array substrate provided by the invention further comprises a peripheral non-display area surrounding the display area, as shown in fig. 1 or fig. 3, the test board P is located in the peripheral non-display area BA. In this embodiment, the test board P is disposed in the peripheral non-display region, and does not occupy the space of the display region.
In an embodiment, fig. 6 is a schematic view of another alternative implementation of the array substrate according to an embodiment of the present disclosure. As shown in fig. 6, in a direction pointing to the display area AA from the notch K, three conductive traces X are sequentially arranged in the notch non-display area BAK, where the conductive trace X near the edge M of the notch K is a closed trace arranged around the notch K, and the conductive trace X on the outer ring is not a closed trace.
In an embodiment, fig. 7 is a schematic view of another alternative implementation of the array substrate according to an embodiment of the present disclosure. As shown in fig. 7, the connection lines L include a first connection line L1, the test board P includes a first test board P1, and the first test board P1 is electrically connected to the first connection line L1; within the display area AA, the first connection line L1 extends in the first direction a; the peripheral non-display area BA includes first non-display areas BA1, and two first non-display areas BA1 are respectively located at both sides of the display area AA in the first direction a; the first test plate P1 is positioned in the first non-display area BA 1. Fig. 7 illustrates a case where the connecting wires are closed traces.
Fig. 7 shows that the first test boards connected to the same conductive trace are dispersedly disposed in the two first non-display areas. Optionally, the first test boards connected to the same conductive trace are located in the same first non-display area, as shown in fig. 8, and fig. 8 is a schematic view of another optional implementation manner of the array substrate according to the embodiment of the present invention. The connection line L includes a first connection line L1, the test board P includes a first test board P1, the first test board P1 is electrically connected to the first connection line L1; within the display area AA, the first connection line L1 extends in the first direction a; the peripheral non-display area BA includes first non-display areas BA1, and two first non-display areas BA1 are respectively located at both sides of the display area AA in the first direction a; the first test boards connected to the same conductive trace are located in the same first non-display area BA 1.
In an embodiment, fig. 9 is a schematic view of another alternative implementation of the array substrate according to an embodiment of the present disclosure. Fig. 10 is a schematic diagram of another alternative embodiment of the array substrate according to the embodiment of the invention. Referring to fig. 9 and 10 together, the connection lines L include first connection lines L1, the test board P includes a first test board P1, and the first test board P1 is electrically connected to the first connection lines L1; within the display area AA, the first connection line L1 extends in the first direction a; the peripheral non-display area BA includes first non-display areas BA1, and two first non-display areas BA1 are respectively located at both sides of the display area AA in the first direction a; the first test plate P1 is positioned in the first non-display area BA 1. The connecting line L further comprises a second connecting line L2, the test board P comprises a second test board P2, and the second test board P2 is electrically connected with the second connecting line L2; within the display area AA, the second connection line L2 extends along a second direction b, which intersects the first direction a, and optionally, the second direction b is perpendicular to the first direction a; the peripheral non-display area BA further includes a second non-display area BA2, in the second direction b, two second non-display areas BA2 are respectively located at two sides of the display area AA, and the second test board P2 is located in the second non-display area BA 2.
The array substrate provided by the invention comprises a plurality of signal lines extending along a first direction, and the first connecting lines and the signal lines are positioned on the same film layer of the array substrate. The signal line may be a data line, a gate line, or a touch signal line.
In an embodiment, fig. 11 is a schematic view of another alternative implementation of the array substrate according to an embodiment of the present disclosure. Fig. 12 is a schematic view of a film structure of the array substrate provided in the embodiment of fig. 11.
As shown in fig. 11, the array substrate includes a plurality of data lines D extending in a first direction a, and the first connection lines L1 extend in the same direction as the data lines D. As shown in fig. 12, the array substrate 100 is a multi-film stack structure, a plurality of thin film transistors T are disposed in the array substrate 100, the thin film transistors T serve as devices for controlling pixel switches, each thin film transistor T includes a gate, a source, a drain, and an active layer, a data line, the source, and the drain are disposed in the same film layer, and a gate line and the gate are disposed in the same film layer. Fig. 12 illustrates a thin film transistor with a top gate structure. The array substrate T comprises a first metal layer M1 and a second metal layer M2, the source electrode, the drain electrode and the data line D in the array substrate 100 are located in the first metal layer M1, and the gate electrode and the gate line G are located in the second metal layer M2; the first connecting line L1 and the data line D are located on the same film layer. In the array substrate provided by the embodiment, the first connecting line and the data line are located in the same film layer, and the first connecting line and the data line can be manufactured in the same process, so that the manufacturing process of the array substrate can be simplified. Optionally, the conductive routing and the first connection line (i.e., the connection line) are located on the same film layer, so that the film layer thickness of the array substrate is not increased while the cutting accuracy of the array substrate can be controlled, and the requirement of thinning is facilitated.
In an embodiment, the array substrate further includes touch signal lines, the touch signal lines and the data lines are located in the same film layer, generally, in the arrangement direction of the touch signal lines and the data lines, three data lines are arranged between two effective touch signal lines at intervals to realize a touch detection function, and in order to ensure the uniformity of the array substrate wiring and the uniformity of pixel display after a display panel is assembled in a subsequent layer, dummy touch signal lines are manufactured in the array substrate to ensure that the touch signal lines and the data lines are alternately arranged in the arrangement direction. Fig. 13 is a schematic diagram of another alternative embodiment of the array substrate according to the embodiment of the invention. As shown in fig. 13, the touch signal lines CK and the data lines D are alternately arranged in the display area of the array substrate, and the touch signal lines CK include dummy touch signal lines SCK, and the first connection lines may multiplex the dummy touch signal lines SCK. The dummy touch signal lines are dummy lines and are not used for transmitting touch signals, and the display effect uniformity of the display area can be improved through the dummy touch signal lines SCK; the touch signal line CK and the dummy touch signal line SCK are located on the same film layer. The first connecting line in the embodiment reuses the original structure of the array substrate, does not increase new process, and is simple and easy to implement. Optionally, in this embodiment, a manufacturing process of the silver rubber plate is further included when the array substrate is manufactured, and the test board in the invention may also reuse the manufacturing process of the silver rubber plate.
In an embodiment, fig. 14 is a schematic view of another alternative implementation of the array substrate according to an embodiment of the present disclosure. Fig. 15 is a schematic view of a film structure of the array substrate provided in the embodiment of fig. 14.
As shown in fig. 14, the array substrate includes a plurality of gate lines G extending in a first direction a, and the first connection line L1 extends in the same direction as the gate lines G. The array substrate 100 is provided with a plurality of thin film transistors T as devices for controlling pixel switches, and only the thin film transistor with a top gate structure is taken as an example in fig. 15. As shown in fig. 15, the array substrate 100 includes a first metal layer M1 and a second metal layer M2, wherein the data line D is located in the first metal layer M1 and the gate line G is located in the second metal layer M2 in the array substrate 100; the first connecting line L1 is located on the same layer as the gate line G. In the array substrate provided by the embodiment, the first connecting line and the gate line are located on the same film layer, and the first connecting line and the gate line can be manufactured in the same process, so that the manufacturing process of the array substrate can be simplified. Optionally, the conductive routing and the first connection line (i.e., the connection line) are located on the same film layer, so that the film layer thickness of the array substrate is not increased while the cutting accuracy of the array substrate can be controlled, and the requirement of thinning is facilitated.
In an embodiment, fig. 16 is a schematic view of another alternative implementation of the array substrate according to the embodiment of the present disclosure. Fig. 17 is a schematic view of a film structure of the array substrate provided in the embodiment of fig. 16.
As shown in fig. 16, the array substrate includes a plurality of touch signal lines CK extending along a first direction a, and the extending direction of the first connecting lines L1 is the same as the extending direction of the touch signal lines CK. The array substrate 100 is provided with a plurality of thin film transistors T as devices for controlling pixel switches, and only the thin film transistor with a top gate structure is taken as an example in fig. 17. As shown in fig. 17, the array substrate includes a first metal layer M1, a second metal layer M2, and a third metal layer M3; in the array substrate 100, the data line D is located in the first metal layer M1, the gate line G is located in the second metal layer M2, and the touch signal line CK is located in the third metal layer M3; the first connecting line L1 and the touch signal line CK are located on the same film layer. In the array substrate provided by the embodiment, the first connecting line and the touch signal line are located on the same film layer, and the first connecting line and the touch signal line can be manufactured in the same process, so that the manufacturing process of the array substrate can be simplified. Optionally, the conductive routing and the first connection line (i.e., the connection line) are located on the same film layer, so that the film layer thickness of the array substrate is not increased while the cutting accuracy of the array substrate can be controlled, and the requirement of thinning is facilitated.
In the above embodiments, the notch of the array substrate is described by taking a circular notch as an example, but the present invention is not limited thereto, and the shape of the notch of the array substrate may be rectangular, square, oval or triangular. The design can be designed according to specific design requirements.
Based on the same inventive concept, the present invention further provides a display panel, and fig. 18 is a schematic view of the display panel provided by the present invention, where the display panel provided by the present invention includes the array substrate provided in any of the embodiments described above.
The display panel provided by the invention can be a liquid crystal display panel, and further comprises a color film substrate arranged opposite to the array substrate, and a liquid crystal molecular layer is arranged between the array substrate and the color film substrate. Liquid crystal molecules are not arranged at the position of the notch of the array substrate, color resistors are not arranged at the position, corresponding to the notch of the array substrate, in the color film substrate, or the position, corresponding to the notch of the array substrate, in the color film substrate is cut off to form a through hole.
The display panel provided by the invention can be an organic light-emitting display panel, and further comprises a display layer arranged on the array substrate, wherein the display layer comprises a plurality of organic light-emitting devices.
The invention further provides a cutting control method of the array substrate, the cutting control method is used for controlling cutting of the array substrate provided by the invention, and fig. 19 is a flow chart of an optional implementation mode of the cutting control method of the array substrate provided by the embodiment of the invention. As shown in fig. 19, the cutting control method includes:
step S101: detecting a resistance value between two test boards electrically connected to the same conductive wire aiming at the cut array substrate to obtain a cut test value; whether the conductive routing is complete or not is judged through the test value of the cutting opening, so that whether the cutting position of the array substrate deviates or not is judged.
Step S102: when the test value after cutting is a specific numerical value, the conductive routing is complete, and the cutting position of the array substrate does not deviate; when the test value after cutting is infinite, the conductive routing is incomplete, and the cutting position of the array substrate deviates
Step S103: when the test value is infinite after cutting, the conductive routing is incomplete, and the cutting position of the array substrate deviates.
The description of the application of the cutting control method provided by this embodiment can be referred to the corresponding description of the embodiment in fig. 3. In the embodiment, when the completeness of the conductive wiring is detected, only the array substrate after cutting needs to be tested, and the resistance value between the two test boards electrically connected with the conductive wiring is not required to be tested in advance between the cutting of the array substrate, which is equivalent to simplifying the process of cutting precision detection, improving the efficiency and saving the production cost.
In the array substrate provided in some optional embodiments, at least two wire traces are sequentially arranged in the gap non-display area in a direction from the gap to the display area; the array substrate provided in this embodiment may adopt the cutting control method provided in fig. 20, and fig. 20 is a flowchart of another alternative implementation manner of the cutting control method of the array substrate provided in this embodiment of the present invention. As shown in figure 20 of the drawings,
step S201: aiming at the cut array substrate, in the direction of pointing to the display area from the gap, testing the resistance value between two test boards which are electrically connected with the sequentially arranged wire routing to obtain a test value data group;
step S202: and judging the cutting offset distance according to the test value data group and the distance between two adjacent conductive wires in the direction pointing to the display area from the notch. The distance between two adjacent wire traces can be the same or different.
The description of the application of the cutting control method provided in this embodiment can be made with reference to the corresponding implementation of fig. 5. The embodiment can judge the cutting offset distance according to the test value data group and the distance between two adjacent conductive wires in the direction pointing to the display area from the notch. Not only can be according to the electrically conductive complete not definite cutting accuracy of walking the line, the skew distance of judgement cutting that moreover can be more accurate to adjustment cutting process parameter that can be more accurate.
According to the embodiment, the array substrate, the display panel and the cutting control method of the array substrate, provided by the invention, at least the following beneficial effects are realized:
in the array substrate provided by the invention, the conductive wires are arranged around the notch of the array substrate, and the integrity of the conductive wires can be detected by testing the two test boards electrically connected with the conductive wires, so that the cutting precision is determined, and the follow-up processing is still carried out after the cutting precision exceeds the specification.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (15)
1. An array substrate is characterized in that the array substrate is provided with a notch and comprises a display area and a notch non-display area, wherein the notch non-display area surrounds the notch, and the display area surrounds the notch non-display area; further comprising:
the conductive routing is positioned in the gap non-display area and is arranged along the edge of the gap, at least two mutually insulated conductive routing wires are respectively routed along different positions of the edge of the gap, and the at least two mutually insulated conductive routing wires form a non-closed routing wire arranged around the gap;
and the test boards are electrically connected with the conductive traces through connecting lines, wherein at least two test boards are electrically connected to the same conductive trace.
2. The array substrate of claim 1,
the conductive routing lines are cutting warning lines.
3. The array substrate of claim 1,
at least two conductive wires are sequentially arranged in the gap non-display area in the direction from the gap to the display area.
4. The array substrate of claim 3,
in the direction pointing to the display area from the notch, the distance between two adjacent conductive wires is d, wherein d is more than or equal to 3 mu m and less than or equal to 10 mu m。
5. The array substrate of claim 1,
the array substrate further comprises a peripheral non-display area surrounding the display area, and the test board is located in the peripheral non-display area.
6. The array substrate of claim 5,
the connecting wires comprise first connecting wires, the test board comprises a first test board, and the first test board is electrically connected with the first connecting wires;
within the display area, the first connecting line extends along a first direction;
the peripheral non-display area comprises first non-display areas, and in the first direction, the two first non-display areas are respectively positioned at two sides of the display area; the first test board is located in the first non-display area.
7. The array substrate of claim 6,
the connecting wires further comprise second connecting wires, the test board comprises a second test board, and the second test board is electrically connected with the second connecting wires;
in the display area, the second connecting line extends along a second direction, and the second direction is crossed with the first direction;
the peripheral non-display area further comprises second non-display areas, in the second direction, the two second non-display areas are located on two sides of the display area respectively, and the second test board is located in the second non-display areas.
8. The array substrate of claim 6,
the first test boards connected to the same conductive trace are located in the same first non-display area, or the first test boards connected to the same conductive trace are dispersedly disposed in two first non-display areas.
9. The array substrate of claim 6,
the array substrate comprises a plurality of signal lines extending along the first direction, and the first connecting lines and the signal lines are located on the same film layer of the array substrate.
10. The array substrate of claim 9,
the array substrate comprises a first metal layer and a second metal layer, and the array substrate comprises data lines and gate lines; the data line is positioned on the first metal layer, and the gate line is positioned on the second metal layer;
the first connecting line and the data line or the gate line are located on the same film layer.
11. The array substrate of claim 9,
the array substrate comprises a first metal layer, a second metal layer and a third metal layer;
the array substrate comprises data lines, gate lines and touch signal lines, wherein the data lines are located on the first metal layer, the gate lines are located on the second metal layer, and the touch signal lines are located on the third metal layer; the first connecting line and the touch signal line are located on the same film layer.
12. The array substrate of claim 1,
the conductive wires and the connecting wires are located on the same film layer of the array substrate.
13. A display panel comprising the array substrate according to any one of claims 1 to 12.
14. A method for controlling cutting of an array substrate, the method being used for controlling cutting of the array substrate according to any one of claims 1 to 12, the method comprising:
detecting a resistance value between two test boards electrically connected to the same conductive wire according to the cut array substrate to obtain a cut test value;
when the test value after cutting is a specific numerical value, the conductive routing is complete, and the cutting position of the array substrate does not deviate;
when the test value after cutting is infinite, the conductive routing is incomplete, and the cutting position of the array substrate deviates.
15. The cutting control method according to claim 14, wherein at least two of the conductive traces are sequentially arranged in the gap non-display area in a direction from the gap to the display area;
for the array substrate after cutting, detecting a resistance value between two test boards electrically connected to the same conductive wire to obtain a test value after cutting, specifically:
aiming at the cut array substrate, in the direction pointing to the display area from the gap, testing the resistance value between the two test boards electrically connected with the sequentially arranged conductive wires to obtain a test value data set;
the cutting control method further includes:
and judging the cutting offset distance according to the test value data group and the distance between two adjacent conductive wires in the direction pointing to the display area from the notch.
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| CN110426885B (en) * | 2019-07-22 | 2020-12-04 | 武汉华星光电半导体显示技术有限公司 | Display panel, manufacturing method and display device |
| CN113224107A (en) * | 2020-01-21 | 2021-08-06 | 华为技术有限公司 | Display panel and display device |
| KR20220042020A (en) | 2020-09-25 | 2022-04-04 | 삼성디스플레이 주식회사 | Display panel and display apparatus including the same |
| CN113838903B (en) * | 2021-09-26 | 2024-05-07 | 京东方科技集团股份有限公司 | Display panel, preparation method of display panel and display device |
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