CN109254224A - A kind of open circuit of the communications cable, misconnection line sequence measurement method and system - Google Patents
A kind of open circuit of the communications cable, misconnection line sequence measurement method and system Download PDFInfo
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- CN109254224A CN109254224A CN201811344638.1A CN201811344638A CN109254224A CN 109254224 A CN109254224 A CN 109254224A CN 201811344638 A CN201811344638 A CN 201811344638A CN 109254224 A CN109254224 A CN 109254224A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
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Abstract
The present invention discloses a kind of breaking communications cable, misconnection line sequence measurement method and system, it uses two circuit switches to be successively respectively turned on two different cables, a resistance is accessed on every cable, judges whether route is connected or misconnection using the sample voltage value between access resistance and divider resistance.When carrying out communications cable measurement using the present invention, if breaking 1 line, other line sequence measurement results are unaffected, can really reflect wire quality；It, also can accurate measurements if line sequence is arbitrarily intersected；Entire principle is made of resistance and diode, and measuring speed is fast, while measurement result is not influenced by temperature and humidity, and stability is high.
Description
Technical field
The present invention discloses a kind of communications cable measurement method and system, especially a kind of communications cable open circuit, misconnection line sequence
Measurement method and system belong to cable fault the field of test technology.
Background technique
The communications cable typically refers to: grid line (inside be made of 8 core wires), telephone wire (inside is at most made of 6 core wires),
Coaxial line (inside is made of 2 core wires), USB line (inside is made of 4 core wires) etc., in addition to this, there are also other for communication
Cable form, will not enumerate herein.In comprehensive wiring, whether the wire rod for needing to detect production is connected to and whether line sequence
Correctly, if be not connected to or line sequence mistake, gently if will affect communication quality and effect, it is heavy then communication mistake can be generated, no
Can communicate etc..
The communications cable measurement method generallyd use in currently available technology has following two ways:
1, LED Dynamically Announce method:
By cable one end to be measured access host, another termination distal, every line and LED light corresponding on instrument are direct-connected, lead to
It crosses controller successively to gate, human eye observes currently selected wire size and whether the LED number currently lighted consistent and LED in real time
Whether lamp is lighted, and then may determine that whether cable to be measured has open circuit or cross faults.
Its existing main problem is: for the cable of 8 cores, needing successively to light all wire sizes, Synchronous is as a result, institute
It is slow with measuring speed, and it is easy error；If the both ends of wire rod in same place, do not need two people to measure jointly, very
It is inconvenient.
2, capacitor normal shows result to measurement, LCD:
Cable one to be measured is terminated into host, another termination distal, using single-chip microcontroller and internal switching circuit, automatic measurement,
Final result is shown to above LCD.
Its existing main problem is: being all 1-2,3-6,4-5 for grid line, 7-8 carries out pairing setting, such as
Fruit any wire open circuit, then with it, matched wire size also is unable to measure out；If breaking core number is more than the half of sum,
Then the measurement result of remaining core is also all incorrect；In addition, having used capacity cell in the circuit of the measurement method, cause by temperature
Degree is affected, under high and low temperature environment, measurement result mistake or unstable.
Summary of the invention
The shortcomings that it is inconvenient to measure for the communications cable in the prior art mentioned above, some situations are unable to measure,
The present invention provides a kind of breaking communications cable, misconnection line sequence measurement method and system, and two circuit switches is used in turn switch on
Both threads cable judges whether route is connected or misconnection using the voltage value that divider resistance is got.
The technical solution used to solve the technical problems of the present invention is that: a kind of open circuit of the communications cable, misconnection line sequence measurement side
Method, measurement method are that cable one end to be measured is connected on host using host and distal, cable other end connection to be measured
On distal, at host, positive supply is connect by divider resistance Rs with one end of first switch K1, second switch K2 mono-
End ground connection, distal are provided with access resistance R1 ~ access resistance Rn, wherein n is the natural number more than or equal to 2, access electricity
Resistance R1 ~ one end access resistance Rn link together, access resistance R1 ~ access resistance Rn other end successively respectively with cable to be measured
The connection of piece core wire, access resistance R1 ~ access resistance Rn resistance value is different, the other end of first switch K1 successively with it is to be measured
Each core wire of cable connects, and the second switch K2 other end successively connect with each core wire of cable to be measured, first switch K1 with
Second switch K2 cannot be connect with same root core wire simultaneously, appointed to take in the route between divider resistance Rs and access resistance and a little be made
For sampled point, by detecting sample amplitude when reproduced, judge the communications cable whether open circuit or misconnection, when sample amplitude when reproduced is equal to positive supply
When voltage, then illustrates the core wire of first switch K1 connection or the core wire open circuit of second switch K2 connection, second switch K2 is connected
On to another core wire, if sample amplitude when reproduced is not equal to positive voltage, illustrate the former core wire open circuit of second switch K2 connection,
When the corresponding default partial pressure value of the core wire that sample amplitude when reproduced is equal to first switch K1 connection, then illustrate that wiring is correct, if adopted
Sampling point voltage is not equal to the corresponding default partial pressure value of core wire of first switch K1 connection, then illustrates wiring error.
A kind of open circuit of the communications cable, misconnection line sequence measuring system, system includes being connected to the host side of cable one end to be measured
With the distal for being connected to the cable other end to be measured, host side includes that central control module, first switch module and second are opened
Module is closed, is connect by divider resistance Rs with positive supply on the input terminal of first switch module, the output end of second switch module
Ground connection, the output end of first switch module are electrically connected with cable connection interface module to be measured respectively with the input terminal of second switch module
It connects, central control module is connect with the control terminal of first switch module and second switch module respectively, central control module control
First switch module and the work of second switch module, distal are provided with access resistance R1 ~ access resistance Rn, wherein n is big
In or equal to 2 natural number, access resistance R1 ~ one end access resistance Rn link together, access resistance R1 ~ access resistance Rn it is another
One end is successively electrically connected with the connection interface module of cable to be measured respectively, accesses resistance R1 ~ access resistance Rn resistance value respectively not
Identical, first switch module is connect with the sampled point at the common end of divider resistance Rs with central control module.
The technical scheme adopted by the invention to solve the technical problem further comprises:
Forward direction is connected in parallel to a bypass diode respectively with access resistance R1 ~ access resistance Rn.
The first switch module selects electronic analog swtich chip U5, and second switch module selects electronic analog swtich
The enable end of chip U6, electronic analog swtich chip U5 and a universaling I/O port of central control module connect, and electronic simulation is opened
8 input/output terminals for closing chip U5 pass through interface module respectively and connect with a core wire in cable to be measured, and electronic simulation is opened
The public input/output end for closing chip U5 is connect with divider resistance Rs, and the control terminal of electronic analog swtich chip U5 is respectively in
Entreat the universaling I/O port connection of control module；One of the enable end of electronic analog swtich chip U6 and central control module is general
I/O mouthfuls of connections, 8 input/output terminals of electronic analog swtich chip U6 pass through one in interface module and cable to be measured respectively
The connection of core wire, the public input/output end ground connection of electronic analog swtich chip U6, the control terminal of electronic analog swtich chip U6
It is connect respectively with the universaling I/O port of central control module.
The system further includes having the first auxiliary switch module and the second auxiliary switch module, the first auxiliary switch module
Electronic analog swtich chip U14 is selected, the second auxiliary switch module selects electronic analog swtich chip U15, electronic analog swtich
The enable end of chip U14 and a universaling I/O port of central control module connect, and 8 of electronic analog swtich chip U14 are defeated
Enter/output end passes through interface module respectively and connect with a core wire in cable to be measured, electronic analog swtich chip U14's is public
Input/output end is connect with divider resistance Rs, and the control terminal of electronic analog swtich chip U14 is logical with central control module respectively
It is connected with I/O mouthfuls；The enable end of electronic analog swtich chip U15 and a universaling I/O port of central control module connect, electronics
8 of analog switch chip U15 inputs output end pass through interface module respectively and connect with a core wire in cable to be measured, it is electric
The public input/output end of sub- analog switch chip U15 is grounded, the control terminal of electronic analog swtich chip U15 respectively with center
The universaling I/O port of control module connects.
The system further includes having linear measure longimetry module, and linear measure longimetry module includes electronic switch module U3 and NAND gate
The enable end of module U4, electronic switch module U3 and the universaling I/O port of central control module connect, the X of electronic switch module U3
Pin and Y pin are connect with the com port of electronic analog swtich chip U5 respectively, and the control terminal of electronic switch module U3 is respectively in
The universaling I/O port connection of control module is entreated, the one end divider resistance Rs is connected on the X1 pin of electronic switch module U3, partial pressure electricity
The resistance Rs other end is connect with positive supply, and the Y1 pin of electronic switch module U3 is as voltage sample point output end, NAND gate module
U4 uses 4 NAND gate chips, and two input terminals of the first NAND gate are connect with the waveform delivery outlet of central control module, and first
The output end of NAND gate is connect with the X0 pin of electronic switch module U3, the input terminal and electronic switch mould of the second NAND gate
The X0 pin of block U3 connects, another input terminal of the second NAND gate is connect with the output end of the 4th NAND gate, the second NAND gate
Output end simultaneously connect with two input terminals of third NAND gate, the output end of third NAND gate and the wave of central control module
The connection of shape input terminal, two input terminals of the 4th NAND gate are connect with the Y0 pin of electronic switch module U3.
Voltage follower is connected on the Y1 pin of the electronic switch module U3, voltage follower uses amplifier
The Y1 pin of U7A, electronic switch module U3 are connect with the non-inverting input terminal of amplifier U7A, the inverting input terminal of amplifier U7A with
The output end of amplifier U7A connects, and the output end of amplifier U7A is voltage sample point output end, connect with central control module.
The host side is equipped with local detection interface, and local detection interface is connect with electronic analog swtich chip U8,
Electronic analog swtich chip U8 selects 1 duplex channel selector using 8, and the enable end and center of electronic analog swtich chip U8 control
One universaling I/O port of module connects, 8 input/output terminals of electronic analog swtich chip U8 pass through respectively interface module with
Core wire connection in cable to be measured, the public input/output end ground connection of electronic analog swtich chip U8, electronic analog swtich
The control terminal of chip U8 is connect with the universaling I/O port of central control module respectively.
The distal includes access resistance R1 ~ access resistance R9, and resistance R1 resistance value is 4.02K, resistance R2 resistance value
For 6.8K, resistance R3 resistance value is 16K, and resistance R4 resistance value is 20K, and resistance R5 resistance value is 24K, and resistance R6 resistance value is 27K, resistance R7
Resistance value is 33K, and resistance R8 resistance value is 40.2K, and the resistance value of resistance R9 is 47K, and divider resistance Rs resistance value is 10K, resistance Rs and is connect
Entering resistance R1 ~ access resistance R9 precision should be higher than that 1%.
The battery detection module for detecting battery capacity, battery are connected on the I/O mouth of the central control module
Detection module includes the resistance R4 and resistance R5 being connected in series, and the one end resistance R4 is connect with anode, the other end and resistance R5
Connection, the one end resistance R5 are connect with resistance R4, other end ground connection, the common end and central control module of resistance R4 and resistance R5
The voltage value of I/O mouthfuls of connections, output resistance R4 and resistance R5 are connected in parallel to capacitor with resistance R5 to central control module
C12 and diode D1, diode D1 plus earth, diode D1 cathode are connect with the common end of resistance R4 and resistance R5.
The beneficial effects of the present invention are: when carrying out communications cable measurement using the present invention, if breaking 1 line, other lines
Sequence measurement result is unaffected, can really reflect wire quality；It, also can accurate measurements if line sequence is arbitrarily intersected；Entirely
Principle is made of resistance and diode, and measuring speed is fast, while measurement result is not influenced by temperature and humidity, and stability is high.
Below in conjunction with the drawings and specific embodiments, the present invention will be further described.
Detailed description of the invention
Fig. 1 is measurement method schematic diagram of the present invention.
Fig. 2 is control circuit block diagram of the present invention.
Fig. 3 is MCU main control part circuit diagram of the present invention.
Fig. 4 is main part circuit diagram of the present invention.
Fig. 5 is key of the present invention and liquid crystal display partial circuit schematic diagram.
Fig. 6 is present system power pack circuit diagram.
Fig. 7 is hunting signal of the present invention generation and output par, c circuit diagram.
Fig. 8 is hunting of the present invention and external output interface partial circuit schematic diagram.
Fig. 9 is distal portions circuit diagram of the present invention.
Specific embodiment
The present embodiment is the preferred embodiment for the present invention, other its all principles and basic structure are identical or close as the present embodiment
As, within that scope of the present invention.
Please refer to attached drawing 1, the present invention protects a kind of communications cable open circuit, misconnection line sequence measurement method, and this method is to use
Cable one end to be measured is connected on host by host and distal, and the cable other end to be measured is connected on distal, in master
At machine, positive supply is connect by divider resistance Rs with one end of first switch K1, and the one end second switch K2 ground connection, distal is set
It is equipped with access resistance R1 ~ access resistance Rn, wherein n is the natural number more than or equal to 2, accesses resistance R1 ~ access resistance Rn mono-
End links together, and access resistance R1 ~ access resistance Rn other end successively connect respectively with a core wire of cable to be measured and (connects
Entering resistance R1 to connect with first core wire, access resistance R2 is connect with second core wire, and so on, access resistance Rn and n-th
Root core wire connection), access resistance R1 ~ access resistance Rn resistance value it is different, the other end of first switch K1 successively with it is to be measured
Each core wire of cable connects, and the second switch K2 other end successively connect with each core wire of cable to be measured, first switch K1 with
Second switch K2 cannot be connect with same root core wire simultaneously, appointed to take in the route between divider resistance Rs and access resistance and a little be made
For sampled point, by detecting sample amplitude when reproduced, judge the communications cable whether open circuit or misconnection, when sample amplitude when reproduced is equal to positive supply
When voltage, then illustrates the core wire of first switch K1 connection or the core wire open circuit of second switch K2 connection, second switch K2 is connected
On to another core wire, if sample amplitude when reproduced is not equal to positive voltage, illustrate the former core wire open circuit of second switch K2 connection,
When the corresponding default partial pressure value of the core wire that sample amplitude when reproduced is equal to first switch K1 connection, then illustrate that wiring is correct, if adopted
Sampling point voltage is not equal to the corresponding default partial pressure value of core wire of first switch K1 connection, then illustrates wiring error.
In order to keep the more accurate error of measurement result smaller, in the present embodiment, distinguish with access resistance R1 ~ access resistance Rn
Forward direction is connected in parallel to a diode, by diode that the access circuit of the core wire connecting with second switch K2 all the way is short
It connects.
In the present embodiment, cable both ends to be measured are connected separately with modular connection (usually male end connector), host and auxiliary
Corresponding connector (usually female end connector) is provided on distal end, in use, directly cable one end to be measured is plugged on host,
The other end is plugged on distal.
Incorporated by reference to referring to attached drawing 2 to attached drawing 9, the communications cable open circuit in the present invention, misconnection line sequence measuring system are mainly wrapped
The distal for including the host side for being connected to cable one end to be measured and being connected to the cable other end to be measured, host side include center control
Molding block, first switch module and second switch module pass through divider resistance Rs and positive electricity on the input terminal of first switch module
Source connection, the output end ground connection of second switch module, the output end of first switch module and the input terminal point of second switch module
Be not electrically connected with cable connection interface module to be measured, central control module respectively with first switch module and second switch module
Control terminal connection, central control module control first switch module and the work of second switch module, and distal is provided with access
Resistance R1 ~ access resistance Rn, wherein n is the natural number more than or equal to 2, and access resistance R1 ~ one end access resistance Rn is connected to
Together, access resistance R1 ~ access resistance Rn other end is successively electrically connected with the connection interface module of cable to be measured respectively, is accessed
Resistance R1 ~ access resistance Rn resistance value is different, the sampled point at the common end of first switch module and divider resistance Rs with
Central control module connection.
In the present embodiment, central control module (i.e. MCU) uses the single-chip microcontroller of model STM32F103RBT6, specific real
Shi Shi, can also be using the single-chip microcontroller of other models or series, internal included A/D conversion function, can be directly to sampled point electricity
Pressure carries out sampling identification.In the present embodiment, external memory is connected with by serial line interface on central control module, for saving
The operating parameter of system, in the present embodiment, external memory uses the EEPROM storage chip U1 of model AT24C02, specifically
It, can also be using the storage chip of other models or series when implementation.In the present embodiment, connect on the I/O mouth of central control module
It is connected to battery detection module, for detecting battery capacity, in the present embodiment, battery detection module includes the resistance R4 being connected in series
With resistance R5, the one end resistance R4 is connect with anode, and the other end is connect with resistance R5, and the one end resistance R5 is connect with resistance R4,
Other end ground connection, the I/O mouth connection of the common end and central control module of resistance R4 and resistance R5, output resistance R4 and resistance R5
Voltage value to central control module, central control module judges the number of battery capacity, the present embodiment by voltage value
In, capacitor C12 and diode D1, diode D1 plus earth, cathode and resistance R4 and resistance R5 are connected in parallel to resistance R5
Common end connection.
In the present embodiment, first switch module selects electronic analog swtich chip U5(to use as first switch K1), the
Two switch modules select electronic analog swtich chip U6(to use as second switch K2), electronic analog swtich chip U5 and electronics
What model SN74LV4051A was respectively adopted in analog switch chip U6 8 selects 1 duplex channel selector, electronic analog swtich chip
The enable end of U5 and a universaling I/O port of central control module connect, 8 input/output of electronic analog swtich chip U5
End (i.e. In/Out0 ~ In/Out7) is connect by interface module with a core wire in cable to be measured respectively, electronic analog swtich
The public input/output end (i.e. COM pin) of chip U5 is connect with divider resistance Rs, the control terminal of electronic analog swtich chip U5
It is connect respectively with the universaling I/O port of central control module；The enable end of electronic analog swtich chip U6 and central control module
One universaling I/O port connection, 8 input/output terminals (i.e. In/Out0 ~ In/Out7) of electronic analog swtich chip U6 are respectively
It is connect by interface module with a core wire in cable to be measured, the public input/output end of electronic analog swtich chip U6 is (i.e.
COM pin) it is grounded, the control terminal of electronic analog swtich chip U6 is connect with the universaling I/O port of central control module respectively.
It further include having the first auxiliary switch module and the second auxiliary switch module in the present embodiment, the first auxiliary switch mould
Block selects electronic analog swtich chip U14(to use as first switch K1), the second auxiliary switch module selects electronic simulation to open
Chip U15(is closed to use as second switch K2), electronic analog swtich chip U14 and electronic analog swtich chip U15 are adopted respectively
1 duplex channel selector is selected with the 8 of model SN74LV4051A, the enable end and center of electronic analog swtich chip U14 control
One universaling I/O port of module connects, 8 input/output terminal (i.e. In/Out0 ~ In/ of electronic analog swtich chip U14
Out7 it) is connect respectively by interface module with a core wire in cable to be measured (defeated only with one of them in the present embodiment
Enter/output port progress LINEG line measurement, when it is implemented, 8 input/output terminals can also be separately connected to survey line
Core wire in cable measures more cables), (i.e. COM draws at the public input/output end of electronic analog swtich chip U14
Foot) connect with divider resistance Rs, the control terminal of electronic analog swtich chip U14 respectively with the universaling I/O port of central control module
Connection；The enable end of electronic analog swtich chip U15 and a universaling I/O port of central control module connect, and electronic simulation is opened
Close 8 of chip U15 inputs output end (i.e. In/Out0 ~ In/Out7) respectively by one in interface module and cable to be measured
The connection of core wire (in the present embodiment, the measurement of LINEG line is carried out only with one of input/output end port, when it is implemented,
The core wire that 8 input/output terminals can also be separately connected in upper cable to be measured, measures more cables), electronic simulation
The public input/output end (i.e. COM pin) of switch chip U15 is grounded, the control terminal of electronic analog swtich chip U15 respectively with
The universaling I/O port of central control module connects.
Further include having linear measure longimetry module in the present embodiment, linear measure longimetry module include electronic switch module U3 and with it is non-
Door module U4, electronic switch module U3 select 2 tunnels four of model SN74LV4052A to select an analog switch chip, electronic switch
The enable end of module U3 and the universaling I/O port of central control module connect, X pin and Y the pin difference of electronic switch module U3
Connect with the com port (public port) of electronic analog swtich chip U5 and the com port (public port) of electronic analog swtich chip U14
It connecing, the control terminal (i.e. A pin and B pin) of electronic switch module U3 is connect with the universaling I/O port of central control module respectively, point
It is the resistance R7 of 10K that piezoresistance Rs, which selects resistance value, and the one end resistance R7 is connected on the X1 pin of electronic switch module U3, resistance R7
The other end is connect with positive supply, and the resistance R6 that resistance value is 100K is connected on the X2 pin of electronic switch module U3, and resistance R6 is another
One end is connect with positive supply, and the Y1 pin and Y2 pin of electronic switch module U3 connects with the non-inverting input terminal of amplifier U7A respectively
It connects, the inverting input terminal of amplifier U7A is connect with the output end of amplifier U7A, and the output end of amplifier U7A is voltage sample
Point, connect with central control module, uses using amplifier U7A as voltage follower.NAND gate module U4 selects model
The 4 NAND gate chips (being wherein integrated with 4 NAND gates) of 74HC00D, two input terminals (i.e. 1A pin and 1B of the first NAND gate
Pin) it (is the I/O mouth of central control module, output waveform in the present embodiment with the waveform delivery outlet of central control module
Signal CPU_WAVE) it connects, the output end (i.e. 1Y pin) of the first NAND gate is connect with the X0 pin of electronic switch module U3, the
An input terminal (i.e. 2A pin) for two NAND gates is connect with the X0 pin of electronic switch module U3, the second NAND gate another
Input terminal (i.e. 2B pin) is connect with the output end (i.e. 4Y pin) of the 4th NAND gate, and the output end of the second NAND gate is simultaneously with the
Two input terminals (i.e. 3A pin and 3B pin) of three NAND gates connect, the output end of third NAND gate and central control module
Waveform Input end (being the I/O mouth of central control module, input waveform signal CPU_TIME_IN in the present embodiment) connection, the
Two input terminals (i.e. 4A pin and 4B pin) of four NAND gates are connect with the Y0 pin of electronic switch module U3.
In the present embodiment, local detection interface, local detection interface and electronic analog swtich chip are additionally provided in host side
U8 connection, electronic analog swtich chip U8 select 1 duplex channel selector using the 8 of model SN74LV4051A, and electronic simulation is opened
One universaling I/O port of the enable end and central control module of closing chip U8 connects, and 8 of electronic analog swtich chip U8 are defeated
Enter/output end (i.e. In/Out0 ~ In/Out7) connect with a core wire in cable to be measured by interface module respectively, electronics
The public input/output end of analog switch chip U8 is grounded, and the control terminal of electronic analog swtich chip U8 is controlled with center respectively
The universaling I/O port of module connects.
It is also connected with hunting module in the present embodiment, on central control module, hunting instrument can be cooperated to carry out hunting operation, sought
Wire module includes that signal generating unit, enabled control unit and signal gating unit, the input terminal of signal generating unit are connected to
On the I/O mouth of central control module, hunting signal CPU_SCAN is generated by central control module, hunting signal CPU_SCAN passes through
It is divided into signal SIN_P and SIN_N after signal generating unit, in the present embodiment, signal generating unit uses transistor amplifier,
Signal gating unit uses two-way relay RL1, and signal SIN_P and SIN_N are connected to the normally-closed contact of relay RL1
On, two normally opened contacts of relay RL1 connect respectively with a core wire (in the present embodiment, the normally opened contact of relay RL1 point
Not in interface LINE4 and LINE5 connect), two commons of relay RL1 connect (this reality with a core wire respectively
Apply in example, the normally opened contact of relay RL1 respectively in interface LINE4 and LINE5 connect), go here and there on the power end of relay
It is connected to triode Q8, triode exports enable signal S_EN2, and signal SIN_P and SIN_N are accessed in core wire, carries out hunting, no
When the hunting needed, signal SIN_P and SIN_N are shorted by enable signal, are at unjust open state, signal SIN_P
It is connect respectively with the I/O of central control module mouth with SIN_N, inputs to central control module CPU_ADC_N signal and CPU_
ADC_P signal.Enabled control unit includes analog switch chip U12 and analog switch chip U13, analog switch chip U12 and
Analog switch chip U13 is 4 path analoging switch, in the control terminal of analog switch chip U12 and analog switch chip U13 respectively
It is connected with control triode, the base stage of two control triodes connect with the I/O of central control module mouth respectively, controls by center
Molding block output control signal S_EN 0 and control signal S_EN 1, controls the on-off of two triodes, thus the enabled letter of input
Number analog switch chip U12 and analog switch chip U13, signal SIN_N is given to be connected to four of analog switch chip U12 inputs
On end, signal SIN_P is connected on four input terminals of analog switch chip U13, analog switch chip U12 and analog switch core
The output end of piece U13 is connect with a core wire respectively, when using hunting function, controls analog switch core by enabled control unit
Piece U12 and analog switch chip U13, hunting signal is input in cable, when not using hunting signal, can control list by making
Member control analog switch chip U12 and analog switch chip U13 is in close state.
In the present embodiment, key module is also connected on central control module, key module uses key switch.This implementation
In example, display screen drive module is also connected on central control module, display screen drive module uses LCD interface, passes through center
Control module driving LCD display is shown.
In the present embodiment, using lithium battery as power supply, it is connected with power supply terminal on lithium battery and gives lithium battery charging, this reality
It applies in example, lithium battery out-put supply is converted by+3.3V using the voltage stabilizing chip U9 of model AMS1117-3.3V and is powered,
Lithium battery out-put supply is converted into+5V using the voltage stabilizing chip U10 of model 78L05 to be powered, using model
Lithium battery out-put supply is converted into -5V and is powered by the voltage stabilizing chip U11 of TPS60400.
In the present embodiment, distal is illustrated by taking 9 resistance as an example, can at most measure 9 core cables, specific implementation
When, route can also be increased according to this principle, carry out more route surveys, in the present embodiment, distal is provided with access electricity
R1 ~ access resistance R9 is hindered, resistance R1 resistance value is 4.02K, and resistance R2 resistance value is 6.8K, and resistance R3 resistance value is 16K, resistance R4 resistance value
For 20K, resistance R5 resistance value is 24K, and resistance R6 resistance value is 27K, and resistance R7 resistance value is 33K, and resistance R8 resistance value is 40.2K, resistance
The resistance value of R9 is 47K, and access resistance R1 ~ access resistance R9 precision should be higher than that 1%.With resistance R1 ~ access resistance R9 points of access
It is not connected in parallel to a bypass diode, in the present embodiment, bypass diode selects the germanium tube (tube voltage drop of model 1N60P
For 0.2V).
In the use of the present invention, there are several types of usage modes:
One, distally to line line sequence measurement method: host side and distal are connected to the both ends of cable to be measured, electronic cutting
It closes module U3 and selects x=x1, y=y1, first switch K1 are connected to Line 1, and second switch K2 is connected to No. 2 lines, at this point, by positive supply
VCC, sampling resistor Rs, cable Line 1, No. 1 cell resistance R1 of distal, No. 2 cell diodes and cell resistance R2 to be measured
No. 2 lines of cable in parallel, to be measured are connected to ground using second switch K2, constitute a current loop, the partial pressure value of AD sampled point
Are as follows:, VCC, Vd(diode drop in formula), Rs be constant, then the voltage at sampled point is only determined by the resistance value of resistance R1, choosing
It selects different wire size resistance (R1 ~ R9) and respectively corresponds wire size 1-9, so just can know that first by the voltage of measurement AD sampled point
Which single line of wire size selected by switch K1 and distal connects, and here it is the principles of measurement line sequence；
First switch K1 to a certain wire size of gating, second switch K2 will gate remaining all wire sizes and successively constitute back every time
Road, it is ensured that, also can correct measurement when only two core wire；
When some loop open circuit, the voltage of AD sampled point and then can judge current wire size for open circuit close to the value of VCC.
Two, local to fulfil line sequence measurement method: cable to be measured is both connected to host side, cable one end to be measured be connected to
It (is electrically connected with electronic analog swtich chip U5, is opened electronic analog swtich chip U5 as first in survey line cable connecting interface
Close K1), the other end, which is connected on local detection interface, (to be electrically connected with electronic analog swtich chip U8, by electronic analog swtich
Chip U8 is got to as second switch K2), electronic switch module U3 selection x=x2, y=y2, first switch K1 and second switch K2
On same cable, if the voltage of AD sampled point close to 0V, illustrates that this core wire is access, the voltage of AD sampled point is close
The value of VCC, and then current wire size can be judged for open circuit.
Three, length testing mode: electronic switch module U3 selects x=x0, and y=y0, MCU generate an impulse waveform, pass through
NAND gate module U4(dual input NAND gate) driving pulse that generates and line capacitance collective effect, exportable one with electric between line
The pulsewidth for holding variation exports CPU_TIME_IN, after which accesses single-chip microcontroller, by calculating pulsewidth length it can be concluded that wire length
Degree.
When carrying out communications cable measurement using the present invention, if breaking 1 line, other line sequence measurement results are unaffected,
It can really reflect wire quality；It, also can accurate measurements if line sequence is arbitrarily intersected；Entire principle is by resistance and diode structure
At measuring speed is fast, while measurement result is not influenced by temperature and humidity, and stability is high.
Claims (10)
1. a kind of open circuit of the communications cable, misconnection line sequence measurement method, it is characterized in that: the measurement method is using host and auxiliary
Distal end is helped, cable one end to be measured is connected on host, the cable other end to be measured is connected on distal, at host, just
Power supply is connect by divider resistance Rs with one end of first switch K1, and the one end second switch K2 ground connection, distal, which is provided with, to be connect
Enter resistance R1 ~ access resistance Rn, wherein n is the natural number more than or equal to 2, access resistance R1 ~ access one end resistance Rn connection
Together, access resistance R1 ~ access resistance Rn other end is successively connect with a core wire of cable to be measured respectively, accesses resistance R1
The resistance value of ~ access resistance Rn is different, and the other end of first switch K1 is successively connect with each core wire of cable to be measured, and second
The switch K2 other end is successively connect with each core wire of cable to be measured, first switch K1 and second switch K2 cannot simultaneously with it is same
Appoint in the connection of root core wire, divider resistance Rs and the route accessed between resistance and takes a little as sampled point, by detecting sampled point
Voltage judges whether open circuit or misconnection then illustrate first switch K1 when sample amplitude when reproduced is equal to positive voltage to the communications cable
The core wire of connection or the core wire open circuit of second switch K2 connection, second switch K2 are connected on another core wire, if sampled point
Voltage is not equal to positive voltage, then illustrates the former core wire open circuit of second switch K2 connection, opens when sample amplitude when reproduced is equal to first
When closing the corresponding default partial pressure value of core wire of K1 connection, then illustrate that wiring is correct, if sample amplitude when reproduced is not equal to first switch
The corresponding default partial pressure value of the core wire of K1 connection, then illustrate wiring error.
2. the communications cable according to claim 1 open circuit, misconnection line sequence measurement method, it is characterized in that: with access resistance R1 ~
Forward direction is connected in parallel to a bypass diode to access resistance Rn respectively.
3. a kind of communications cable open circuit, misconnection line sequence measuring system, it is characterized in that: the system includes being connected to cable to be measured
The host side of one end and the distal for being connected to the cable other end to be measured, host side includes central control module, first switch
Module and second switch module are connect by divider resistance Rs with positive supply on the input terminal of first switch module, second switch
The output end of module is grounded, and the output end of first switch module is connect with cable to be measured respectively with the input terminal of second switch module
Interface module electrical connection, central control module are connect with the control terminal of first switch module and second switch module respectively, center
Control module controls first switch module and the work of second switch module, and distal is provided with access resistance R1 ~ access resistance
Rn, wherein n is the natural number more than or equal to 2, and access resistance R1 ~ one end access resistance Rn links together, and accesses resistance R1
~ access resistance Rn the other end is successively electrically connected with the connection interface module of cable to be measured respectively, accesses resistance R1 ~ access resistance
The resistance value of Rn is different, and the sampled point and central control module at the common end of first switch module and divider resistance Rs connect
It connects.
4. communications cable open circuit according to claim 3, misconnection line sequence measuring system, it is characterized in that: described first opens
It closes module and selects electronic analog swtich chip U5, second switch module selects electronic analog swtich chip U6, electronic analog swtich
One universaling I/O port of the enable end of chip U5 and central control module connects, and 8 inputs of electronic analog swtich chip U5/
Output end passes through interface module respectively and connect with a core wire in cable to be measured, and electronic analog swtich chip U5's is public defeated
Out/input terminal is connect with divider resistance Rs, and the control terminal of electronic analog swtich chip U5 is general with central control module respectively
I/O mouthfuls of connections；The enable end of electronic analog swtich chip U6 and a universaling I/O port of central control module connect, electronic die
8 input/output terminals of quasi- switch chip U6 pass through interface module respectively and connect with a core wire in cable to be measured, electronic die
The public input/output end ground connection of quasi- switch chip U6, the control terminal of electronic analog swtich chip U6 control mould with center respectively
The universaling I/O port of block connects.
5. communications cable open circuit according to claim 4, misconnection line sequence measuring system, it is characterized in that: the system is also
It include the first auxiliary switch module and the second auxiliary switch module, the first auxiliary switch module selects electronic analog swtich chip
U14, the second auxiliary switch module select electronic analog swtich chip U15, the enable end and center of electronic analog swtich chip U14
One universaling I/O port of control module connects, and 8 input/output terminals of electronic analog swtich chip U14 pass through interface mould respectively
Block is connect with a core wire in cable to be measured, the public input/output end of electronic analog swtich chip U14 and divider resistance Rs
Connection, the control terminal of electronic analog swtich chip U14 are connect with the universaling I/O port of central control module respectively；Electronic simulation is opened
One universaling I/O port of the enable end and central control module of closing chip U15 connects, and 8 of electronic analog swtich chip U15 are defeated
Enter output end pass through interface module respectively and connect with a core wire in cable to be measured, electronic analog swtich chip U15's is public
Input/output end ground connection, the control terminal of electronic analog swtich chip U15 are connect with the universaling I/O port of central control module respectively.
6. communications cable open circuit according to claim 3, misconnection line sequence measuring system, it is characterized in that: the system is also
It include linear measure longimetry module, linear measure longimetry module includes electronic switch module U3 and NAND gate module U4, electronic switch module
The universaling I/O port of the enable end of U3 and central control module connects, the X pin and Y pin of electronic switch module U3 respectively with electricity
The com port of sub- analog switch chip U5 connects, the control terminal of electronic switch module U3 respectively with general purpose I/O of central control module
Mouth connection, the one end divider resistance Rs are connected on the X1 pin of electronic switch module U3, the divider resistance Rs other end and positive supply
Connection, for the Y1 pin of electronic switch module U3 as voltage sample point output end, NAND gate module U4 uses 4 NAND gate chips,
Two input terminals of the first NAND gate are connect with the waveform delivery outlet of central control module, the output end and electricity of the first NAND gate
The X0 pin of sub switch module U3 connects, and an input terminal of the second NAND gate is connect with the X0 pin of electronic switch module U3,
Another input terminal of second NAND gate is connect with the output end of the 4th NAND gate, the output end of the second NAND gate while and third
Two input terminals of NAND gate connect, and the output end of third NAND gate and the Waveform Input end of central control module connect, and the 4th
Two input terminals of NAND gate are connect with the Y0 pin of electronic switch module U3.
7. communications cable open circuit according to claim 6, misconnection line sequence measuring system, it is characterized in that: the electronic cutting
It closes and is connected with voltage follower on the Y1 pin of module U3, voltage follower uses amplifier U7A, the Y1 of electronic switch module U3
Pin is connect with the non-inverting input terminal of amplifier U7A, and the inverting input terminal of amplifier U7A is connect with the output end of amplifier U7A,
The output end of amplifier U7A is voltage sample point output end, is connect with central control module.
8. communications cable open circuit according to claim 3, misconnection line sequence measuring system, it is characterized in that: the host side
It is equipped with local detection interface, local detection interface is connect with electronic analog swtich chip U8, and electronic analog swtich chip U8 is adopted
1 duplex channel selector, the enable end of electronic analog swtich chip U8 and a universaling I/O port of central control module are selected with 8
Connection, 8 input/output terminals of electronic analog swtich chip U8 pass through a core wire in interface module and cable to be measured respectively
Connection, electronic analog swtich chip U8 public input/output end ground connection, the control terminal of electronic analog swtich chip U8 respectively with
The universaling I/O port of central control module connects.
9. communications cable open circuit according to claim 3, misconnection line sequence measuring system, it is characterized in that: the auxiliary is remote
End includes access resistance R1 ~ access resistance R9, and resistance R1 resistance value is 4.02K, and resistance R2 resistance value is 6.8K, and resistance R3 resistance value is
16K, resistance R4 resistance value are 20K, and resistance R5 resistance value is 24K, and resistance R6 resistance value is 27K, and resistance R7 resistance value is 33K, resistance R8 resistance
Value is 40.2K, and the resistance value of resistance R9 is 47K, and divider resistance Rs resistance value is 10K, resistance Rs and access resistance R1 ~ access resistance R9
Precision should be higher than that 1%.
10. communications cable open circuit according to claim 3, misconnection line sequence measuring system, it is characterized in that: the center control
The battery detection module for detecting battery capacity is connected on the I/O mouth of molding block, battery detection module includes being connected in series
Resistance R4 and resistance R5, the one end resistance R4 connect with anode, and the other end is connect with resistance R5, the one end resistance R5 and resistance
R4 connection, other end ground connection, the I/O mouth connection of the common end and central control module of resistance R4 and resistance R5, output resistance R4
Voltage value with resistance R5 is connected in parallel to capacitor C12 and diode D1, diode with resistance R5 to central control module
D1 plus earth, diode D1 cathode are connect with the common end of resistance R4 and resistance R5.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109799419A (en) * | 2019-01-29 | 2019-05-24 | 国家电网有限公司 | A kind of secondary error connection analyzer of exchange |
| CN112180242A (en) * | 2020-10-15 | 2021-01-05 | 东莞飞思凌通信技术有限公司 | Method and device for fault diagnosis of DDR (double data Rate) interface circuit of high-density chip |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102012465A (en) * | 2010-01-21 | 2011-04-13 | 柳州市达迪通信设备有限公司 | Wire order test method |
| CN102608456A (en) * | 2012-03-02 | 2012-07-25 | 华为技术有限公司 | Parallel operation line failure detection device and system |
| CN103115561A (en) * | 2013-01-16 | 2013-05-22 | 林烨 | Cable length testing device and method |
| CN203148462U (en) * | 2013-01-16 | 2013-08-21 | 林烨 | Multifunctional video monitoring cable tester |
| CN103994713A (en) * | 2014-06-16 | 2014-08-20 | 雷鸣 | Novel cable length measuring method |
| CN104237717A (en) * | 2013-06-14 | 2014-12-24 | 珠海格力电器股份有限公司 | Static bracelet monitor and static export system |
| CN107870283A (en) * | 2017-11-06 | 2018-04-03 | 山东谦恒电子科技有限公司 | BMS wiring testing devices and method |
-
2018
- 2018-11-13 CN CN201811344638.1A patent/CN109254224A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102012465A (en) * | 2010-01-21 | 2011-04-13 | 柳州市达迪通信设备有限公司 | Wire order test method |
| CN102608456A (en) * | 2012-03-02 | 2012-07-25 | 华为技术有限公司 | Parallel operation line failure detection device and system |
| WO2013127221A1 (en) * | 2012-03-02 | 2013-09-06 | 华为技术有限公司 | Parallel operation wire fault detection device and system |
| CN103115561A (en) * | 2013-01-16 | 2013-05-22 | 林烨 | Cable length testing device and method |
| CN203148462U (en) * | 2013-01-16 | 2013-08-21 | 林烨 | Multifunctional video monitoring cable tester |
| CN104237717A (en) * | 2013-06-14 | 2014-12-24 | 珠海格力电器股份有限公司 | Static bracelet monitor and static export system |
| CN103994713A (en) * | 2014-06-16 | 2014-08-20 | 雷鸣 | Novel cable length measuring method |
| CN107870283A (en) * | 2017-11-06 | 2018-04-03 | 山东谦恒电子科技有限公司 | BMS wiring testing devices and method |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109799419A (en) * | 2019-01-29 | 2019-05-24 | 国家电网有限公司 | A kind of secondary error connection analyzer of exchange |
| CN112180242A (en) * | 2020-10-15 | 2021-01-05 | 东莞飞思凌通信技术有限公司 | Method and device for fault diagnosis of DDR (double data Rate) interface circuit of high-density chip |
| CN113064770A (en) * | 2021-03-04 | 2021-07-02 | 山东英信计算机技术有限公司 | A device, system and method for preventing the wrong connection of slimline cables |
| CN113075589A (en) * | 2021-03-25 | 2021-07-06 | 广东工业大学 | Integrated line sequence testing device and method |
| CN113640710A (en) * | 2021-08-13 | 2021-11-12 | 深圳市新威尔电子有限公司 | Channel crossing automatic detection method |
| CN113640710B (en) * | 2021-08-13 | 2024-04-09 | 深圳市新威尔电子有限公司 | Automatic detection method for channel crossing |
| CN114646903A (en) * | 2022-03-15 | 2022-06-21 | 永州市诺方舟电子科技有限公司 | Air switch hunting instrument with socket line sequence detection function and detection method |
| CN115389979A (en) * | 2022-10-28 | 2022-11-25 | 海的电子科技(苏州)有限公司 | Detection circuit and detection method for signal transmission line, controller and storage medium |
| CN115389979B (en) * | 2022-10-28 | 2023-01-13 | 海的电子科技(苏州)有限公司 | Detection circuit and detection method for signal transmission line, controller and storage medium |
| CN116299071A (en) * | 2023-05-18 | 2023-06-23 | 天津博益气动股份有限公司 | Pressure sensor prevents wrong line detection circuitry that connects |
| WO2025044584A1 (en) * | 2023-08-30 | 2025-03-06 | 天津瑞发科半导体技术有限公司 | Cable state testing circuit |
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