CN109244077B

CN109244077B - Method for manufacturing three-dimensional memory

Info

Publication number: CN109244077B
Application number: CN201811031283.0A
Authority: CN
Inventors: 肖莉红; 胡斌
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2018-09-05
Filing date: 2018-09-05
Publication date: 2020-07-03
Anticipated expiration: 2038-09-05
Also published as: CN109244077A

Abstract

The invention provides a method for manufacturing a three-dimensional memory, which comprises the following steps: providing a semiconductor structure comprising a dummy step structure and a stack structure, the dummy step structure comprising a plurality of steps, each step having a different height, the stack structure conformally formed on the dummy step structure, the stack structure comprising a plurality of first material layers and a plurality of second material layers alternately stacked; removing at least part of the stacked structure to form exposed contact surfaces on the plurality of first material layers; forming a plurality of conductive contacts that respectively contact the plurality of first material layers through the contact surfaces; covering an insulating layer on the stacked structure; forming a plurality of contact portions penetrating to the plurality of conductive contacts, respectively, on the insulating layer; the number of the stacked layers of the stacked structure on the Nth step is different from the number of the stacked layers on the N +1 th step, and N is an integer greater than or equal to 1.

Description

Method for manufacturing three-dimensional memory

Technical Field

The invention mainly relates to the field of semiconductor manufacturing, in particular to a manufacturing method of a three-dimensional memory.

Background

To overcome the limitations of the two-dimensional memory device, the industry has developed a memory device having a three-dimensional (3D) structure to increase integration density by arranging memory cells three-dimensionally over a substrate.

In a three-dimensional memory device such as a 3D NAND flash memory, a memory array may include a core (core) region and a staircase region. The step region is used for leading out a contact part of a gate layer in each layer of the memory array. These gate layers are used as word lines of the memory array to perform programming, erasing, reading, etc.

In the manufacturing process of the 3D NAND flash memory, contact holes are formed on all levels of stepped structures in a stepped area in an etching mode, and then the contact holes are filled, so that electric signals of a grid layer are led out. In the actual production process, because the number of the 3D-NAND flash memory ladder layers is large, in the step of etching the contact hole, in order to ensure that the lower-layer ladder can be smoothly led out, the upper-layer ladder is easily etched by over etching (OverEtch), and etching Through (Punch Through) occurs, so that the process requirements cannot be met, and the product yield is reduced.

In order to solve the above problem, it is often necessary to perform light irradiation and etching a plurality of times, thereby reducing the depth difference at each etching.

Disclosure of Invention

The invention aims to solve the technical problem that the method for manufacturing the three-dimensional memory can overcome the problems of etching defects of word line connecting areas and the like, and does not need to carry out multiple times of illumination and etching.

In order to solve the technical problem, the invention provides a method for manufacturing a three-dimensional memory, which comprises the following steps: providing a semiconductor structure comprising a dummy step structure and a stack structure, the dummy step structure comprising a plurality of steps, each step having a different height, the stack structure conformally formed on the dummy step structure, the stack structure comprising a plurality of first material layers and a plurality of second material layers alternately stacked; removing at least part of the stacked structure to form exposed contact surfaces on the plurality of first material layers; after removing at least part of the stacked structures, the number of the stacked layers of the stacked structures on the Nth level of the step is different from the number of the stacked layers on the N +1 th level of the step, and N is an integer greater than or equal to 1; forming a plurality of conductive contacts that respectively contact the plurality of first material layers through the contact surfaces; covering an insulating layer on the stacked structure; forming a plurality of contact portions penetrating to the plurality of conductive contacts, respectively, on the insulating layer.

In an embodiment of the invention, the first material layer is a dummy gate layer or a dummy gate layer, and the second material layer is a dielectric layer.

In an embodiment of the invention, the conductive contact is made of the same material as the gate layer.

In an embodiment of the invention, the contact surface is an upper surface of the first material layer, and the thickness of the conductive contact is equal to a thickness of a single layer of the second material layer.

In an embodiment of the invention, the contact surface is an inner side surface formed by removing at least a part of the thickness of the first material layer, and the thickness of the conductive contact is greater than that of a single layer of the second material layer.

In an embodiment of the invention, a method of forming the dummy step structure is a subtractive etching method.

In an embodiment of the invention, the step of removing at least part of the stacked structure to form the exposed contact surface on the plurality of first material layers includes: removing at least part of the stacked structure to expose part of the surface of the plurality of second material layers; and removing at least part of the second material layer at the part of the surface to expose the contact surface on the first material layer.

In an embodiment of the invention, a method of removing at least a portion of the stacked structure to expose a portion of the surface of the plurality of second material layers is a subtractive etching method, and a direction of the subtractive etching is toward a center direction of the semiconductor structure.

In an embodiment of the present invention, the step of removing at least a portion of the second material layer at the portion of the surface to expose the contact surface on the first material layer includes: and covering photoresist on the exposed dielectric layer and performing dry etching on the photoresist.

In an embodiment of the present invention, the dry etching may be single layer dry etching.

In an embodiment of the present invention, the step of forming a plurality of conductive contacts respectively contacting the plurality of first material layers through the contact surfaces includes: covering the first material layer with a conductive contact and removing the conductive contact on the second material layer.

In an embodiment of the present invention, after forming the contact portion penetrating to the conductive contact on the insulating layer, the method further includes: removing the dummy gate layer to form a gap between the dielectric layers and a gate layer in the gap.

In an embodiment of the present invention, forming a peripheral device under the dummy step structure is further included.

The invention has the following advantages: the invention provides a method for manufacturing a three-dimensional memory, which comprises a virtual step structure and a stack structure, wherein a preformed conductive contact is arranged on the stack structure, so that the thickness of a gate layer in the stack structure can be increased, and the risk of etching through is greatly reduced because the gate layer is increased in thickness and is not easy to etch through.

Drawings

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:

FIGS. 1A-1F are flow diagrams of a method of fabricating a three-dimensional memory.

Fig. 2A-2B are schematic structural diagrams of a three-dimensional memory.

Fig. 3 is a flowchart of a method for fabricating a three-dimensional memory according to an embodiment of the invention.

Fig. 4A-4F are cross-sectional views illustrating exemplary processes of a method for fabricating a three-dimensional memory according to an embodiment of the invention.

Fig. 5A-5L are schematic cross-sectional views illustrating the formation of exposed contact surfaces on a plurality of first material layers according to an embodiment of the invention.

Fig. 6 is a schematic structural diagram of a three-dimensional memory according to an embodiment of the invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.

In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

As introduced in the background, in a three-dimensional memory device such as a 3D NAND flash memory, a memory array may include a core (core) region and a staircase region. The step region is used for leading out a contact part of a gate layer in each layer of the memory array. These gate layers are used as word lines of the memory array to perform programming, erasing, reading, etc.

FIGS. 1A-1F are flow diagrams of a method of fabricating a three-dimensional memory. The manufacturing method mainly comprises the step of etching and forming a contact hole on each step. The process of forming the contact hole includes forming a stacked structure 110 having dummy gate layers 101 and dielectric layers 102 stacked alternately as shown in fig. 1A, forming a stepped structure at the edge of the stacked structure 110 as shown in fig. 1B, covering an insulating layer 103 on the stacked structure 110 as shown in fig. 1C, and replacing the dummy gate layer 101 with a gate layer 104 as shown in fig. 1D, and finally forming a contact hole 106 through an etch mask 105 and filling the contact hole 106 to form a contact portion 107 as shown in fig. 1E and 1F, respectively.

As shown in fig. 1D, the step-region gate layer 104 is thin and is easily over-etched in this method. As shown in fig. 2A, when the contact hole 106 is etched, due to the large depth difference, when the deepest contact hole is etched to a right position, the shallowest contact hole may be etched through to cause a short circuit. In order to avoid over-etching of the shallowest contact hole, the vertical through holes corresponding to the metal gate layers in different regions are usually etched in a segmented manner, as shown in fig. 2B, the method needs to perform multiple steps of photoetching and etching, the cost and the time cost are high, the mass production rate is seriously influenced, and the more the number of stacked layers of the memory cells is, the more the photoetching and etching processes need to be performed.

Fig. 3 is a flowchart of a method for fabricating a three-dimensional memory according to an embodiment of the invention. Fig. 4A-4F are cross-sectional views illustrating exemplary processes of a method for fabricating a three-dimensional memory according to an embodiment of the invention. A method of fabricating a three-dimensional memory according to the present embodiment will be described with reference to fig. 3 to 4F.

In step 302, a semiconductor structure is provided.

The semiconductor structure is at least a portion of a structure that will be used in subsequent processing to ultimately form a three-dimensional memory device. The semiconductor structure may include an array region (array), which may include a core region (core) and a step region (SS). The core region is a region including memory cells, and the staircase region is a region including word line connection circuits. The array region may have a substrate and a stack layer, and a channel hole array may be formed on the stack structure of the core region, and a dummy channel hole array may be formed on the stack structure of the stepped region, the stack structure including first material layers and second material layers alternately stacked, as viewed in a vertical direction. The first material layer may be a dummy gate layer or a gate layer. The second material layer may be a dielectric layer. For simplicity, the first material layer is a dummy gate layer, and the second material layer is a dielectric layer.

In the cross-sectional view of the semiconductor structure 400a illustrated in fig. 4A, the semiconductor structure 400a may include a dummy step structure 410 and a stack structure 420. For simplicity, other regions of the semiconductor structure in the horizontal direction, such as the core region, are not shown. And also other layers of the staircase structure in the vertical direction, such as the substrate, are not shown. The virtual stair-step structure 410 includes

multi-step steps

410a, 410b, 410c, and 410 d. The

multi-step steps

410a, 410b, 410c, and 410d have different heights, i.e., the top surface of each step is located at a different height. The higher the height of the top surface of the step, the larger the number of steps. The height of the dummy step structures 410 may increase in a direction away from the center of the semiconductor structure 400a or may decrease in a direction away from the center of the semiconductor structure 400 a. The central direction of the semiconductor structure refers to the direction in which the core region is located in the semiconductor structure. Preferably, as shown in fig. 4A, the height of the dummy step structure 410 increases in a direction away from the center of the semiconductor structure 400 a. The core region of the semiconductor structure 400a in fig. 4A is on the left side, and the direction away from the center of the semiconductor structure 400a is from left to right. The method of forming the dummy step structure 410 may be trim etch (trim/etch). Performing the trim etch in a direction away from the center of the semiconductor structure 400a may form a dummy step structure 410 having a height that increases in a direction away from the center of the semiconductor structure 400 a. It is appreciated that the trim etch in a direction closer to the center of the semiconductor structure 400a may form a dummy step structure 410 having a height that decreases in a direction away from the center of the semiconductor structure 400 a. The stack structure 420 is conformally formed on the dummy step structure 410. The stack structure 420 includes a plurality of dummy gate layers 420a and a plurality of dielectric layers 420b that are alternately stacked. The number of layers of the plurality of dummy gate layers 420a and the plurality of dielectric layers 420b in the stacked structure 420 depends on the number of layers (e.g., 32 or 64 layers) of the three-dimensional memory device to be fabricated. Fig. 4A shows that stacked structure 420 has 6 dummy gate layers 420a and 6 dielectric layers 420b, which however does not represent the number of layers of actual dummy gate layers 420a and dielectric layers 420 b. A method of forming the stack structure 420 on the dummy step structure 420 may be to alternately deposit the dummy gate layer 420a and the dielectric layer 420 b. The method for depositing the dummy gate Layer 420a and the dielectric Layer 420b may be Atomic Layer Deposition (ALD). The shape of the deposited dummy gate layer 420a and dielectric layer 420b of each layer is the same as the shape of the dummy step structure 420.

In an embodiment of the present invention, the material of the dummy gate layer 420a may be silicon nitride. The material of the dielectric layer 420b is, for example, silicon oxide.

Although exemplary configurations of the initial semiconductor structure are described herein, it will be appreciated that one or more features may be omitted, substituted, or added to the semiconductor structure. In addition, the materials of the illustrated layers are merely exemplary, and other materials that are available in charge storage (CTF) three-dimensional NAND memories may be selected for the dummy gate layer 420a and the dielectric layer 420 b. For example, the dummy gate layer 420a and the dielectric layer 420b may also be a combination of silicon oxide and (undoped) polysilicon or amorphous silicon, a combination of silicon oxide or silicon nitride and amorphous carbon, and the like.

At step 304, at least a portion of the stacked structure is removed to form exposed contact surfaces on the plurality of first material layers.

At least part of the stacked structure is removed, and exposed contact surfaces are formed on the first material layers. After removing at least part of the stacked structures, the number of stacked layers of the stacked structures on the Nth step is different from the number of stacked layers on the (N + 1) th step, and N is an integer greater than or equal to 1. The number of stacks on a step refers to the number of complete stacks. The step of removing at least part of the stacked structure to form an exposed contact surface on the plurality of first material layers may comprise removing at least part of the stacked structure to expose part of a surface of the plurality of second material layers and removing at least part of the second material layers at part of the surface to expose the contact surface on the first material layers. The method of removing at least a portion of the stacked structure to expose a portion of the surface of the plurality of second material layers may be a subtractive etching process. The step of removing at least part of the second material layer at part of the surface to expose the contact surface on the first material layer may comprise covering the exposed second material layer with a photoresist and dry etching the photoresist. The dry etch may be a single layer dry etch. The step of forming the contact surface on the exposed first material layer will be described in detail later. The contact surface may be an upper surface of the first material, or an inner side surface formed by removing at least a portion of the thickness of the first material layer.

In the cross-sectional view of the semiconductor structure 400B illustrated in fig. 4B, a portion of the stacked structure 420 in the semiconductor structure 400a is removed, and the plurality of dummy gate layers 420a form exposed contact surfaces 420 c. The step of removing at least a portion of the stack structure 420 to form an exposed contact surface 420c on the plurality of dummy gate layers 420a may include removing at least a portion of the stack structure 420 to expose a portion of the surface of the plurality of dielectric layers 420b and removing at least a portion of the dielectric layer 420b at the portion of the surface to expose the contact surface 420c on the dummy gate layer 420 a. The method of removing at least a portion of the stacked structure to expose a portion of the surface of the plurality of dielectric layers 420b may be a subtractive etching process, the subtractive etching process being directed toward the center of the semiconductor structure. The central direction of the semiconductor structure refers to the direction in which the core region is located in the semiconductor structure. The core region of the semiconductor structure 400B in fig. 4B is on the left side, and the direction toward the center of the semiconductor structure 400B is from right to left. Removing at least a portion of the dielectric layer 420b at a portion of the surface to expose the contact surface on the dummy gate layer 420a may include covering the exposed dielectric layer 420b with a photoresist and dry etching the photoresist. The dry etch may be a single layer dry etch. In fig. 4B, the contact surface 420c is an inner surface formed by removing the entire thickness of the dummy gate layer 420 a. It is understood that the contact surface 420c may also be an upper surface of the dummy gate layer 420a or an inner side surface formed by removing a portion of the thickness of the dummy gate layer 420 a. The position of the contact face 420c can be controlled by the depth of the etching. For example, when the etching depth is the thickness of the single dielectric layer 420b, the contact surface 420c is the upper surface of the dummy gate layer 420 a. When the etching depth exceeds the thickness of the single-layer dielectric layer 420b and is less than the thickness of the single-layer dielectric layer 420b plus the single-layer dummy gate layer 420a, the contact surface 420c is an inner side surface of the dummy gate layer 420 a. After removing at least part of the stacked structure 420, the number of stacked layers of the stacked structure 420 on the nth step is different from the number of stacked layers on the (N + 1) th step, where N is an integer greater than or equal to 1. The number of stacks on a step refers to the number of complete stacks. For example, as shown in fig. 4B, after removing at least part of the stack structure 420, the number of stacks on the step 410a is 8(4 gate layers 420a and 4 dielectric layers 420B), the number of stacks on the step 410B is 6(3 gate layers 420a and 3 dielectric layers 420B), the number of stacks on the step 410c is 4(2 gate layers 420a and 2 dielectric layers 420B), and the number of stacks on the step 410d is 0. As can be seen from fig. 4B, the number of stacked layers of the stacked structure 420 on the nth step (e.g.,

steps

410a, 410B, 410c) is different from the number of stacked layers on the (N + 1) th step (e.g., steps 410B, 410c, 410 d). Further, in fig. 4B, the height of the dummy step structure 410 increases in a direction away from the center of the semiconductor structure 410B, and the number of stacked layers of the stacked structure 420 on the nth step is greater than the number of stacked layers on the N +1 th step. It is understood that, correspondingly, if the height of the dummy step structure 410 decreases in the direction away from the center of the semiconductor structure 410b, the number of stacked layers of the stacked structure 420 on the nth step is greater than the number of stacked layers on the N +1 th step.

At step 306, a plurality of conductive contacts are formed that respectively contact the plurality of first material layers through the contact surfaces.

In this step, a plurality of conductive contacts are formed that respectively contact the plurality of first material layers through the contact surfaces. Forming a plurality of conductive contacts that respectively contact the plurality of first material layers through the contact surfaces may include covering the first material layers with a conductive layer and removing the conductive layer on the second material layers. The method of covering the first material layer with the conductive layer may be an atomic layer deposition method. The thickness of the conductive contact may be slightly greater than the distance between the contact surface and the second material layer corresponding to the contact surface. The conductive contacts may be of the same material as the gate layer, e.g., both being tungsten metal. The conductive layer on the second material layer is then removed to insulate the conductive contacts from each other. The method of removing the conductive layer on the second material layer may be wet etching. The etchant for the wet etch may be phosphoric acid. To this end, each first material layer has a conductive contact contacted thereon.

In the cross-sectional view of the semiconductor structure 400C illustrated in fig. 4C, the surface of the semiconductor structure 400C is covered with the conductive layer 430, and the conductive layer 430 fills the etched recesses of the dummy gate layer 420a to form a plurality of conductive contacts 430a contacting the plurality of dummy gate layers 420a through the contact surface 420C. The method of forming the conductive layer 430 may be an atomic layer deposition method. The thickness of the conductive contact 430a is slightly greater than the distance from the contact surface 420c to the dielectric layer 420b corresponding to the contact surface 420 c. The conductive contact 430a may be made of the same material as the gate layer, e.g., both metal tungsten.

In the cross-sectional view of semiconductor structure 400D illustrated in fig. 4D, conductive layer 430 on dielectric layer 420b is removed. The method of removing the conductive layer 430 on the dielectric layer 420b may be wet etching. The etchant for the wet etch may be phosphoric acid. After the conductive layer 430 on the dielectric layer 420b is removed, the thickness of the conductive contact 430a is approximately equal to the distance from the contact surface 420c to the dielectric layer 420b corresponding to the contact surface 420 c. To this end, each dummy gate layer 420a is contacted with a conductive contact 430 a.

At step 308, an insulating layer is overlaid on the stacked structure.

In this step, an insulating layer is covered on the stacked structure. The method of capping the stacked structure with an insulating layer may include depositing. Suitable processes can be selected from various known deposition processes, such as Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), High Density Plasma CVD (HDPCVD), Metal-Organic CVD (MOCVD) MOCVD, Molecular Beam Epitaxy (MBE), atomic layer deposition. The step of covering the insulating layer on the stacked structure may further include planarizing a surface of the insulating layer. The process of planarizing the surface of the insulating layer may be Chemical Mechanical Planarization (CMP). The material of the insulating layer may be, for example, silicon oxide.

In the cross-sectional view of the semiconductor structure 400D illustrated in fig. 4D, the stacked structure 420 is covered with an insulating layer 440. The surface of the insulating layer 440 is flat. The process of forming the surface of the flat insulating layer 440 may be chemical mechanical planarization. The material of the insulating layer 440 may be, for example, silicon oxide.

In step 310, a plurality of contact portions are formed on the insulating layer to penetrate the plurality of conductive contacts, respectively.

In this step, a plurality of contact portions penetrating the plurality of conductive contacts, respectively, are formed on the insulating layer. Contact holes may be etched in a conventional manner vertically through the stack. Contact holes extend vertically through the insulating material from the upper surface to the conductive contacts.

The contact hole is formed by, for example, etching or other known methods, and is not limited herein. After the contact hole is formed, the contact hole is filled with a conductive material to form a contact portion. After forming the contact portion, when the first material layer is a dummy gate layer, the method may further include removing the dummy gate layer to form a gap between the dielectric layers, and forming a gate layer in the gap. This step may be omitted when the first material layer is a gate layer.

In the cross-sectional view of the semiconductor structure 400F illustrated in fig. 4F, each step structure is covered with an insulating material 440, and contact holes (not shown) are formed through the insulating material 440 to the conductive contacts 430a, respectively. The core region of the memory array may then be provided with conductive paths by filling the contact 450 into the contact holes. The material of the contact 470 is, for example, a metal such as tungsten (W). The dummy gate layer 420a is then removed to form a gap between the dielectric layers 420b and a gate layer is formed in the gap.

Flow charts are used herein to illustrate operations performed by methods according to embodiments of the present application. It should be understood that the preceding operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes. For example, forming a virtual channel hole in the semiconductor structure to provide support for the semiconductor structure may also be included. It is understood that the dummy trench hole does not completely block the dummy gate layer or the gate layer. The dummy trench hole is only a hole structure penetrating through the cross-sectional area of the dummy gate layer or a part of the gate layer, and the control signal can still be transmitted to the core region through the gate layer. Also for example, forming a peripheral device below the virtual staircase may also be included.

The semiconductor structure formed by the above embodiments may be processed by the following conventional steps to obtain a three-dimensional memory device. A three-dimensional memory according to an embodiment of the invention is described herein with reference to the semiconductor structure formed in this embodiment.

Fig. 5A-5L are schematic cross-sectional views illustrating the formation of exposed contact surfaces on a plurality of first material layers according to an embodiment of the invention. For convenience of explanation, a basic stack structure of the stack structure 520 is represented by ON layers, each of which includes a second material layer and a first material layer located under the second material layer. Fig. 5A-5L show that the stacked structure 520 includes 6 ON layers (520 a, 520b, 520c, 520d, 520e, 520f in order from top to bottom), however this is not intended to represent the actual number of layers.

The step of removing at least part of the stacked structure to form an exposed contact surface on the plurality of first material layers may comprise removing at least part of the stacked structure to expose part of a surface of the plurality of second material layers and removing at least part of the second material layers at part of the surface to expose the contact surface on the first material layers. Fig. 5A-5I illustrate a process of removing at least a portion of the stacked structure to expose a portion of a surface of the plurality of second material layers. Fig. 5J-5L illustrate the process of removing at least a portion of the second material layer at a portion of the surface to expose a contact surface on the first material layer.

As shown in fig. 5A-5I, the method of removing at least a portion of the stacked structure to expose a portion of the surface of the plurality of second material layers may be a subtractive etching method. The direction of the trim etch is toward the center of the semiconductor structure (center of semiconductor is on the left side in fig. 5A, and direction is from right to left toward the center of the semiconductor structure). In fig. 5A, a photoresist 530 is covered on the stacked structure 520. The surface of the photoresist 530 is flat. The formation of the photoresist 530 that is planarized may be Spin-on (Spin-on). In fig. 5B, a portion of the photoresist 530 is opened, so that the ON layer 520a is exposed. In fig. 5C, the ON layer 520b is exposed and the ON layer 520a is partially etched. In fig. 5C, a portion of the photoresist 530 is removed, the ON layer 520C is exposed, and the ON layer 520a and the ON layer 520b are partially etched. The subtractive etch is then sequentially performed toward the center of the semiconductor structure as shown in FIGS. 5D-5I. In fig. 5I, a portion of the surface of the second material layer of each ON layer (i.e., 520a, 520b, 520c, 520d, 520e, 520f) is exposed.

As shown in fig. 5J-5L, the step of removing at least a portion of the second material layer at a portion of the surface to expose the contact surface on the first material layer may include covering the exposed second material layer with a photoresist and dry etching the photoresist. The dry etch may be a single layer dry etch. In fig. 5J, a photoresist 530 is coated on the stacked structure. The surface of the photoresist 530 is flat. The formation of the photoresist 530 that is planarized may be Spin-on (Spin-on). In fig. 5K, the photoresist 530 is etched using a photomask to form holes 540 reaching the plurality of second material layers. A portion of the surface of the second material layer of each ON layer is correspondingly formed with a hole 540. In fig. 5L, the exposed second material layer is etched through the holes 540. The etch may be a single layer etch.

Exposed contact surfaces 550 may be formed on the plurality of first material layers by exemplary steps as shown in fig. 5A-5L.

Fig. 6 illustrates a partial structure of a three-dimensional memory 600 according to an embodiment of the invention. As shown in fig. 6, the three-dimensional memory includes a semiconductor structure 600. The semiconductor structure 600 includes a dummy step structure 610 and a stack structure 620. The virtual stair-step structure 610 includes a plurality of steps. The multiple steps have different heights, i.e., the top surface of each step is at a different height. The higher the height of the step top surface, the larger the number of steps. The height of the dummy step structures 610 may increase in a direction away from the center of the semiconductor structure 400a or may decrease in a direction away from the center of the semiconductor structure 400 a. The central direction of the semiconductor structure refers to the direction in which the core region is located in the semiconductor structure. Preferably, as shown in fig. 6, the height of the dummy step structure 610 increases in a direction away from the center of the semiconductor structure 600. The stack structure 620 is conformally formed on the dummy step structure 610. The stack structure 620 includes gate layers 620a and dielectric layers 620b stacked alternately. A conductive contact 630 is formed on at least a portion of the gate layer 620 a. The conductive contacts 630 are correspondingly formed with contact portions 640. The number of stacked layers of the stacked structure 620 on the nth step is different from the number of stacked layers on the (N + 1) th step, where N is an integer greater than or equal to 1. The number of stacks on a step refers to the number of complete stacks. In fig. 6, the height of the dummy step structure 610 increases in a direction away from the center of the semiconductor structure 600, and the number of stacked layers of the stacked structure 620 on the nth step is greater than the number of stacked layers on the N +1 th step. It is understood that, correspondingly, if the height of the dummy step structure 610 decreases in a direction away from the center of the semiconductor structure 600, the number of stacked layers of the stacked structure 420 on the nth step is greater than the number of stacked layers on the N +1 th step.

In some embodiments of the present invention, the conductive contact 630 and the gate layer 620a may be made of the same material, for example, tungsten. In some embodiments of the present invention, the thickness of the conductive contact 630 is the thickness of the single dielectric layer 620 b. In some embodiments of the present invention, the thickness of the conductive contact 630 is greater than the thickness of the single dielectric layer 620 b. In some embodiments of the present invention, a peripheral device 650 is formed below the dummy ladder structure 610. In some embodiments of the present invention, the semiconductor structure 600 further includes a dummy channel hole 660 extending through the dummy ladder structure 610 and the stack structure 620 in the illustrated vertical direction to provide support for the semiconductor structure 600. It is understood that the dummy trench hole 660 does not completely block the gate layer 620 a. The dummy channel hole 660 is only a hole structure penetrating a partial cross-sectional area of the gate layer 620a, and the control signal can still be transmitted to the core region through the gate layer 620 a.

For further details of the present embodiment, reference is made to the above-mentioned manufacturing method, which is not further expanded herein.

The invention provides a method for manufacturing a three-dimensional memory, which comprises a virtual step structure and a stack structure, wherein a preformed conductive contact is arranged on the stack structure, so that the thickness of a gate layer in the stack structure can be increased, and the risk of etching through is greatly reduced because the gate layer is increased in thickness and is not easy to etch through.

Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.

Claims

1. A method for manufacturing a three-dimensional memory comprises the following steps:

providing a semiconductor structure comprising a dummy step structure and a stack structure, the dummy step structure comprising a plurality of steps, each step having a different height, the stack structure conformally formed on the dummy step structure, the stack structure comprising a plurality of first material layers and a plurality of second material layers alternately stacked;

removing at least part of the stacked structure to form exposed contact surfaces on the plurality of first material layers; after removing at least part of the stacked structures, the number of the stacked layers of the stacked structures on the Nth level of the step is different from the number of the stacked layers on the N +1 th level of the step, and N is an integer greater than or equal to 1;

forming a plurality of conductive contacts that respectively contact the plurality of first material layers through the contact surfaces;

covering an insulating layer on the stacked structure;

forming a plurality of contact portions penetrating to the plurality of conductive contacts, respectively, on the insulating layer.

2. The method of claim 1, wherein the height of the dummy step structure increases in a direction away from the center of the semiconductor structure, and the number of stacks of the stacked structure on the step of the Nth level is greater than the number of stacks on the step of the N +1 th level.

3. The method of claim 1, wherein the first material layer is a dummy gate layer or a gate layer and the second material layer is a dielectric layer.

4. The method of claim 3, wherein the conductive contact is made of the same material as the gate layer.

5. The method of claim 1, wherein the contact surface is an upper surface of the first material layer and the thickness of the conductive contact is a thickness of a single layer of the second material layer.

6. The method of claim 1, wherein the contact surface is an inner surface formed by removing at least a portion of the thickness of the first material layer, and wherein the thickness of the conductive contact is greater than the thickness of a single layer of the second material layer.

7. The method of claim 1, wherein the method of forming the dummy step structure is a subtractive etch process.

8. The method of claim 1, wherein removing at least a portion of the stacked structure to form an exposed contact surface on the plurality of first material layers comprises:

removing at least part of the stacked structure to expose part of the surface of the plurality of second material layers; and

removing at least a portion of the second material layer at the portion of the surface to expose a contact surface on the first material layer.

9. The method of claim 8, wherein the removing at least a portion of the stacked structure to expose a portion of the surface of the plurality of second material layers is a subtractive etching process, the subtractive etching process being directed toward a center of the semiconductor structure.

10. The method of claim 8, wherein removing at least a portion of the second material layer at the portion of the surface to expose the contact surface on the first material layer comprises: and covering photoresist on the exposed second material layer and carrying out dry etching on the photoresist.

11. The method of claim 10, wherein the dry etch is a single layer dry etch.

12. The method of claim 1, wherein forming a plurality of conductive contacts that respectively contact the plurality of first material layers through the contact surfaces comprises: covering the first material layer with a conductive contact and removing the conductive contact on the second material layer.

13. The method of claim 3, further comprising, after forming a contact portion on the insulating layer through to the conductive contact: when the first material layer is a dummy gate layer, removing the dummy gate layer to form a gap between the dielectric layers and a gate layer in the gap.

14. The method of claim 1, further comprising forming a peripheral device below the virtual stair-step structure.