CN109243399B - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN109243399B CN109243399B CN201811397470.0A CN201811397470A CN109243399B CN 109243399 B CN109243399 B CN 109243399B CN 201811397470 A CN201811397470 A CN 201811397470A CN 109243399 B CN109243399 B CN 109243399B
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- 239000000758 substrate Substances 0.000 title claims abstract description 127
- 239000003990 capacitor Substances 0.000 claims description 87
- 238000005452 bending Methods 0.000 claims description 6
- 230000000694 effects Effects 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 77
- 238000010586 diagram Methods 0.000 description 27
- 239000010409 thin film Substances 0.000 description 21
- 239000004973 liquid crystal related substance Substances 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Theoretical Computer Science (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses an array substrate, a display panel and a display device.A virtual stage shift register output end is electrically connected with a load device through a virtual gate line, so that the problem of high-temperature jitter of the display device can be avoided by adjusting the parameter size of the load device, and the display effect of the display device is ensured to be high. Meanwhile, the length of the virtual gate line can be reduced due to the arrangement of the load device, so that the length of the virtual gate line is smaller than that of the main gate line, the situation that the occupied area is too large due to the fact that the virtual gate line extends for a longer distance in a frame area is avoided, the width of the frame area of the display device can be reduced, and the narrow frame of the display device is achieved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.
Background
The liquid crystal display panel and the liquid crystal display device are one of the mainstream display technologies at present, the liquid crystal display panel comprises a plurality of gate lines and a plurality of data lines, the gate lines and the data lines are crossed to define a plurality of pixel units, and the pixel units comprise pixel electrodes and thin film transistors. The grid line is used for receiving a grid signal transmitted by the grid driving circuit so as to start the thin film transistor; meanwhile, the data line receives a source signal and transmits the source signal to the pixel electrodes through the thin film transistor so as to control the voltage on each pixel electrode, thereby controlling the rotation angle of the liquid crystal and realizing different light transmittance.
The gate driving circuit generally includes a plurality of stages of shift registers, and at least one end of the plurality of stages of shift registers is connected to a dummy stage shift register in cascade. However, the length of the conventional dummy gate line is generally similar to the length of the gate line connected to the shift register, so that when the dummy gate line is disposed in the frame region of the display device, the occupied area is large, and the width of the frame region of the conventional display device is large.
Disclosure of Invention
In view of the above, the present invention provides an array substrate, a display panel and a display device, which effectively solve the technical problems in the prior art, and can reduce the width of a frame region of the display device and realize a narrow frame of the display device.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
an array substrate, comprising:
a plurality of shift registers, each of which is electrically connected to a respective main gate line;
and at least one stage of virtual stage shift register cascaded with at least one end part of the multistage shift register, wherein the output end of the virtual stage shift register is electrically connected with a load device through a virtual gate line, the length of the virtual gate line is smaller than that of the main gate line, and the virtual gate line and the load device are both positioned in the frame area of the array substrate.
Optionally, the load device comprises at least one capacitor;
and when a plurality of capacitors are included, the plurality of capacitors are connected in parallel.
Optionally, the capacitance of the load device is greater than 1/4 of the capacitance of any one of the main gate lines and its overlapping line forming a capacitor.
Optionally, the first electrode plate of the capacitor is a partial region of the dummy gate line;
and the second polar plate of the capacitor and a signal line of the array substrate are formed by the same conductive layer, or the second polar plate of the capacitor is a partial area of the signal line.
Optionally, the dummy gate line further includes at least one bending portion.
Optionally, the first plate of the capacitor is at least a partial region of the bending portion.
Optionally, the width of the dummy gate line corresponding to the first electrode plate is not less than the width of the rest of the dummy gate line;
and/or the width of the signal line corresponding to the second pole plate is not less than the width of the rest part of the signal line.
Optionally, the second plate of the capacitor and the dummy gate line are formed by the same conductive layer.
Optionally, the second plate of the capacitor and the data line of the array substrate are formed by the same conductive layer;
or the second plate of the capacitor is a partial region of the data line.
Optionally, the second electrode plate of the capacitor and the common electrode line of the array substrate are formed by the same conductive layer;
or the second electrode plate of the capacitor is a partial area of the common electrode line.
Optionally, the multi-stage shift register and the at least one stage of virtual stage shift register are both located on the same side of the frame region.
Optionally, the multi-stage shift register includes a first shift register group and a second shift register group respectively located at two opposite sides of the frame region;
at least one end of at least one shift register group in the first shift register group and the second shift register group is cascaded with at least one stage of virtual shift register, and the virtual shift register and the cascaded shift register group are positioned on the same side of the frame area.
Optionally, the array substrate includes:
and the dummy gate lines and the load devices electrically connected with the dummy gate lines are positioned on the same side of the driving unit.
Optionally, the orthographic projection of the array substrate on a projection plane parallel to the plane on which the array substrate is located is a preset shape.
Correspondingly, the invention also provides a display panel which comprises the array substrate.
Correspondingly, the invention further provides a display device which comprises the display panel.
Compared with the prior art, the technical scheme provided by the invention at least has the following advantages:
the invention provides an array substrate, a display panel and a display device, wherein the array substrate comprises: a plurality of shift registers, each of which is electrically connected to a respective main gate line; and at least one stage of virtual stage shift register cascaded with at least one end part of the multistage shift register, wherein the output end of the virtual stage shift register is electrically connected with a load device through a virtual gate line, the length of the virtual gate line is smaller than that of the main gate line, and the virtual gate line and the load device are both positioned in the frame area of the array substrate.
From the above, the output end of the virtual stage shift register is electrically connected to a load device through the virtual gate line, so that the problem of high temperature jitter of the display device can be avoided by adjusting the parameter of the load device, and the display effect of the display device is ensured to be high. Meanwhile, the length of the virtual gate line can be reduced due to the arrangement of the load device, so that the length of the virtual gate line is smaller than that of the main gate line, the situation that the occupied area is too large due to the fact that the virtual gate line extends for a longer distance in a frame area is avoided, the width of the frame area of the display device can be reduced, and the narrow frame of the display device is achieved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;
fig. 10 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure;
fig. 11 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;
fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background art, the gate driving circuit generally includes a plurality of stages of shift registers, and a dummy stage shift register is cascaded at least one end of the plurality of stages of shift registers, so as to avoid the problem of high temperature jitter of the display device, the display device generally has a dummy gate line as a load connected to an output terminal of the dummy stage shift register. However, the length of the conventional dummy gate line is generally similar to the length of the gate line connected to the shift register, so that when the dummy gate line is disposed in the frame region of the display device, the occupied area is large, and the width of the frame region of the conventional display device is large.
Based on this, the embodiment of the application provides an array substrate, a display panel and a display device, effectively solves the technical problems existing in the prior art, can reduce the width of a frame region of the display device, and realizes the narrow frame of the display device. To achieve the above object, the technical solutions provided by the embodiments of the present application are described in detail below, specifically with reference to fig. 1 to 12.
Referring to fig. 1, a schematic structural diagram of an array substrate according to an embodiment of the present disclosure is shown, where the array substrate includes a display area AA and a frame area NA surrounding the display area AA, where the frame area NA of the array substrate includes:
a plurality of stages of shift registers 110, each of the shift registers 110 being electrically connected to a respective corresponding main gate line 120;
and at least one dummy stage shift register 210 cascaded with at least one end of the multi-stage shift register 110, wherein an output end of the dummy stage shift register 210 is electrically connected to a load device 230 through a dummy gate line 220, a length of the dummy gate line 220 is smaller than a length of the main gate line 120, and the dummy gate line 220 and the load device 230 are both located in a frame area NA of the array substrate.
It can be understood that, in the array substrate provided in the embodiment of the present application, the output end of the virtual stage shift register is electrically connected to a load device through the virtual gate line, so that by adjusting the parameter size of the load device, the problem of high temperature jitter of the display device can be avoided, and the display effect of the display device is ensured to be high. Meanwhile, the length of the virtual gate line can be reduced due to the arrangement of the load device, so that the length of the virtual gate line is smaller than that of the main gate line, the situation that the occupied area is too large due to the fact that the virtual gate line extends for a longer distance in a frame area is avoided, the width of the frame area of the display device can be reduced, and the narrow frame of the display device is achieved.
In an embodiment of the present application, a frame region of the array substrate provided by the present application includes a driving unit region, where the driving unit region is mainly configured to provide signals for data lines of the array substrate, and the driving unit region is mainly configured with driving devices such as a driving IC and a splitter; in the dummy gate line on the same side of the frame area as the driving unit area, the extending end of the dummy gate line can be cut off before the driving unit area, so as to reduce the length of the dummy gate line. Referring to fig. 2, a schematic structural diagram of an array substrate provided in an embodiment of the present application is shown, where the array substrate provided in the embodiment of the present application includes:
the dummy gate lines 220 are located on the same side of the frame area NA as the driving unit area 100, and the dummy gate lines 220 and the load devices 230 electrically connected thereto are located on the same side of the driving unit area 100.
It should be noted that, in the embodiment of the present application, no particular limitation is imposed on the shape of the array substrate, that is, an orthogonal projection of the array substrate on a projection plane parallel to a plane where the array substrate is located is a preset shape. Wherein, the preset shape may be a rectangular shape, as shown in fig. 1; furthermore, the preset shape may also be non-rectangular, such as: fig. 3 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure, wherein the array substrate is a circular array substrate, a display area AA of the array substrate is also circular, and a frame area NA of the array substrate is circular.
In an embodiment of the present application, the load device provided by the present application may include a capacitor, and when the load device includes a plurality of capacitors, in order to meet a requirement of the virtual stage shift register for a load parameter, a relationship between the plurality of capacitors is a parallel relationship. That is, the load device comprises at least one capacitance;
and when a plurality of capacitors are included, the plurality of capacitors are connected in parallel.
In order to ensure that the parameters of the load device meet the requirements of the virtual shift register on the load parameters, and to avoid the problem of high-temperature jitter of the display device, when the load device is a capacitor, the capacitance value of the load device provided by the embodiment of the present application is greater than 1/4 of the capacitance value of a capacitor formed by any one of the main gate lines and the overlapping line thereof.
It is understood that when the load device includes a capacitor, the capacitance value of the capacitor is the capacitance value of the capacitor; and when the load device comprises a plurality of capacitors connected in parallel, the capacitance value of the load device is the total capacitance value of the plurality of capacitors connected in parallel. And, the capacitor formed by the main gate line and the overlapping line thereof provided by the embodiment of the application is a capacitor formed between the main gate line and the pixel electrode when the display device is a liquid crystal display device, wherein the capacitance value of the load device is set to be greater than 1/4 of the capacitance value of the capacitor formed between any one main gate line and the pixel electrode, so as to meet the requirement of the virtual level shift register on the load parameter, avoid the problem of high temperature jitter of the display device, and ensure that the display effect of the display device is high.
Further, in order to reduce the manufacturing process of the display panel, when the load device provided by the embodiment of the application is a capacitor, the polar plate of the capacitor can be reused by the original circuit on the array substrate. Referring to fig. 4, a schematic structural diagram of another array substrate provided in the present embodiment is shown, where a dashed line frame shown in fig. 4 is an equivalent diagram of a capacitor C, where a first plate of the capacitor C is a partial region of the dummy gate line 220;
and the second plate of the capacitor C and a signal line 240 of the array substrate are formed by the same conductive layer, or the second plate of the capacitor C is a partial region of the signal line 240.
It can be understood that, when the second plate of the capacitor and the signal line are formed by the same conductive layer, the second plate is a line independent from the signal line, wherein the second plate may be connected to a reference signal, and the reference signal may be provided by the driver IC, or an independent signal terminal is provided, which is not limited in this application. Or when the second plate of the capacitor is a partial area of the signal line, the port originally connected with the signal line provides a corresponding signal.
And when the load device comprises a plurality of capacitors, the first polar plates of the capacitors are arranged in partial areas of the virtual gate lines, so that the first polar plates of the capacitors are connected, and the capacitors are ensured to be in a parallel connection state. The first electrode plate of the capacitor of the load device is a partial area of the virtual gate line, and the second electrode plate of the capacitor is formed by the same conductive layer as a signal line of the array substrate, or the second electrode plate of the capacitor is directly formed by the partial area of the signal line, so that two conductive layers for forming the first electrode plate and the second electrode plate of the capacitor are not required to be manufactured separately when the array substrate is manufactured, and the situation that the manufacturing process for manufacturing the array substrate is excessive is avoided.
In an embodiment of the present application, on the basis that a partial region of the virtual gate line is reused as the first electrode plate of the capacitor, in order to ensure that the parameters of the load device meet the requirements of the virtual shift register on the load parameters, a plurality of parallel capacitors may be designed, at this time, in order to avoid the virtual gate line from extending too long to affect the width of the frame region of the display device, the virtual gate line may be further bent at least one to obtain at least one bent portion, and then the capacitors connected at the front end among the plurality of capacitors adopt at least a partial region of the original extension portion of the virtual gate line, and the first electrode plate of the capacitors connected at the tail end among the plurality of capacitors reuses a partial region of the bent portion to form the plurality. Referring to fig. 5, a schematic structural diagram of another array substrate according to an embodiment of the present disclosure is shown, wherein a dashed line frame in fig. 5 is an equivalent diagram of a plurality of capacitors C connected in parallel, the dummy gate line 220 further includes at least one bending portion 222, and the dummy gate line 220 includes an extending portion 221 that is not bent. The first plate of the capacitor C provided in the embodiment of the present application is at least a partial region of the bending portion 222;
alternatively, the first plate of the capacitor C is at least a partial region of the extension portion 221.
It should be noted that, when the load device provided by the embodiment of the present application includes a capacitor, a partial region of the bent portion may also be used as the first plate of the capacitor; and when the load device comprises a plurality of capacitors connected in parallel, the first electrode plates of all the capacitors can adopt partial areas of the bent parts, or the first electrode plates of all the capacitors adopt partial areas of the extending parts, so that the application is not limited, and the load device needs to be specifically designed according to practical application.
In an embodiment of the present application, on the basis that a partial region of the dummy gate line is multiplexed as the first electrode plate of the capacitor, in order to ensure that the parameters of the load device meet the requirements of the dummy shift register on the load parameters, the width of the first electrode plate and/or the second electrode plate of the capacitor may be increased, so as to increase the overlapping area between the first electrode plate and the second electrode plate. Referring to fig. 6, a schematic structural diagram of another array substrate provided in an embodiment of the present invention is shown in a dashed line frame in fig. 6, which is an enlarged diagram after separating a dummy gate line 220 and a signal line 240, where the width a of the dummy gate line 220 at the first plate is not less than the width b of the rest of the dummy gate line 220, that is, at the overlapping position of the first plate and the second plate, the width of the first plate is increased along the extending direction of the signal line at the second plate to increase the overlapping area between the first plate and the corresponding second plate;
and/or the width c of the signal line 240 corresponding to the second plate is not less than the width d of the rest of the signal line 240, and similarly, at the overlapping position of the first plate and the second plate, the width of the second plate is increased along the extending direction of the virtual gate line where the first plate is located, so as to increase the overlapping area between the first plate and the corresponding second plate.
The second plate of the capacitor provided by the application can be formed by the same conductive layer as the signal line, or the second plate can be a partial area of the signal line. In an embodiment of the present application, the signal line provided in the embodiment of the present application may be a dummy gate line, that is, the second plate of the capacitor provided in the embodiment of the present application and the dummy gate line are formed by the same conductive layer.
Or, the signal line provided in the embodiment of the present application is a data line of the array substrate, that is, the second plate of the capacitor provided in the embodiment of the present application and the data line of the array substrate are formed by the same conductive layer; or the second plate of the capacitor is a partial region of the data line.
Or, the signal line provided in this embodiment of the present application may be a common electrode line of the array substrate, that is, the second electrode plate of the capacitor provided in this embodiment of the present application and the common electrode line of the array substrate are formed by the same conductive layer; or the second electrode plate of the capacitor is a partial area of the common electrode line.
It should be noted that, when the virtual stage shift register works, the signal transmitted by the data line at this time does not respond to the signal of the display image, so that the second plate of any capacitor provided in the embodiment of the present application can adopt partial region of the data line, and does not affect the display effect of the display device. And the width of the public electrode wire in the frame area is larger, and the area of the public electrode in the display area connected with the public electrode wire is larger, so that when the second plate of any capacitor can adopt a partial area of the public electrode wire, the capacitance value of the formed capacitor is larger, and the influence of the formed capacitor on the signal transmitted by the public electrode wire to the public electrode is limited, and the display effect of the display device can not be influenced.
In an embodiment of the present application, the array substrate provided by the present application may be an array substrate of a liquid crystal display device, and as shown in fig. 7, is a schematic structural diagram of an array substrate provided by an embodiment of the present application, where the array substrate is an array substrate of a liquid crystal display device, and includes:
a substrate 1001;
a thin film transistor array layer on the substrate 1001, wherein the thin film transistor array layer may include: a gate layer on the substrate 1001, the gate layer may be used to form a main gate line (not shown), a dummy gate line (not shown), and a gate 20021 of a thin film transistor; a gate insulating layer 20022 on a side of the gate layer away from the substrate 1001; a semiconductor layer on a side of the gate insulating layer 20022 away from the substrate 1001, the semiconductor layer may be used to form an active region 20023 of the thin film transistor; a source/drain layer located on a side of the semiconductor layer away from the substrate 1001, where the source/drain layer may be used to form a data line (not shown) and a source 20024 and a drain 20025 of the thin film transistor;
a planarization layer 1003 on the side of the thin film transistor array layer away from the substrate 1001;
a common electrode layer 1004 on a side of the planarization layer 1003 away from the substrate 1001, the common electrode layer including a common electrode;
an insulating layer 1005 on a side of the common electrode layer 1004 facing away from the substrate 1001;
and a pixel electrode 1006 located on a side of the insulating layer 1005 away from the substrate 1001, the array substrate further includes a common electrode line layer located in the frame region and connected to the common electrode, the common electrode line includes a common electrode line, wherein the common electrode line may be on the same layer or on the same layer as the common electrode, and when the common electrode line and the common electrode are on the same layer, the common electrode line and the common electrode are electrically connected through a via hole. The first electrode plate of the capacitor provided by the embodiment of the application is manufactured by a gate electrode layer, and the second electrode plate of any capacitor can be manufactured by one of the gate electrode layer, a source drain layer and a common electrode line layer.
In addition, the array substrate provided in the embodiment of the present application may also be an array substrate of an organic light emitting display device, and refer to fig. 8, which is a schematic structural diagram of another array substrate provided in the embodiment of the present application, where the array substrate includes:
a substrate 2001;
a thin film transistor array layer on the substrate 2001, wherein the thin film transistor array layer may include: a gate layer on the substrate 2001, the gate layer being used to form a main gate line (not shown), a dummy gate line (not shown), and a gate electrode 30021 of a thin film transistor; a gate insulating layer 30022 on a side of the gate layer facing away from the substrate 2001; a semiconductor layer on a side of the gate insulating layer 30022 facing away from the substrate 2001, the semiconductor layer may be used to form an active region 30023 of a thin film transistor; a source-drain layer on the side of the semiconductor layer opposite to the substrate 2001, wherein the source-drain layer can be used for forming a data line (not shown) and a source electrode 30024 and a drain electrode 30025 of the thin film transistor;
a planarization layer 2003 on the side of the thin film transistor array layer facing away from the substrate 2001;
an anode layer on a side of the planarization layer 2003 facing away from the substrate 2001, the anode layer may include a plurality of anodes 2004, and the anodes 2004 may be connected to the tft source 20024 or drain 20025 through vias (not shown) in the planarization layer 2003;
an organic light-emitting layer 2005 on the side of the anode 2004 facing away from the substrate 2001;
and a cathode layer 2006 on a side of the organic light emitting layer 2005 away from the substrate 2001, wherein a first electrode plate of the capacitor provided by the embodiment of the present application is made of a gate layer, and a second electrode plate of any capacitor can be made of a gate layer or a source/drain layer.
It should be noted that, when the array substrate is an array substrate of a liquid crystal display device, the interlayer relationship between the common electrode and the pixel electrode may be interchanged, or the common electrode and the pixel electrode may be formed by the same conductive layer, which is not limited in this application. In the embodiments shown in fig. 7 and 8, the thin film transistors are bottom gate thin film transistors, which is not specifically limited in this application, and the thin film transistors may also be top gate thin film transistors, that is, the thin film transistor array layer includes:
a semiconductor layer on the substrate, the semiconductor layer being used to form an active region of the thin film transistor;
the gate insulating layer is positioned on one side, away from the substrate, of the semiconductor layer;
the grid electrode layer is positioned on the side, away from the substrate, of the grid insulating layer and can be used for forming a main grid line, a virtual grid line and a grid electrode of the thin film transistor;
the interlayer insulating layer is positioned on one side of the gate electrode layer, which is far away from the substrate;
and the source and drain layers are positioned on one side of the interlayer insulating layer, which is far away from the substrate, and can be used for forming a data line and a source electrode and a drain electrode of the thin film transistor.
In an embodiment of the present application, the multi-stage shift register and the at least one stage of virtual stage shift register are located on the same side of the frame region. Referring to fig. 9, a schematic structural diagram of another array substrate according to an embodiment of the present disclosure is shown, wherein the multi-stage shift register 110 and the dummy stage shift register 210 included in the array substrate are both located on the same side of the frame area NA.
In an embodiment of the present application, the shift registers and the virtual stage shift registers provided in the embodiment of the present application may also be grouped and disposed on two sides of the frame region. Referring to fig. 10, a schematic structural diagram of another array substrate according to an embodiment of the present disclosure is shown, wherein the multi-stage shift register 110 includes a first shift register group 1101 and a second shift register group 1102 respectively located at two opposite sides of the frame area NA;
at least one end of at least one of the first shift register group 1101 and the second shift register group 1102 is cascaded with at least one stage of virtual shift register 210, and the virtual shift register 210 and the cascaded shift register group thereof are located on the same side of the border area NA.
Correspondingly, the embodiment of the application also provides a display panel, and the display panel comprises the array substrate provided by any one of the embodiments.
Referring to fig. 11, a schematic structural diagram of a display panel according to an embodiment of the present disclosure is shown, where the display panel is a liquid crystal display panel, and includes:
the color filter substrate 3001 and the array substrate 3003 provided by any one of the embodiments above are disposed opposite to each other;
and a liquid crystal layer 3002 located between the color filter substrate 3001 and the array substrate 3002.
It should be noted that the display panel provided in the embodiment of the present application may also be an organic light emitting display panel, and the present application is not particularly limited thereto.
Correspondingly, an embodiment of the present application further provides a display device, where the display device includes the display panel provided in any one of the above embodiments.
Referring to fig. 12, a schematic structural diagram of a display device according to an embodiment of the present disclosure is shown, where the display device is a liquid crystal display device, and includes:
the display panel 4001 provided by any one of the above embodiments;
and a backlight module 4002 for providing a light source for the display panel 4001.
In an embodiment of the present application, the display device provided in the present application may also be an organic light emitting display device, and the like, and the present application is not limited specifically. Moreover, the display device provided by the application can be a mobile phone, a smart watch, a tablet computer and the like, and the application is not particularly limited.
The embodiment of the application provides an array substrate, display panel and display device, the array substrate includes: a plurality of shift registers, each of which is electrically connected to a respective main gate line; and at least one stage of virtual stage shift register cascaded with at least one end part of the multistage shift register, wherein the output end of the virtual stage shift register is electrically connected with a load device through a virtual gate line, the length of the virtual gate line is smaller than that of the main gate line, and the virtual gate line and the load device are both positioned in the frame area of the array substrate.
From the above, the output end of the virtual stage shift register is electrically connected to a load device through the virtual gate line, so that the problem of high temperature jitter of the display device can be avoided by adjusting the parameter of the load device, and the display effect of the display device is ensured to be high. Meanwhile, the length of the virtual gate line can be reduced due to the arrangement of the load device, so that the length of the virtual gate line is smaller than that of the main gate line, the situation that the occupied area is too large due to the fact that the virtual gate line extends for a longer distance in a frame area is avoided, the width of the frame area of the display device can be reduced, and the narrow frame of the display device is achieved.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (16)
1. An array substrate, comprising:
a plurality of shift registers, each of which is electrically connected to a respective main gate line;
and at least one stage of virtual stage shift register cascaded with at least one end part of the multistage shift register, wherein the output end of the virtual stage shift register is electrically connected with a load device through a virtual gate line, the length of the virtual gate line is smaller than that of the main gate line, and the virtual gate line and the load device are both positioned in the frame area of the array substrate.
2. The array substrate of claim 1, wherein the load device comprises at least one capacitor;
and when a plurality of capacitors are included, the plurality of capacitors are connected in parallel.
3. The array substrate of claim 2, wherein the capacitance of the load device is greater than 1/4 of the capacitance of any one of the main gate lines forming a capacitor with its overlapping line.
4. The array substrate of claim 2, wherein the first plate of the capacitor is a partial region of the dummy gate line;
and the second polar plate of the capacitor and a signal line of the array substrate are formed by the same conductive layer, or the second polar plate of the capacitor is a partial area of the signal line.
5. The array substrate of claim 4, wherein the dummy gate line further comprises at least one bending portion.
6. The array substrate of claim 5, wherein the first plate of the capacitor is at least a partial region of the bending portion.
7. The array substrate of claim 4, wherein the width of the dummy gate line corresponding to the first electrode plate is not less than the width of the rest of the dummy gate line;
and/or the width of the signal line corresponding to the second pole plate is not less than the width of the rest part of the signal line.
8. The array substrate of claim 4, wherein the second plate of the capacitor and the dummy gate line are formed of a same conductive layer.
9. The array substrate of claim 4, wherein the second plate of the capacitor and the data line of the array substrate are formed by the same conductive layer;
or the second plate of the capacitor is a partial region of the data line.
10. The array substrate of claim 4, wherein the second plate of the capacitor and the common electrode line of the array substrate are formed by the same conductive layer;
or the second electrode plate of the capacitor is a partial area of the common electrode line.
11. The array substrate of claim 1, wherein the multi-stage shift register and the at least one stage of dummy shift register are located on a same side of the frame region.
12. The array substrate of claim 1, wherein the multi-stage shift register comprises a first shift register group and a second shift register group respectively located at two opposite sides of the frame region;
at least one end of at least one shift register group in the first shift register group and the second shift register group is cascaded with at least one stage of virtual shift register, and the virtual shift register and the cascaded shift register group are positioned on the same side of the frame area.
13. The array substrate of claim 1, wherein the array substrate comprises:
and the dummy gate lines and the load devices electrically connected with the dummy gate lines are positioned on the same side of the driving unit.
14. The array substrate of claim 1, wherein an orthographic projection of the array substrate on a projection plane parallel to a plane on which the array substrate is located is a preset shape.
15. A display panel comprising the array substrate according to any one of claims 1 to 14.
16. A display device characterized by comprising the display panel according to claim 14.
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| CN201811397470.0A CN109243399B (en) | 2018-11-22 | 2018-11-22 | Array substrate, display panel and display device |
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| CN115250633A (en) * | 2021-02-26 | 2022-10-28 | 京东方科技集团股份有限公司 | Display panel, display device and driving method |
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| KR20150079645A (en) * | 2012-10-30 | 2015-07-08 | 샤프 가부시키가이샤 | Active matrix substrate, display panel and display device provided with same |
| CN103941507B (en) * | 2014-04-02 | 2017-01-11 | 上海天马微电子有限公司 | Array substrate, display panel and display device |
| CN104914641B (en) * | 2015-06-30 | 2018-05-01 | 上海天马微电子有限公司 | Array substrate, display panel and liquid crystal display device |
| CN105448259B (en) * | 2015-12-25 | 2018-03-30 | 上海中航光电子有限公司 | Gate drivers and display panel |
| CN105427789B (en) * | 2015-12-31 | 2019-05-03 | 上海天马微电子有限公司 | Drive circuit, array substrate and display device |
| CN105719593A (en) * | 2016-04-29 | 2016-06-29 | 上海中航光电子有限公司 | Grid electrode driving circuit, display panel and electronic equipment |
| US10056468B2 (en) * | 2016-09-07 | 2018-08-21 | Globalfoundries Inc. | Source/drain parasitic capacitance reduction in FinFET-based semiconductor structure having tucked fins |
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