CN109167573B - Demodulation circuit - Google Patents
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Abstract
The demodulation circuit is convenient to integrate, and a peripheral amplifier, a resistor and a capacitor are not needed, so that the size and the cost of the demodulation circuit are reduced, and the demodulation complexity is reduced. The demodulation circuit includes: the device comprises a rectifying module, a band-pass amplifying module, a differential amplifying module, a decision device and a decoding module which are connected in sequence; the rectification module is used for rectifying the input ASK amplitude modulation signal to obtain a rectified ASK amplitude modulation signal; the band-pass amplification module is used for filtering and amplifying the rectified ASK amplitude modulation signal to obtain an ASK envelope signal; the differential amplification module is used for detecting and amplifying the rising edge and the falling edge of the ASK envelope signal to obtain a demodulation digital signal which can be identified by the decision device; the decision device is used for filtering burrs of the demodulation digital signal to obtain a deburring demodulation digital signal; and the decoding module is used for decoding the deburring demodulation digital signal to obtain a data information packet.
Description
Technical Field
The application belongs to the technical field of electronics, and in particular relates to a demodulation circuit.
Background
The market demand for wireless charging technology is increasing, wherein the market occupation rate of the QI standard of the wireless charging consortium (WPC) is the most widespread. The market has introduced various corresponding signal demodulation schemes according to the QI standard.
Because the frequency of ASK amplitude modulation signals under QI standard is as low as about 2kHz, most current demodulation schemes still need a plurality of peripheral amplifiers, resistors and capacitors in order to realize functions such as low-pass filtering and blocking, which is not beneficial to the integration of the demodulation circuit. These demodulation schemes have therefore failed to meet the ever-increasing demands for low cost, do not facilitate reducing the size of the application circuitry, and do not facilitate reducing the complexity of debugging.
Disclosure of Invention
In order to solve the above problems, the present application provides a demodulation circuit that can be easily integrated without a peripheral amplifier, a resistor, and a capacitor, thereby reducing the size and cost of the demodulation circuit and the demodulation complexity.
The application provides a demodulation circuit, including: the device comprises a rectifying module, a band-pass amplifying module, a differential amplifying module, a decision device and a decoding module which are connected in sequence;
the rectification module is used for rectifying the input ASK amplitude modulation signal to obtain a rectified ASK amplitude modulation signal;
the band-pass amplification module is used for filtering and amplifying the rectified ASK amplitude modulation signal to obtain an ASK envelope signal;
the differential amplification module is used for detecting and amplifying the rising edge and the falling edge of the ASK envelope signal to obtain a demodulated digital signal which can be identified by the decision device;
the decision device is used for filtering burrs of the demodulation digital signal to obtain a deburring demodulation digital signal;
and the decoding module is used for decoding the deburring demodulation digital signal to obtain a data information packet.
Optionally, the band pass amplification module includes: the input direct current bias circuit, the band-pass filter unit and the buffer are connected in sequence.
Optionally, the circuit further comprises: and the low-pass filter is arranged between the connection end of the band-pass filter unit and the buffer and the grounding end.
Optionally, the band pass filter unit includes: the circuit comprises a first amplifier, a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor and a fourth resistor; the first resistor and the second resistor are sequentially connected in series; the fourth resistor and the second capacitor are sequentially connected in series; the output end of the input direct current bias circuit is connected with one end, far away from the second capacitor, of the fourth resistor, and one end, far away from the fourth resistor, of the second capacitor is connected with the first resistor, the first capacitor and the negative input end of the first amplifier; the second resistor, the first capacitor and the output end of the first amplifier are connected, and the connecting end is used as the output end of the band-pass filter unit; the positive input end of the first amplifier is connected with a first power supply; the third resistor is connected between the first power source and the connection end of the first resistor and the second resistor.
Optionally, the differential amplifying module comprises: the device comprises a clock generator, a differential hysteresis control unit, and a differential unit and a cascade amplification module which are sequentially connected in series.
Optionally, the clock generator is configured to process the input clock signal into a self-zeroing phase and an amplifying phase that do not overlap.
Optionally, the differentiation unit comprises: the device comprises a first self-zeroing switch, a second self-zeroing switch, a first amplifying switch, a sampling capacitor and a second amplifier; the first self-zeroing switch is connected with the first amplifying switch in parallel, the output end of the band-pass amplifying module is connected with the first self-zeroing switch and the first parallel end of the first amplifying switch, and the second parallel ends of the first self-zeroing switch and the first amplifying switch are sequentially connected with the sampling capacitor and the second amplifier in series; the second self-zeroing switch is connected between the input end and the output end of the second amplifier; the first self-zeroing switch and the second self-zeroing switch are closed when the input clock signal is in a self-zeroing phase and are opened when the input clock signal is in an amplifying phase; the first amplifying switch is turned off when the input clock signal is in the self-zeroing phase and is turned on when the input clock signal is in the amplifying phase.
Optionally, the cascade amplification module includes at least one amplification unit connected in series in sequence; the amplification unit includes: the self-zeroing circuit comprises a self-zeroing capacitor, an amplifier and a self-zeroing switch, wherein the self-zeroing capacitor is connected with the amplifier in series, and the self-zeroing switch is connected between the input end and the output end of the amplifier; the self-zero switch is closed when the input clock signal is in a self-zero phase, and is opened when the input clock signal is in an amplification phase.
Optionally, the differential hysteresis control unit comprises: the automatic zero-setting and inverting circuit comprises a register, a cascade subunit, an automatic zero-setting and inverting switch, an amplifying and inverting switch and a feedback capacitor which are sequentially connected in series; the input signal of the control end of the register is an input clock signal, the input clock signal is a self-zeroing clock, the register is a clock rising edge register, and the input end of the register is connected with the output end of the differential amplification module; the cascade subunit comprises at least one amplifier or inverter connected in series; the output end of the cascade subunit is connected with the auto-zeroing inverting switch and the amplifying inverting switch in series, and the other end of the amplifying inverting switch is connected with the output end of any amplifier in the differential unit and the cascade amplifying module which are connected in series; the feedback capacitor is connected between the input end of the next-stage amplifier of any amplifier and the connecting ends of the self-zero inverting switch and the amplifying inverting switch; the amplifying and inverting switch is closed when the input clock signal is in the self-zero-adjusting phase and is opened when the input clock signal is in the amplifying phase; the auto-zero negation switch is switched off when the input clock signal is in the auto-zero phase and is switched on when the input clock signal is in the amplification phase.
Optionally, the differential hysteresis control unit comprises: the automatic zero-setting and inverting circuit comprises a register, a cascade subunit, an automatic zero-setting and inverting switch, an amplifying and inverting switch and a feedback capacitor which are sequentially connected in series; the input signal of the control end of the register is an input clock signal, the input clock signal is a self-zeroing clock, the register is a clock rising edge register, and the input end of the register is connected with the output end of the differential amplification module; the cascade subunit comprises at least one amplifier or inverter connected in series; the output end of the cascade subunit is connected with the self-zeroing inverting switch and the amplifying inverting switch in series, and the other end of the amplifying inverting switch is connected with the output end of the band-pass amplifying module; the feedback capacitor is connected between the input end of the second amplifier and the connecting ends of the self-zero-setting inverting switch and the amplifying inverting switch; the amplifying and inverting switch is closed when the input clock signal is in the self-zero-adjusting phase and is opened when the input clock signal is in the amplifying phase; the auto-zero negation switch is switched off when the input clock signal is in the auto-zero phase and is switched on when the input clock signal is in the amplification phase.
Optionally, the decider comprises a multi-way voter.
The application has the following beneficial effects:
the demodulation circuit detects and amplifies the rising edge and the falling edge of the ASK envelope signal through a differential amplification unit to obtain a demodulation digital signal which can be identified by the judger; the circuit is simplified, and the circuit cost is reduced; in addition, the demodulation circuit does not need a peripheral large capacitor or a large resistor, can be fully integrated, and greatly reduces the size of the demodulation circuit.
Drawings
Fig. 1 is a schematic structural diagram of a demodulation circuit disclosed in the present application;
FIG. 2 is a schematic diagram of the configuration of the bandpass amplifier module circuit of FIG. 1 according to the present disclosure;
FIG. 3 is a schematic diagram of the differential amplifier module circuit of FIG. 1 according to the present disclosure;
fig. 4 is a schematic diagram of an amplitude-frequency response simulation result of the bandpass amplification module disclosed in the present application;
FIG. 5 is a schematic illustration of non-overlapping clocks generated by clock generator 131 of FIG. 4 according to the present disclosure;
FIG. 6 is a schematic diagram of a specific structure of the differential amplifier module circuit of FIG. 4 according to the present disclosure;
FIG. 7 is a schematic diagram of another specific structure of the differential amplifier module circuit of FIG. 4 according to the present disclosure;
FIG. 8 is a diagram illustrating transient response simulation results for each node in the circuit of the present application.
Detailed Description
Fig. 1 is a schematic diagram of a demodulation circuit disclosed in the present application. The demodulation circuit 100 includes: the rectifier module 110, the band-pass amplifier module 120, the differential amplifier module 130, the determiner 140 and the decoder module 150 are connected in sequence;
the rectifying module 110 is configured to rectify an input ASK amplitude modulation signal to obtain a rectified ASK amplitude modulation signal;
the band-pass amplification module 120 is configured to filter and amplify the rectified ASK amplitude modulation signal to obtain an ASK envelope signal;
a differential amplification module 130, configured to detect and amplify a rising edge and a falling edge of the ASK envelope signal, so as to obtain a demodulated digital signal that can be identified by the decision device 140;
the decision device 140 is configured to filter out burrs of the demodulated digital signal to obtain a deburred demodulated digital signal;
and the decoding module 150 is used for decoding the deburring demodulated digital signal to obtain a data information packet.
As shown in fig. 2, the band pass amplification module 120 includes: an input dc bias circuit 121, a band pass filter unit 122, and a buffer 123 connected in this order.
The input dc bias circuit 121 includes: resistance RB1、RB2(ii) a The buffer 123 may be a buffer, and the output Vo2 of the buffer 123 is the output of the band pass amplifying module 120.
The band pass amplifying module 120 may further include: and a low pass filter 124, the low pass filter 124 being disposed between a connection terminal of the band pass filter unit 122 and the buffer 123 and a ground terminal. The low pass filter 124 is used to further filter out high frequency signals.
The band pass filter unit 122 includes: the circuit comprises a first amplifier, a first capacitor C2, a second capacitor C1, a first resistor R3, a second resistor R4, a third resistor R5 and a fourth resistor R1;
the first resistor R3 and the second resistor R4 are sequentially connected in series; the fourth resistor R1 and the second capacitor C1 are sequentially connected in series; the output end of the input dc bias circuit 121 is connected to one end of the fourth resistor R1 away from the second capacitor C1, and one end of the second capacitor C1 away from the fourth resistor R1 is connected to the first resistor R3, the first capacitor C2 and the negative input end-of the first amplifier; the second resistor R4, the first capacitor C2 and the output Vo1 of the first amplifier are connected, and the connection terminal is the output terminal of the band pass filter unit 122; the positive input end of the first amplifier is connected with a first power supply VCM; the third resistor R5 is connected between the first power VCM and the connection terminals of the first resistor R3 and the second resistor R4. The overall transfer function of the bandpass amplifier of fig. 2 can be expressed as follows:
pole therein
Indicating a capacitance multiplication function, i.e. by increasing
The value of (2) reduces the pole, and plays a role in reducing the area of the capacitor and further reducing the cost. FIG. 3 shows the gain of the band pass amplifier module 120A frequency characteristic. Wherein the dashed line represents the amplitude-frequency characteristic of the low-pass filter input signal and the solid line represents the overall amplitude-frequency characteristic of the band-pass amplifier.
As shown in fig. 4, which is a circuit diagram of the differential amplifying module 130, the differential amplifying module 130 includes: the clock generator 131, the differential hysteresis control unit 134, and the differentiation unit 132 and the cascade amplification module 133 connected in series in sequence.
Wherein, the clock generator 131 is configured to process the input clock signal into a self-zeroing phase and an amplifying phase which are not overlapped. Fig. 5 is a schematic diagram of non-overlapping clocks generated by the clock generator 131. Wherein phiazFor self-zero-setting of the clock,. phi.bazFor negation of self-zeroing clocks, phiampTo amplify the clock,. phi.bampTo invert the amplified clock.
As shown in fig. 6, the differentiating unit 132 includes: a first self-zeroing switch 1321, a second self-zeroing switch 1322, a first amplifying switch 1323, a sampling capacitor C1 and a second amplifier; the first self-zeroing switch 1321 is connected in parallel with the first amplifying switch 1323, the output end Vo2 of the band-pass amplifying module is connected with the first parallel ends of the first self-zeroing switch 1321 and the first amplifying switch 1323, and the second parallel ends of the first self-zeroing switch 1321 and the first amplifying switch 1323 are sequentially connected in series with the sampling capacitor C1 and the second amplifier; the second self-zeroing switch 1322 is connected between the input end and the output end of the second amplifier; the first self-zeroing switch 1321 and the second self-zeroing switch 1322 are closed when the input clock signal is in a self-zeroing phase, and are opened when the input clock signal is in an amplifying phase; the first amplification switch 1323 is opened when the input clock signal is in the self-zeroing phase and is closed when the input clock signal is in the amplification phase.
The above-mentioned differentiating unit 132 is used to detect and amplify the difference between the front and rear periods of its input signal. In the self-zeroing phase of the clock, the self-zeroing switches at the two ends of the amplifier are closed, the left polar plate of the sampling capacitor C1 collects input signals, and the right polar plate of the sampling capacitor C1 collects offset voltage formed by self zeroing of the amplifier; in the amplification phase of the clock, the self-zeroing switches at the two ends of the amplifier are switched off, the left plate of the sampling capacitor C1 continues to collect input signals, and after the amplifier is built, amplified differential signals, namely the difference value of the input signals in the amplification phase and the self-zeroing phase, are output.
With continued reference to fig. 6, the cascaded amplification module 133 includes at least one amplification unit 1330 (two amplification units are shown in fig. 6) connected in series; the amplification unit 1330 includes: the self-zeroing circuit comprises a self-zeroing capacitor C0, an amplifier and a self-zeroing switch 1331, wherein the self-zeroing capacitor C0 is connected with the amplifier in series, and the self-zeroing switch 1331 is connected between the input end and the output end of the amplifier; the self-zeroing switch 1331 is closed when the input clock signal is in the self-zeroing phase and is open when the input clock signal is in the amplifying phase.
The cascade amplification module 133 is configured to amplify the output signal of the differentiation unit 132 until a voltage that can be recognized by the decision circuit is output. In the self-zeroing phase of the clock, a self-zeroing switch of the amplifier unit is closed, a left polar plate of a capacitor C0 collects output offset of a front stage, and a right polar plate collects offset voltage of the amplifier; in the amplifying phase of the clock, the self-zeroing switch of the amplifying unit is switched off, and the amplifier further amplifies the output signal of the previous stage. The multiple amplification units contribute to an increase in the overall amplification gain, thereby improving the detection resolution.
With continued reference to fig. 6, the differential hysteresis control unit 134 described above includes: a register and cascade subunit 1340, a self-zeroing inverting switch 1341, an amplifying inverting switch 1342 and a feedback capacitor C which are connected in series in sequence;
the input signal of the control end of the register is an input clock signal, the input clock signal is a self-zero-adjusting clock, and the register is a clock rising edge register;
the cascade subunit 1340 includes, in series, at least one amplifier or inverter (two inverters are shown);
the output end of the cascade subunit 1340 is connected in series with the auto-zero negation switch 1341 and the amplification negation switch 1342, and the other end of the amplification negation switch 1342 is connected with the output end of any amplifier in the series-connected differential unit and the cascade amplification module (in the figure, the other end of the amplification negation switch 1342 is connected with the amplifier output end of the differential unit); the feedback capacitor C is connected between the input end of the next-stage amplifier of any amplifier (in the figure, one end of the feedback capacitor C is connected with the input end of the first amplifier of the cascade amplification module) and the connecting ends of the auto-zero inverting switch C and the amplifying inverting switch; the amplifying and inverting switch 1342 is turned on when the input clock signal is in the self-zeroing phase and turned off when the input clock signal is in the amplifying phase; the auto-zero negation switch 1342 is turned off when the input clock signal is in the auto-zero phase and turned on when the input clock signal is in the amplification phase.
The differential hysteresis control unit 134 is used to achieve two effects: firstly, the influence of noise on a differential function is eliminated, and misoperation is prevented; the other is to maintain the differentiation result of the previous period when the signal differentiation value is approximate or already 0 (i.e. the voltage is saturated or temporarily stable). And the differential hysteresis control unit generates a corresponding signal according to the output voltage of the differentiator and feeds the signal back to the preamplifier or the first differentiator, so that the effect of hysteresis control is achieved.
One implementation of the differential hysteresis control unit 134 is included as shown in fig. 6: the register of the control circuit latches the output value of the last period differentiator, and the control circuit correspondingly feeds back the power supply voltage (or ground) to the preamplifier through the capacitor according to the current data of the register being high (or low), so that the hysteresis control is realized. The hysteresis voltage in the figure may be set by the following expression.
Wherein it is assumed that the working point of the input and output voltage after the self-zeroing of the amplifier is located at half of the power supply voltage, i.e. 0.5VDD(ii) a Gain is the Gain of the first differentiating unit.
As another specific configuration of the differential amplifier module circuit, as shown in fig. 7, the differential hysteresis control unit 134 includes: the register and the cascade subunit which are connected in series in sequence, and the self-zeroing inverting switch 1341, the amplifying inverting switch 1342 and the feedback capacitor C;
the input signal of the control end of the register is an input clock signal, the input clock signal is a self-zero-adjusting clock, the register is a clock rising edge register, and the input end of the register is connected with the output end of the differential amplification module;
the cascaded subcell includes, in series, at least one amplifier or inverter (two inverters are shown); the output end of the cascade subunit is connected in series with a self-zeroing inverting switch 1341 and an amplifying inverting switch 1342, and the other end of the amplifying inverting switch 1342 is connected with the output end Vo2 of the band-pass amplifying module; the feedback capacitor C is connected between the input end of the second amplifier and the connecting ends of the auto-zero negation switch 1341 and the amplification negation switch 1342; the amplifying and inverting switch 1342 is turned on when the input clock signal is in the self-zeroing phase and turned off when the input clock signal is in the amplifying phase; the auto-zero negation switch 1342 is turned off when the input clock signal is in the auto-zero phase and turned on when the input clock signal is in the amplification phase.
The decision device is a digital logic circuit and is used for processing the output of the differential amplification module so as to decide the final output result. The decision device may include a multi-way voter to filter out output glitches that the differentiator may generate due to noise.
It should be noted that the circuits in the figures are all single-ended signal processing, but the present application is also applicable to fully differential signal processing.
Fig. 8 is a schematic diagram showing a simulation of transient response of an important node of the present invention. Wherein, VINDIs ASK modulation signal from wireless charging coil, which contains data information packet; vINIs a rectified data information envelope signal; vo1Is a voltage signal passing through a band-pass filtering unit of the band-pass filtering module; voIs the output signal of the differential amplification module; voutIs the final output signal of the decision device. And the final output signal of the decision device can be further processed by combining a decoding circuit or a Microcontroller (MCU) at the later stage to obtain a digital data information packet.
The foregoing is illustrative of embodiments of the present invention, and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the embodiments of the present invention and are intended to be within the scope of the present invention.
Claims (9)
1. A demodulation circuit, comprising: the device comprises a rectifying module, a band-pass amplifying module, a differential amplifying module, a decision device and a decoding module which are connected in sequence;
the rectification module is used for rectifying the input ASK amplitude modulation signal to obtain a rectified ASK amplitude modulation signal;
the band-pass amplification module is used for filtering and amplifying the rectified ASK amplitude modulation signal to obtain an ASK envelope signal;
the differential amplification module is used for detecting and amplifying the rising edge and the falling edge of the ASK envelope signal to obtain a demodulated digital signal which can be identified by the decision device; the differential amplification module includes: the device comprises a clock generator, a differential hysteresis control unit, a differential unit and a cascade amplification module which are sequentially connected in series; the output end of the cascade amplification module is connected with a differential hysteresis control unit, and the output end of the differential hysteresis control unit is connected with the differential unit; the clock generator is connected with the differential hysteresis control unit, the differential unit and the cascade amplification module;
the decision device is used for filtering burrs of the demodulation digital signal to obtain a deburring demodulation digital signal;
and the decoding module is used for decoding the deburring demodulation digital signal to obtain a data information packet.
2. The circuit of claim 1, wherein the band pass amplification module comprises: the input direct current bias circuit, the band-pass filter unit and the buffer are connected in sequence.
3. The circuit of claim 2, further comprising: and the low-pass filter is arranged between the connection end of the band-pass filter unit and the buffer and the grounding end.
4. A circuit according to claim 2 or 3, characterized in that the band-pass filter unit comprises: the circuit comprises a first amplifier, a first capacitor, a second capacitor, a first resistor, a second resistor, a third resistor and a fourth resistor;
the first resistor and the second resistor are sequentially connected in series;
the fourth resistor and the second capacitor are sequentially connected in series;
the output end of the input direct current bias circuit is connected with one end, far away from the second capacitor, of the fourth resistor, and one end, far away from the fourth resistor, of the second capacitor is connected with the first resistor, the first capacitor and the negative input end of the first amplifier;
the second resistor, the first capacitor and the output end of the first amplifier are connected, and the connecting end of the second resistor, the first capacitor and the first amplifier is used as the output end of the band-pass filter unit;
the positive input end of the first amplifier is connected with a first power supply; the third resistor is connected between the first power source and the connection end of the first resistor and the second resistor.
5. The circuit of claim 1, wherein the clock generator is configured to process the input clock signal into a self-zeroing phase and an amplifying phase that do not overlap.
6. The circuit of claim 5, wherein the differentiating unit comprises: the device comprises a first self-zeroing switch, a second self-zeroing switch, a first amplifying switch, a sampling capacitor and a second amplifier;
the first self-zeroing switch is connected with the first amplifying switch in parallel, the output end of the band-pass amplifying module is connected with the first self-zeroing switch and the first parallel end of the first amplifying switch, and the second parallel ends of the first self-zeroing switch and the first amplifying switch are sequentially connected with the sampling capacitor and the second amplifier in series;
the second self-zeroing switch is connected between the input end and the output end of the second amplifier;
the first self-zeroing switch and the second self-zeroing switch are closed when the input clock signal is in a self-zeroing phase and are opened when the input clock signal is in an amplifying phase;
the first amplifying switch is turned off when the input clock signal is in the self-zeroing phase and is turned on when the input clock signal is in the amplifying phase.
7. The circuit of claim 6, wherein the cascaded amplification modules comprise at least one amplification cell connected in series in sequence;
the amplification unit includes: the self-zeroing circuit comprises a self-zeroing capacitor, an amplifier and a self-zeroing switch, wherein the self-zeroing capacitor is connected with the amplifier in series, and the self-zeroing switch is connected between the input end and the output end of the amplifier;
the self-zero switch is closed when the input clock signal is in a self-zero phase, and is opened when the input clock signal is in an amplification phase.
8. The circuit of claim 7, wherein the differential hysteresis control unit comprises: the automatic zero-setting and inverting circuit comprises a register, a cascade subunit, an automatic zero-setting and inverting switch, an amplifying and inverting switch and a feedback capacitor which are sequentially connected in series;
the input signal of the control end of the register is an input clock signal, the input clock signal is a self-zeroing clock, the register is a clock rising edge register, and the input end of the register is connected with the output end of the differential amplification module;
the cascade subunit comprises at least one amplifier or inverter connected in series;
the output end of the cascade subunit is connected with the auto-zeroing inverting switch and the amplifying inverting switch in series, and the other end of the amplifying inverting switch is connected with the output end of any amplifier in the differential unit and the cascade amplifying module which are connected in series; the feedback capacitor is connected between the input end of the next-stage amplifier of any amplifier and the connecting ends of the self-zero inverting switch and the amplifying inverting switch;
the amplifying and inverting switch is closed when the input clock signal is in the self-zero-adjusting phase and is opened when the input clock signal is in the amplifying phase;
the auto-zero negation switch is switched off when the input clock signal is in the auto-zero phase and is switched on when the input clock signal is in the amplification phase.
9. The circuit of claim 7,
the differential hysteresis control unit includes: the automatic zero-setting and inverting circuit comprises a register, a cascade subunit, an automatic zero-setting and inverting switch, an amplifying and inverting switch and a feedback capacitor which are sequentially connected in series;
the input signal of the control end of the register is an input clock signal, the input clock signal is a self-zeroing clock, the register is a clock rising edge register, and the input end of the register is connected with the output end of the differential amplification module;
the cascade subunit comprises at least one amplifier or inverter connected in series;
the output end of the cascade subunit is connected with the self-zeroing inverting switch and the amplifying inverting switch in series, and the other end of the amplifying inverting switch is connected with the output end of the band-pass amplifying module; the feedback capacitor is connected between the input end of the second amplifier and the connecting ends of the self-zero-setting inverting switch and the amplifying inverting switch;
the amplifying and inverting switch is closed when the input clock signal is in the self-zero-adjusting phase and is opened when the input clock signal is in the amplifying phase;
the auto-zero negation switch is switched off when the input clock signal is in the auto-zero phase and is switched on when the input clock signal is in the amplification phase.
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|---|---|---|---|---|
| CN109962871B (en) * | 2019-03-28 | 2021-07-23 | 四川中微芯成科技有限公司 | ASK amplitude modulation signal envelope detection system |
| CN110071560A (en) * | 2019-05-24 | 2019-07-30 | 深圳市乐得瑞科技有限公司 | A kind of wireless charging control circuit |
| CN116318213B (en) * | 2023-03-15 | 2024-09-27 | 浙江地芯引力科技有限公司 | Data receiving circuit and data transmission device |
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| US5949826A (en) * | 1995-12-22 | 1999-09-07 | Matsushita Electric Industrial Co., Ltd. | Data transmission and reception system |
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