CN109148499A - Pixel unit and its manufacturing method, imaging sensor and imaging device - Google Patents
Pixel unit and its manufacturing method, imaging sensor and imaging device Download PDFInfo
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- CN109148499A CN109148499A CN201810964921.8A CN201810964921A CN109148499A CN 109148499 A CN109148499 A CN 109148499A CN 201810964921 A CN201810964921 A CN 201810964921A CN 109148499 A CN109148499 A CN 109148499A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/10—Integrated devices
- H10F39/12—Image sensors
- H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/80—Constructional details of image sensors
- H10F39/803—Pixels having integrated switching, control, storage or amplification elements
- H10F39/8037—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor
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Abstract
This disclosure relates to pixel unit and its manufacturing method, imaging sensor and imaging device.A kind of pixel unit, comprising: substrate has recess in the surface of the substrate, wherein the bottom surface of the recess includes at least two parts, the distance on the surface of two parts away from the substrate adjacent to each other is different at least two part；Photosensitive element in the substrate；The transistor being electrically connected with the photosensitive element, the transistor include: the gate insulating layer in the recess of the substrate, and the gate insulating layer covers the bottom surface of the recess；Channel formation region in the substrate, the channel formation region is below the bottom surface of the recess；And grid, at least part of the grid is in the recess and on the bottom surface of the recess.
Description
Technical field
This disclosure relates to pixel unit and its manufacturing method, imaging sensor and imaging device.
Background technique
In recent years, cmos image sensor (CIS) is rapidly developed.It is higher but there are brightness in imaging viewing field
Point light source or when bright area or when imaging sensor is by time exposure, will appear Blooming (halation) effect in CIS
It answers.This is because CIS sensor pixel, when by strong illumination, the illumination that spot zone pixel obtains is too strong, in pixel
The photoelectron number that photosensitive element (for example, photodiode) generates under strong light is more than the maximum that charge storage cell can store
Electron number and overflow, the electronics of spilling will enter adjacent pixel along row or column direction, so that Blooming (halation) occurs in image
Phenomenon.This meeting imaging definition is decreased obviously, and seriously affects the quality of imaging, information is caused to lose.
Therefore, it is necessary to improved pixel unit and its manufacturing methods, imaging sensor and imaging device.
Summary of the invention
According to one aspect of the disclosure, a kind of pixel unit is provided, comprising: substrate has the table in the substrate
Recess in face, it is adjacent to each other at least two part wherein the bottom surface of the recess includes at least two parts
The distance on the surface of two parts away from the substrate is different；Photosensitive element in the substrate；With the photosensitive element
The transistor of electrical connection, the transistor include: the gate insulating layer in the recess of the substrate, and the gate insulating layer covers
Cover the bottom surface of the recess；Channel formation region in the substrate, bottom surface of the channel formation region in the recess
Lower section；And grid, at least part of the grid is in the recess and on the bottom surface of the recess.
In one embodiment, in source electrode and drain electrode of at least part of the photosensitive element as the transistor
One；The transistor further includes doped region in the substrate, as another in the source electrode and drain electrode；The ditch
The both ends in road formation area are adjacent with described at least part of the photosensitive element and the doped region respectively.
In one embodiment, at least two part includes first part and second part, the second part ratio
The first part is further from the photosensitive element, and the second part is than the first part further from described in the substrate
Surface, and the gate insulating layer covers at least two part of the bottom surface.
In one embodiment, the bottom surface of the recess further include: one or more side walls, each side wall it is described extremely
Between two parts adjacent to each other in few two parts, wherein the gate insulating layer also covers one or more of
Side wall.
In one embodiment, at least two part further includes Part III, and the Part III is than described first
Part and second part are further from the surface of the substrate, and the Part III is than the first part and second
Divide further from the photosensitive element.
In one embodiment, the doped region is connected to high potential.In one embodiment, the doped region is floating
Diffusion region.
In one embodiment, the transistor further include: the recess side-walls and in the grid and institute
State the side wall insulating layer between substrate.
In one embodiment, the pixel unit further include: the recess side-walls and in the grid and
Side wall insulating layer between the substrate, wherein the side wall insulating layer includes between the photosensitive element and the grid
Part, and the part between the doped region and the grid.
In one embodiment, the pixel unit further include: transmission transistor is electrically connected to the photosensitive element；With
And charge storage cell, it is electrically connected to the transmission transistor, comes from the sense by what transmission transistor transmitted for storing
The optical charge of optical element, wherein in source electrode and drain electrode of at least part of the photosensitive element as the transmission transistor
One.
In one embodiment, the pixel unit is CMOS active pixel sensor pixel.
According to one aspect of the disclosure, a kind of imaging device, including imaging sensor, described image sensor are provided
Including the pixel unit according to any embodiment.
According to one aspect of the disclosure, a kind of method for manufacturing pixel unit is provided, comprising: provide semiconductor lining
Bottom；Recess is formed in the surface of the semiconductor substrate, the bottom surface of the recess includes at least two parts, it is described at least
The distance on the surface of two parts away from the substrate adjacent to each other is different in two parts；In the bottom surface of the recess
Place forms the gate insulating layer for being used for transistor, and side wall insulating layer is formed at the side surface of the recess；And form institute
The grid of transistor is stated, at least part of the grid is in the recess and on the gate insulating layer.
In one embodiment, the substrate includes photosensitive element in the substrate, and the photosensitive element is at least
A part is as one in the source electrode and drain electrode of the transistor.
In one embodiment, the method also includes: form photosensitive element in the substrate, the photosensitive element
At least part is as one in the source electrode and drain electrode of the transistor.
In one embodiment, the method also includes: form doped region in the substrate, the doped region is as institute
State another in source electrode and drain electrode；Wherein the both ends of the channel formation region of the transistor respectively with the institute of the photosensitive element
It states at least part and the doped region is adjacent.
In one embodiment, it includes: to utilize patterned mask that recess is formed in the surface of the semiconductor substrate,
The substrate is etched to form the first part of the recess；And patterned mask is utilized, the substrate is etched to be formed
The second part of the recess, so that at least two part of the bottom surface of the recess includes first part and second
Point, the second part of the bottom surface than the bottom surface first part further from the photosensitive element, the bottom surface
Second part than the bottom surface first part further from the surface of the substrate, and the gate insulating layer covers
At least two part of the bottom surface.
In one embodiment, recess is formed in the surface of the semiconductor substrate further include: cover using patterned
Mould etches the substrate to form the Part III of the recess, wherein and at least two part further includes Part III,
The Part III than the first part and second part further from the surface of the substrate, and the Part III
Than the first part and second part further from the photosensitive element.
In one embodiment, the bottom surface of the recess further include: one or more side walls, each side wall it is described extremely
Between two parts adjacent to each other in few two parts, wherein the gate insulating layer also covers one or more of
Side wall.
In one embodiment, it is formed in the bottom surface of the recess and is used for the gate insulating layer of transistor and described
It includes: the deposition of insulative material layer on the substrate for foring the recess that side wall insulating layer is formed at the side surface of recess, so that
Bottom surface and the side surface of the recess are covered less；And it is optionally removed the insulation material layer, to retain the insulation
Part of the material layer in the recess.
In one embodiment, it is formed in the bottom surface of the recess and is used for the gate insulating layer of transistor and described
It includes: to carry out oxidation processes to the substrate for foring the recess that side wall insulating layer is formed at the side surface of recess, exhausted to be formed
Edge material layer；And it is optionally removed the insulation material layer, with the insulation material for the formation being retained in the recess
The part of the bed of material.
In one embodiment, the grid for forming the transistor includes: in the substrate for foring the gate insulating layer
Upper deposition of gate material layer；And the gate material layers are optionally removed, to retain the gate material layers described recessed
Part in falling into.
In one embodiment, the pixel unit is CMOS active pixel sensor (APS) pixel.
By the detailed description referring to the drawings to the exemplary embodiment of the disclosure, the other feature of the disclosure and its
Advantage will become apparent.
Detailed description of the invention
The attached drawing for constituting part of specification describes embodiment of the disclosure, and together with the description for solving
Release the principle of the disclosure.
The disclosure can be more clearly understood according to following detailed description referring to attached drawing, in which:
Fig. 1 shows a kind of schematic circuit of pixel unit comprising five transistors (5T)；
Fig. 2 shows the schematic cross-sectionals of spilling (overflow) transistor in 5T pixel unit according to prior art
Figure；
Fig. 3 shows the potential diagram for overflowing transistor according to prior art；
Fig. 4 A shows the Some illustrative sectional view according to the pixel unit of an embodiment of the present disclosure；
Fig. 4 B shows the Some illustrative sectional view of the pixel unit according to the disclosure another embodiment；
Fig. 5 shows the example flow diagram of the manufacturing method of the pixel unit according to an embodiment of the present disclosure；
Showing for some steps of the manufacturing process of the pixel unit according to an embodiment of the present disclosure is shown respectively in Fig. 6 A-6I
Meaning property sectional view；
Fig. 7 A-7F shows showing for some steps of the manufacturing process of the pixel unit according to the disclosure another embodiment
Meaning property sectional view；
Fig. 8 shows the schematic block diagram of the imaging device according to an embodiment of the present disclosure；
Fig. 9 is shown to be illustrated according to the potential of the pixel unit of the embodiment of the present disclosure.
Note that same appended drawing reference is used in conjunction between different attached drawings sometimes in embodiment explained below
It indicates same section or part with the same function, and omits its repeated explanation.In the present specification, using similar label
Indicate therefore similar terms once being defined in a certain Xiang Yi attached drawing, then do not need in subsequent attached drawing to it with letter
It is further discussed.
In order to make it easy to understand, position, size and range of each structure shown in attached drawing etc. etc. do not indicate practical sometimes
Position, size and range etc..Therefore, disclosed invention is not limited to position, size and range disclosed in attached drawing etc. etc..
Specific embodiment
The various exemplary embodiments of the disclosure are described in detail now with reference to attached drawing.It should be noted that unless in addition specific
Illustrate, unlimited this public affairs of system of component and the positioned opposite of step, numerical expression and numerical value otherwise illustrated in these embodiments
The range opened.In addition, technology, method and apparatus known to person of ordinary skill in the relevant may be not discussed in detail,
But in the appropriate case, the technology, method and apparatus should be considered as authorizing part of specification.
In the word "front", "rear" in specification and claim, "top", "bottom", " on ", " under " etc., if deposited
If, it is not necessarily used to describe constant relative position for descriptive purposes.It should be appreciated that the word used in this way
Language be in appropriate circumstances it is interchangeable so that embodiment of the disclosure described herein, for example, can in this institute
It is operated in those of description show or other other different orientations of orientation.
Any implementation of this exemplary description be not necessarily to be interpreted it is more preferred than other implementations or
It is advantageous.Moreover, the disclosure not by given in above-mentioned technical field, background technique, summary of the invention or specific embodiment go out
Theory that is any stated or being implied is limited.
As used in this, word " substantially " means comprising the appearance by the defect, device or the element that design or manufacture
Any small variation caused by difference, environment influence and/or other factors.Word " substantially " also allows by ghost effect, makes an uproar
Caused by sound and the other practical Considerations being likely to be present in actual implementation with perfect or ideal situation
Between difference.
Foregoing description can indicate to be " connected " or " coupling " element together or node or feature.As used herein
, unless explicitly stated otherwise, " connection " means an element/node/feature and another element/node/feature in electricity
Above, it is directly connected (or direct communication) mechanically, in logic or in other ways.Similarly, unless explicitly stated otherwise,
" coupling " mean an element/node/feature can with another element/node/feature in a manner of direct or be indirect in machine
On tool, electrically, in logic or in other ways link to allow to interact, even if the two features may not direct
Connection is also such.That is, " coupling " is intended to encompass the direct connection and connection, including benefit indirectly of element or other feature
With the connection of one or more intermediary elements.
In addition, middle certain term of use can also be described below, and thus not anticipate just to the purpose of reference
Figure limits.For example, unless clearly indicated by the context, be otherwise related to the word " first " of structure or element, " second " and it is other this
Class number word does not imply order or sequence.
It should also be understood that one word of "comprises/comprising" as used herein, illustrates that there are pointed feature, entirety, steps
Suddenly, operation, unit and/or component, but it is not excluded that in the presence of or increase one or more of the other feature, entirety, step, behaviour
Work, unit and/or component and/or their combination.
In the disclosure, therefore term " offer " " it is right to provide certain from broadly by covering all modes for obtaining object
As " including but not limited to " purchase ", " preparation/manufacture ", " arrangement/setting ", " installation/assembly ", and/or " order " object etc..
It is not to this public affairs it should also be understood that being merely illustrative below to the description of at least one exemplary embodiment
It opens and its application or any restrictions used.
Fig. 1 shows a kind of schematic circuit of pixel unit comprising five transistors (5T).As shown in Figure 1, the pixel
Unit includes photosensitive element (such as photodiode PD) and charge storage cell (for example, floating diffusion region FD, can wait
Regard capacitor C as in effect groundFD).The pixel unit further includes five transistors: transmission transistor (transmission gate) TX, and grid receives
TX signal is transmitted, one in source electrode and drain electrode is connected to one end of photodiode PD, another is connected to floating diffusion region
FD；Resetting Switching Trst, grid receive reset signal, and one in source electrode and drain electrode is connected to reset voltage Vrst, another
It is a to be connected to FD；Transistor Tsf, grid are connected to FD, and one in source electrode and drain electrode is connected to supply voltage Vdd, can
Operation is used as source follower；Selection switch (Tsel), grid receive selection signal, and one in source electrode and drain electrode is connected to crystalline substance
Another in the source electrode and drain electrode of body pipe Tsf, another in source electrode and drain electrode is connected to wiring (for example, column output line)；
And switch T5, grid receive control signal, one in source electrode and drain electrode is connected to described one end of PD, another connection
To current potential (in Fig. 1, T5 voltage).Each switch can be formed by transistor respectively.The other end of photodiode PD can connect
Be connected to low potential, for example, (0V).
Such pixel unit is often referred to as 5T pixel unit.In photosensitive element by active device (for example, light-emitting diodes
Pipe) formed in the case where, pixel unit is also referred to as APS (CMOS active pixel sensor) pixel unit.
For 5T APS pixel unit, since switch T5 is generally permanently attached to high potential (for example, power supply potential Vdd),
Therefore, because DIBL (potential barrier caused by draining reduces) effect, electric leakage (leakage) are larger.On the other hand, in imaging sensor
When by time exposure, the temperature of device or chip rises, and becomes to deteriorate so as to cause charge leakage and noise.In these situations
Under, in the optical charge saturation that photodiode PD is generated (for example, there are the higher point light sources of brightness or bright in imaging viewing field
When region or when imaging sensor is by time exposure), optical charge (for example, photoelectron), which is easier to " to overflow " (spill), to be arrived
Adjacent pixel, to cause halo effect or aggravate halo effect.Therefore, switch T5 often referred to as overflows transistor.
Fig. 2 shows the schematic sectional views of the spilling transistor in 5T pixel unit according to prior art.Fig. 3 is shown
Potential for overflowing transistor according to prior art illustrates.As shown in Fig. 2, photodiode PD is connected by transmission transistor
It is connected to floating diffusion region FD, and is connected to high potential Vdd by overflowing transistor.The person skilled in the art will easily understand this
In the frame of shown part or part be only exemplary, be not offered as the actual profile of the part or part.In addition,
Under some cases, it is alternatively possible to pinned diode (pin diode) be formed above photodiode PD, to reduce surface
The influence of state and/or reduction dark current etc..Therefore, photodiode PD and pinned diode can be collectively referred to sometimes photosensitive
Element.Here, photosensitive element can be any element that can convert light to electricity.
However, as shown in figure 3, barrier height is protected when the drain electrode for overflowing transistor is connected to low potential (for example, 0V)
It holds, photoelectron is not easy to cross potential barrier, enters adjacent pixel (for example, by providing the wiring of T5 voltage (Fig. 1)).And it is overflowing
When the drain electrode of transistor is connected to high potential (for example, Vdd), due to DIBL effect etc., barrier height is lowered, and potential barrier is wide
Degree is also reduced by, and photoelectron is easy to cross potential barrier and enters adjacent pixel, to cause halo effect or be allowed to serious.
Based on above-mentioned cognition, present inventor proposes the technology instructed such as the application, existing to be mitigated or overcome
There are one or more problems of technology.
Fig. 4 A shows the Some illustrative sectional view according to the pixel unit of an embodiment of the present disclosure.Such as Fig. 4 A institute
Show, pixel unit includes substrate 101.In some instances, substrate 101 may, for example, be P type substrate (P-sub).For substrate
101 structure and material is not particularly limited, as long as it, which has, can be used for being formed the component of subsequent explanation or having for component
Active layer.Therefore, in certain embodiments, under appropriate circumstances, term " substrate " may refer to entire substrate (for example,
Silicon substrate), or a part (for example, active layer) of entire substrate.
As shown in the figure, substrate 101 has the recess 105 in the surface of the substrate 103 (such as more preferably from Fig. 6 A
It arrives).Recess 105 includes bottom surface 107 and side wall 1051.Bottom surface 107 may include at least two parts.It is shown in figure
Three parts: first part 1071, second part 1073 and Part III 1075；However the present disclosure is not limited thereto.At other
Embodiment in, 105 bottom surface 107 of being recessed may include two parts, such as first part 1071 and second part 1073；
In alternate embodiments, 105 bottom surface 107 of being recessed may include four or more parts.
The pixel unit further includes photosensitive element in the substrate, as indicated by appended drawing reference 109.It is described photosensitive
Element can be photodiode.Here, the person skilled in the art will easily understand can be in the first conduction type (for example, P
Type) substrate (in other words, active area) 101 in form second conduction type (for example, N-type) opposite with the first conduction type
Doped region 109, in this way, light emitting diode can be formed.Here, indication light diode is equally come with appended drawing reference 109.Separately
Outside, in some embodiments, the conduction type that can also be further formed on doped region 109 is opposite with doped region 109
Doped region 141 (for example, p-type), is thusly-formed pinned diode.Here, two pole of pinning is equally indicated with appended drawing reference 141
Pipe.In addition, under appropriate circumstances, so-called photosensitive element in present specification may refer to depicted herein or described
One in following: photodiode and photodiode and pinned diode.
The pixel unit further includes the transistor 120 being electrically connected with the photosensitive element, as the dotted ellipse in figure is signified
Show.As illustrated in the drawing, transistor 120 includes the gate insulating layer 1201 in the recess 105 of the substrate.The grid
Insulating layer 1201 covers the bottom surface 107 of the recess.Gate insulating layer 1201 can be formed by the one or more in following:
The oxide of silicon, the nitride of silicon, oxynitride of silicon etc..Structure and material for gate insulating layer etc. does not limit particularly
System, those skilled in the art, which can according to need, comes unrestricted choice suitable material and structure.
Transistor 120 further includes channel formation region 1203 in the substrate.The channel formation region 1203 is described
The lower section of the bottom surface 107 of recess.
Transistor 120 further includes grid 1205.As shown in the figure, at least part of grid 1205 is in the recess 105
In and on the bottom surface of the recess 107.Grid 1205 can be formed by such as polysilicon.For grid structure and
Material etc. is not particularly limited, and those skilled in the art, which can according to need, comes unrestricted choice suitable material and structure.
As shown in the figure, the bottom surface 107 of the recess includes at least two parts, and at least two part can be by
The distance for being configured to the surface 103 of two parts away from the substrate adjacent to each other is different.For example, second part 1073 can
To be configured as the surface 103 than first part 1071 further from substrate.In some embodiments, Part III 1075 can
To be configured as the surface 103 than second part 1073 further from substrate.Although being shown in figure the bottom surface of recess
First to Part III 1071,1073 and 1075, however the present disclosure is not limited thereto；For example, in other examples can be with
Including more parts, or omit the first one into Part III.
As shown in the figure, second part 1073 can be configured as than first part 1071 further from the photosensitive element
109.Part III 1075 (if any) can be configured as than second part 1073 further from photosensitive element 109.In this way,
Inclined channel can be formed, as shown in the arrow direction in figure.Here, it should be appreciated that first to Part III arrangement
It is not limited to；It in other examples, can be using other arrangements.As shown in the figure, the gate insulating layer
At least two part of the 1201 covering bottom surfaces.
In some embodiments, as shown in the figure, the bottom surface of the recess can also include one or more side walls
1072,1074.Each side wall is between two parts adjacent to each other at least two part.For example, side wall 1072
Between the first part 1071 and second part 1073 on the surface of recess.Second part of the side wall 1074 on the surface of recess
Between 1073 and Part III 1075.In this case, gate insulating layer 1201 also covers one or more of side walls.It answers
Understand, although in the figure of the application, at least two part of the bottom surface of recess (for example, first to Part III) quilt
It is shown as lateral, side wall is shown as longitudinal, but the present disclosure is not limited to the bottom surfaces of such step.In certain implementations
In example, sidewall sections may be not present；For example, each section can be each other continuously at least two part.
In the case where the bottom surface of recess includes side wall, the length for the channel to be formed under it can be increased, thus
It further reduced the influence of DIBL effect.
It should be understood that for embodiment shown in figure, gate insulating layer corresponding with the bottom surface of the step of recess
1201 and channel formation region 1203 also will be step or close to step.
In some embodiments, at least part of the photosensitive element can be used as the source electrode and drain electrode of transistor 120
In one.As shown in the figure, at least part of doped region 141 or doped region 109 can be used as the source electrode of transistor 120
With one in drain electrode.Transistor 120 can also include doped region 111 in the substrate, as the source electrode and drain electrode
In another.The both ends of the channel formation region can respectively with described at least part of the photosensitive element and described mix
Miscellaneous area is adjacent.In some embodiments, doped region 111 may be coupled to high potential, such as the power supply potential for pixel unit
Vdd.In some embodiments, the high potential can be than photosensitive element the other end (that is, not with transmission transistor or spilling
One end of transistor connection) the high current potential of the current potential that is connected.Doped region 111 can be floating diffusion region.
What needs to be explained here is that the first part 1071 of the bottom surface 107 of recess 105 is (that is, with photosensitive member in figure
The adjacent part of part) it is shown as horizontally substantially in the side of doped region 141, accordingly, pair of channel formation region 1203
The one end (left-hand end in figure) answered and doped region 141 are adjacent；However the present disclosure is not limited thereto.For example, in other embodiments,
The first part 1071 of the bottom surface 107 of recess 105 can be configured as horizontally substantially in the side of doped region 109；Ditch
The corresponding one end (left-hand end in figure) in road formation area 1203 can be configured as with one in doped region 109 and 141 or
The two is adjacent.
As shown in the figure, transistor 120 can also include: at the side wall 1051 of the recess and in the grid and
Side wall insulating layer 1207 between the substrate.As shown in the figure, side wall insulating layer be included in the photosensitive element (109 and/or
141) part between the grid 1205, and the part between the doped region 111 and the grid 1205；The two
All indicated with 1207.
In some embodiments, which can also include: transmission transistor 130, such as the dotted ellipse frame in figure
Indicated, it is electrically connected to the photosensitive element；And charge storage cell 133, it is electrically connected to the transmission transistor, is used
In the optical charge from the photosensitive element that storage is transmitted by transmission transistor.At least part of the photosensitive element can
Using one in the source electrode and drain electrode as the transmission transistor.The charge storage cell can be such as capacitor or
Any element of charge, such as floating diffusion region can be stored.
The person skilled in the art will easily understand the pixel unit can be CMOS active pixel sensor APS pixel.
Fig. 4 B shows the Some illustrative sectional view of the pixel unit according to the disclosure another embodiment.Shown in Fig. 4 B
Each component of pixel unit corresponded to substantially with each component of pixel unit shown in Fig. 4 A or identical, difference is: in Fig. 4 B
Shown in embodiment, the position that gate insulating layer 1201 and side wall insulating layer 1207 are formed is different, the technique formed in other words
Difference causes it to be formed by position difference.Therefore, repeated explanation no longer is carried out to component identical or corresponding with Fig. 4 A herein.
In the embodiment shown in Fig. 4 A, gate insulating layer 1201 is on the bottom surface 107 of recess 105, lateral wall insulation
Layer 1207 is formed on the surface of the side wall 1051 of recess 105.And in the embodiment shown in Fig. 4 B, gate insulating layer 1201
It is formed at the bottom surface 107 of recess 105, and can be with a part of substrate；Similarly, side wall insulating layer 1207 is formed in recess
At the surface of 105 side wall 1051, and consume a part of substrate.Therefore, it in the embodiment shown in Fig. 4 B, is formed by recessed
It falls into and is different from the recess formed in the embodiment of Fig. 4 A.In subsequent explanation, these difference will be described in more detail.
Fig. 5 shows the example flow diagram of the manufacturing method of the pixel unit according to an embodiment of the present disclosure.Fig. 6 A-6H points
The schematic sectional view of some steps of the manufacturing process of pixel unit according to an embodiment of the present disclosure is not shown.It ties below
Close the manufacturing method that Fig. 5 and Fig. 6 A-6H is illustrated the pixel unit according to the embodiment of the present disclosure.
In step S510, semiconductor substrate 101 is provided, as shown in Figure 6A.Substrate 101 has surface 103.In some implementations
In example, it can be pre-formed at least part of photosensitive element, such as doped region 109 ' in the substrate.
It in another embodiment, optionally, can be at least one of formation photosensitive element in the substrate in step S515
Point.
In step S520, recess 105 is formed in the surface of the semiconductor substrate 103, as shown in Figure 6 D.Recess 105
With bottom surface 107 and side surface 1051.Bottom surface 107 may include at least two parts.In at least two part
The distance on the surface of two parts away from the substrate adjacent to each other is different.
It in some embodiments, can be by the way that the recess be formed in the surface of the semiconductor substrate as follows: in step
Rapid S521 etches the substrate to form the first part 105_1 of the recess, such as using patterned mask (not shown)
Shown in Fig. 6 B；And patterned mask (not shown) is utilized in step S523, the substrate is etched to form the recess
Second part 105_2, as shown in Figure 6 C.At least two part of the bottom surface of the recess includes 1071 He of first part
Second part 1073.The second part of the bottom surface than the bottom surface first part further from the photosensitive element.Institute
The first part of the second part of bottom surface than the bottom surface is stated further from the surface of the substrate.
In some embodiments, recess is formed in the surface of the semiconductor substrate further include: in step S525, utilize
Patterned mask (not shown) etches the substrate to form the Part III of the recess, as shown in Figure 6 D.It is described at least
Two parts further include Part III 1075, and the Part III is than the first part and second part further from the substrate
The surface, and the Part III than the first part and second part further from the photosensitive element.
In some embodiments, the bottom surface of the recess further include: one or more side walls, each side wall it is described extremely
Between two parts adjacent to each other in few two parts.
In some embodiments, optionally, the method can also include: in step S565, formed recess after, it is right
Channel formation region is doped, with modulation theresholds.
In step S530, the gate insulating layer 1201 for being used for transistor 120 is formed at the bottom surface 107 of the recess,
And side wall insulating layer 1207 is formed at the side surface of the recess 1051, such as Fig. 6 E.The gate insulating layer covers the bottom
At least two part on surface.In the case where the bottom surface further includes the side wall, the gate insulating layer also covers
Cover the side wall.
In some embodiments, it is formed in the bottom surface of the recess and is used for the gate insulating layer of transistor and described
It may include: to deposit on the substrate for foring the recess in step S531 that side wall insulating layer is formed at the side surface of recess
Insulation material layer (not shown), at least to cover bottom surface and the side surface of the recess；And in step S533, choosing
The insulation material layer is removed, selecting property to retain part of the insulation material layer in the recess.
In step S540, the grid 1205 of the transistor is formed, at least part of the grid is in the recess
And on the gate insulating layer 1201, as fig 6 f illustrates.In some embodiments, the grid packet of the transistor is formed
It includes: the deposition of gate material layer (not shown) on the substrate for foring the gate insulating layer；And it is optionally removed described
Gate material layers, to retain part of the gate material layers in the recess.
In some embodiments, at least part of the photosensitive element can be used as the transistor 120 source electrode and
One in drain electrode.
It is alternatively possible to form doped region 141 in the substrate.Doped region 141 can be by leading the injection of doped region 109 '
Electric type opposite to that impurity is formed.And thereby form doped region 109.Doped region 141 can be in the upper of doped region 109 '
Portion, close to or at the surface of substrate；Namely on doped region 109.
In some embodiments, the method can be with further include: in step S550, doping is formed in the substrate 101
Area 111, as fig 6 f illustrates, the doped region is as another in the source electrode and drain electrode of the transistor 120.In some implementations
Example in, the both ends of the channel formation region 1203 of the transistor 120 respectively with described at least part of the photosensitive element and
The doped region 111 is adjacent.
It will be understood by those skilled in the art that the pixel unit can be CMOS active pixel sensor APS pixel.
In some embodiments, the method can also include forming charge storage cell 133 and transmission transistor 130
Step, as shown in fig. 6i.Charge storage cell 133 and transmission transistor 130 can use technique as known in the art and material
Material does not carry out the discussion of more details to be formed to it here.It should be understood that some in certain implementations, in these steps
Either certain steps can carry out simultaneously with some in step describe above or certain steps.
Fig. 7 A-7F shows showing for some steps of the manufacturing process of the pixel unit according to the disclosure another embodiment
Meaning property sectional view.The description of Fig. 5 and Fig. 6 A-6I above in conjunction substantially of its technical process it is same or similar, difference is: in institute
The bottom surface for stating recess forms the gate insulating layer for transistor and forms lateral wall insulation at the side surface of the recess
Oxidation technology is utilized in the step of layer.
It is similar with Fig. 6 D, recess is formed in the substrate, as shown in Figure 7 A.Recess 105 ' has bottom surface 107 ' and side
Surface 1051 '.Bottom surface 107 ' may include at least two parts.Two parts adjacent to each other at least two part
The distance on the surface away from the substrate is different.In some embodiments, described at least two of the bottom surface of the recess
Part includes first part 1071 ' and second part 1073 '.First of the second part of the bottom surface than the bottom surface
Divide further from the photosensitive element.The second part of the bottom surface than the bottom surface first part further from the substrate
The surface.In further embodiments, at least two part further includes Part III 1075 ', the Part III
Than the first part and second part further from the surface of the substrate, and the Part III is than described first
Point and second part further from the photosensitive element.In some embodiments, the bottom surface of the recess further include: one or more
A side wall 1072 ', 1074 ', each side wall is between two parts adjacent to each other at least two part.
It is alternatively possible to be doped to channel formation region, after forming recess with modulation theresholds.
Later, the gate insulating layer 1201 for being used for transistor 120 is formed at the bottom surface 107 of the recess, and in institute
Formation side wall insulating layer 1207 at the side surface 1051 of recess is stated, as shown in Figure 7 B.
In some embodiments, it is formed in the bottom surface of the recess and is used for the gate insulating layer of transistor and described
Formed at the side surface of recess side wall insulating layer may include: in step S535 (Fig. 5), to form the substrate of the recess into
Row oxidation processes, to form insulation material layer；And in step S537, it is optionally removed the insulation material layer, to retain
The part of the insulation material layer of formation in the recess.The oxidation processes can be by the Surface Oxygen of the substrate exposed
Change, to form conductor oxidate, such as silica.The mode of oxidation processes is not particularly limited.Art technology
Personnel can according to need, for example, can requirement according to process flow to heat budget, also select oxidation technology appropriate and oxygen
Agent etc..
In this way, a part on the surface (for example, surface in recess 105) of the exposing of substrate is oxidized.In other words,
Recess 105 ' further extends into substrate, to form recess 105.The recess 105 being thusly-formed have bottom surface 107 and
Side surface 1051.As shown in Figure 7 B, bottom surface 107 may include at least two parts.Phase each other at least two part
The distance on the adjacent surface of two parts away from the substrate is different.In some embodiments, the bottom surface of the recess
At least two part includes first part 1071 and second part 1073.The second part of the bottom surface is than the bottom table
The first part in face is further from the photosensitive element.The second part of the bottom surface is more farther than the first part of the bottom surface
The surface from the substrate.In further embodiments, at least two part further includes Part III 1075, described
Part III is than the first part and second part further from the surface of the substrate, and the Part III compares institute
First part and second part are stated further from the photosensitive element.In some embodiments, the bottom surface of the recess further include:
One or more side walls 1072,1074, each side wall is between two parts adjacent to each other at least two part.
Later, the grid 1205 of the transistor is formed, at least part of the grid is in the recess and in institute
It states on gate insulating layer 1201, as seen in figure 7 c.
It is alternatively possible to form doped region 141 in the substrate, as illustrated in fig. 7d.Doped region 141 can be in doped region 109
On, close to or at the surface of substrate.
Then, doped region 111 is formed in the substrate 101, as seen in figure 7e, the doped region is as the transistor
Another in 120 source electrode and drain electrode.
In some embodiments, the method can also include forming charge storage cell 133 and transmission transistor 130
Step, as shown in fig. 6i.Charge storage cell 133 and transmission transistor 130 can use technique as known in the art and material
Material does not carry out the discussion of more details to be formed to it here.It should be understood that some in certain implementations, in these steps
Either certain steps can carry out simultaneously with some in step describe above or certain steps.
Fig. 8 shows the schematic block diagram of the imaging device according to an embodiment of the present disclosure.According to some realities of the disclosure
Example is applied, a kind of imaging sensor is additionally provided comprising the pixel unit according to any embodiment.According to the one of the disclosure
A little embodiments, additionally provide a kind of imaging device comprising described image sensor.
Fig. 9 is shown to be illustrated according to the potential of the pixel unit of the embodiment of the present disclosure.As shown in figure 9, according to the disclosure
Technology reduces electric leakage, reduces signal noise.To reduce a possibility that optical charge spills into adjacent pixel, improve
Image quality.In addition, channel length can be increased in the case where the bottom surface of recess includes sidewall sections, thus further
Reduce the influence of DIBL effect.In this way, electric leakage and noise can be further decreased, the height and width of potential barrier are improved, into one
Step improves image quality.
In accordance with an embodiment of the present disclosure, improved imaging sensor and its manufacturing method and imaging device can be provided.
According to some embodiments of the present disclosure, image quality can be improved in a cost efficient manner.
It should be appreciated by those skilled in the art that description operates the boundary between (or step) only in the above-described embodiments
It is illustrative.Multiple operations can be combined into single operation, and single operation can be distributed in additional operation, and be operated
It can at least partially overlappingly execute in time.Moreover, alternative embodiment may include multiple examples of specific operation, and
And it can change operation order in other various embodiments.But others are modified, variations and alternatives are equally possible.
Therefore, the specification and drawings should be counted as illustrative and not restrictive.
Although being described in detail by some specific embodiments of the example to the disclosure, the skill of this field
Art personnel it should be understood that above example merely to be illustrated, rather than in order to limit the scope of the present disclosure.It is disclosed herein
Each embodiment can in any combination, without departing from spirit and scope of the present disclosure.It is to be appreciated by one skilled in the art that can be with
A variety of modifications are carried out without departing from the scope and spirit of the disclosure to embodiment.The scope of the present disclosure is limited by appended claims
It is fixed.
Claims (10)
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109904183A (en) * | 2019-02-25 | 2019-06-18 | 德淮半导体有限公司 | Image sensor and method of forming the same |
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| KR20070071018A (en) * | 2005-12-29 | 2007-07-04 | 매그나칩 반도체 유한회사 | Image sensor and its manufacturing method |
| CN103024295A (en) * | 2011-09-22 | 2013-04-03 | 株式会社东芝 | Solid-state imaging device and imager |
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Application publication date: 20190104 |