CN109148451B - Static random access memory cell array and method of forming the same - Google Patents
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- CN109148451B CN109148451B CN201710963096.5A CN201710963096A CN109148451B CN 109148451 B CN109148451 B CN 109148451B CN 201710963096 A CN201710963096 A CN 201710963096A CN 109148451 B CN109148451 B CN 109148451B
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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Abstract
本发明公开一种静态随机存取存储器单元阵列及其形成方法。该形成静态随机存取存储器单元阵列的方法包含有下述步骤。首先，图案化而形成多个鳍状结构于一基底上，其中此些鳍状结构包含多个主动鳍状结构以及多个牺牲鳍状结构，各通道晶体管(PG FinFET)与对应的一降压晶体管(PD FinFET)至少共享一主动鳍状结构，在一存储器单元中二相邻的升压晶体管(PU FinFET)跨设的二主动鳍状结构之间设置有至少一牺牲鳍状结构。接着，移除此些牺牲鳍状结构的至少一部分。
The invention discloses a static random access memory cell array and a method for forming the same. The method of forming a static random access memory cell array includes the following steps. First, patterning to form a plurality of fin structures on a substrate, wherein the fin structures include a plurality of active fin structures and a plurality of sacrificial fin structures, each pass transistor (PG FinFET) and a corresponding buck The transistors (PD FinFET) share at least one active fin structure, and at least one sacrificial fin structure is disposed between two active fin structures spanned by two adjacent boost transistors (PU FinFET) in a memory cell. Next, at least a portion of the sacrificial fin structures are removed.
Description
Technical Field
The present invention relates to an sram cell array and a method for forming the same, and more particularly, to an sram cell array using a sacrificial fin structure and a method for forming the same.
Background
Random Access Memory (RAM) can read data and write data when used, and the data disappears immediately after power is turned off. Since the data of the ram is easy to change, it is commonly used in a pc as a memory for temporarily storing data. The random access memory can be further subdivided into "Dynamic" and "Static".
A "Dynamic Random Access Memory (DRAM)" is called "Dynamic (Dynamic RAM)" because 1bit (1bit) of data is stored in 1 transistor plus 1 capacitor, and power must be periodically supplied to maintain the stored data when the DRAM is used. Dynamic random access memories are simpler in construction (1 transistor plus 1 capacitor to store 1bit of data) resulting in slower access speeds (longer time is required for the capacitor to charge and discharge), but are also less costly and therefore are generally made with higher capacity but lower speed requirements, for example: main memory (main memory) commonly used on the motherboard of a personal computer.
A Static Random Access Memory (SRAM) is called a Static RAM (Static RAM) because it stores 1bit (1bit) of data in 6 transistors and does not require a power supply periodically to maintain the stored contents when in use. The more complex construction of sram (6 transistors storing 1bit of data) results in faster access but higher cost, and therefore typically produces less capacity but more speed-demanding memories, such as: a256 KB or 512KB Cache Memory is built in a Central Processing Unit (CPU) of the personal computer. The speed of CPU determines how fast the computer can operate data and process information, and the capacity of main memory determines how much information the computer can store, so that the cache memory is used to store some frequently used information.
Disclosure of Invention
The invention provides a static random access memory unit array and a forming method thereof, which can promote the reliability of the manufacturing process and improve the performance of the static random access memory.
The invention provides a method for forming a Static Random Access Memory (SRAM) unit array, which comprises the following steps. First, a plurality of fin structures are formed on a substrate by patterning, wherein the fin structures comprise a plurality of active fin structures and a plurality of sacrificial fin structures, each pass transistor (PG FinFET) and a corresponding pull-down transistor (PD FinFET) share at least one active fin structure, and at least one sacrificial fin structure is arranged between two active fin structures spanned by two adjacent pull-up transistors (PU FinFETs) in a memory unit. At least a portion of the sacrificial fin structures are then removed.
The invention provides a Static Random Access Memory (SRAM) unit array, which comprises a plurality of fin-shaped structures positioned on a substrate. The fin structures include a plurality of active fin structures and a plurality of remaining sacrificial fin structures shorter than the active fin structures, wherein each pass transistor (PG FinFET) shares at least one active fin structure with a corresponding pull-down transistor (PD FinFET), and at least one remaining sacrificial fin structure is disposed between two active fin structures straddling two adjacent pull-up transistors (PU FinFETs) in a memory cell.
In view of the foregoing, the present invention provides a sram cell array and a method for forming the same, wherein a plurality of fin structures are formed on a substrate by patterning, wherein the fin structures may include a plurality of active fin structures and a plurality of sacrificial fin structures, and then at least a portion of the sacrificial fin structures are removed, such that the sacrificial fin structures are added to a desired active fin structure layout, such that the pitch between the fin structures is the same or nearly the same, such that the profile of the fin structures is similar. Therefore, the fin-shaped structures with similar shapes formed by the invention can promote the stability of the manufacturing process and the reliability of the device. Furthermore, the present invention provides at least one sacrificial fin structure between two active fin structures across which two adjacent boost transistors in a sram cell are disposed, such that the spacing between the two active fin structures (which typically have a larger pitch) may be similar to the spacing between other active fin structures (including the spacing between fin structures in other regions, such as logic regions).
Drawings
FIGS. 1-7 are schematic top view and cross-sectional views illustrating a method of forming an SRAM cell array according to an embodiment of the invention;
FIG. 8 is a top view and a cross-sectional view of a method of forming an SRAM cell array according to another embodiment of the invention.
Description of the main elements
10: hard mask layer
12: oxide layer
14: nitride layer
20. 30: mask and method for manufacturing the same
22. 32: organic dielectric layer
24. 34: silicon-containing hard mask bottom antireflective layer
26. 36: photoresist and method for producing the same
40: insulation structure
110: substrate
110': bulk substrate
112. 112a, 112b, 112c, 112 d: fin structure
112e, 112f, 112g, 112h1, 112h2, 112i1, 112i2, 112j1, 112j 2: active fin structure
112k, 112k ', 112l ', 112m ', 112n ', 112o ': sacrificial fin structure
112a ', 112 b', 112c ', 112 d': the remaining part
120: polysilicon grid
130: interconnect metal
140: contact plug
A: SRAM cell area
C1: cutting the first fin-shaped structure
C2: second fin shaped structure cutting
E: tail end of the tube
P, P1, P2, P3, P4: distance between each other
P1: etching process
PD1, PD 2: step-down transistor
PG1, PG 2: channel transistor
PU1, PU 2: boost transistor
U1: (1,1,1) type SRAM cell
U2: (1,2,2) type SRAM cell
w: width of
θ: angle of rotation
Detailed Description
Fig. 1-7 are schematic top and cross-sectional views illustrating a method of forming an sram cell array according to an embodiment of the invention. As shown in fig. 1-2, a plurality of fin structures 112 are patterned on a substrate 110. As shown in fig. 1, a bulk substrate 110 'is provided, a hard mask layer 10 is formed thereon and patterned to define the locations of the fin structures 112 to be correspondingly formed in the underlying bulk substrate 110'. In the present embodiment, the hard mask layer 10 may be a stacked structure of an oxide layer 12 and a nitride layer 14 from bottom to top, but the invention is not limited thereto. Next, as shown in fig. 2, an etching process P1 is performed to form fin structures 112 in the bulk substrate 110'. Thus, the fin structure 112 is completed on the substrate 110. In one embodiment, the hard mask layer 10 is removed after the fin structure 112 is formed, and a tri-gate field effect transistor (tri-gate MOSFET) is formed in a subsequent fabrication process. As such, fin structure 112 is referred to as a tri-gate field effect transistor (tri-gate MOSFET) because it has three direct contacts (including two contact sides and one contact top) with a subsequently formed dielectric layer. Compared with a planar field effect transistor, the tri-gate field effect transistor has a wider carrier channel width under the same gate length by using the three direct contact surfaces as a channel for carrier circulation, so that double drain driving current can be obtained under the same driving voltage. In another embodiment, the hard mask layer 10 may be remained, and another multi-gate MOSFET (Fin field effect transistor) Fin field effect transistor (Fin FET) having a Fin structure may be formed in a subsequent process. In the finfet, there are only two sides of contact between the fin structure 112 and the dielectric layer to be formed later, due to the remaining hard mask layer 10.
In addition, as mentioned above, the present invention can also be applied to other types of semiconductor substrates, for example, in another embodiment, a silicon-on-insulator substrate (not shown) is provided, and the single crystal silicon layer on the silicon-on-insulator substrate (not shown) is etched by an etching and photolithography method to stop at the oxide layer, thereby completing the fabrication of the fin structure on the silicon-on-insulator substrate. In addition, although the number of the fin structures 112 is 15 in the present embodiment for simplicity and clarity of disclosure, the number of the fin structures 112 that can be used in the present invention may be other numbers that can form an sram cell array.
As shown in fig. 3-6, the fin structures 112 are cut to form the desired layout of the sram cell array. The method of trimming the fin structure 112 and the layout of the sram cell array depend on the desired fabrication process requirements and device requirements. In the present embodiment, the method for cutting the fin structures 112 includes a first fin structure cutting C1 and a second fin structure cutting C2, wherein fig. 3 to 4 illustrate the first fin structure cutting C1 method of the present embodiment, and fig. 5 to 6 illustrate the second fin structure cutting C2 method of the present embodiment. The method of forming the fin structure 112 may include forming the fin structure by a Sidewall Image Transfer (SIT) technique, and the first fin structure trim C1 or/and the second fin structure trim C2 may be combined with a Sidewall Image Transfer (SIT) technique. That is, the first fin structure trim C1 and/or the second fin structure trim C2 may be steps in a Sidewall Image Transfer (SIT) technique, such that the first fin structure trim C1 and/or the second fin structure trim C2 may include a combination of cut-out to define and Transfer images to the substrate 110 to form sidewalls of the fin structures 112.
In detail, as shown in fig. 3, a mask 20 is sequentially covered and patterned to cover portions of the fin structures 112 that are not to be removed and expose portions of the fin structures 112 to be removed. In the present embodiment, the overlying mask 20 is an Organic Dielectric Layer (ODL) 22, a Silicon-containing hard mask Bottom anti-reflection layer (SHB) 24 and a photoresist 26 stacked from Bottom to top. The mask 20 completely exposes a fin structure 112a and a fin structure 112b at both ends, and exposes only the tail end E of the fin structure 112 between the fin structure 112a and the fin structure 112b, so that the problems of fin structure connection and line-end shortening (line-end shortening) in the Sidewall Image Transfer (SIT) technology can be solved. Next, a first fin trimming C1 is performed to completely remove the exposed fin structures 112a and 112b and the tail end E of the fin structure 112 between the fin structures 112a and 112b, as shown in fig. 4, the dashed line is the trimming range of the first fin trimming C1. After cutting, the remaining portions 112a '/112 b' of the fin structures 112a and 112b may remain, and the tail end E of the fin structure 112 between the fin structures 112a and 112b also remains (not shown), wherein the remaining portions 112a '/112 b' protrude from the substrate 110 between the fin structures 112. The first fin cut C1 may be a multi-directional cut, or only a first directional cut. In the present embodiment, the first fin structure cut C1 is cut in the y direction, and an x direction cut is selectively added to remove the fin structures 112a and 112b, but the invention is not limited thereto. In other embodiments, the first fin cut C1 may be cut only in the y-direction, leaving the fins 112a and 112 b. After the first fin cut C1 is performed, the photoresist 26, the silicon-containing hardmask bottom anti-reflective layer 24, and the organic dielectric layer 22 are removed.
Next, a second fin cut C2 is performed. As shown in fig. 5, a mask 30 is sequentially covered and patterned to cover portions of the fin structures 112 that are not to be removed and to expose portions of the fin structures 112 to be removed. In the present embodiment, the overlying Mask 30 is an Organic Dielectric Layer (ODL) 32, a silicon-containing Hard Mask bottom antireflective layer (SHB) 34 and a photoresist 36 stacked from bottom to top. The mask 30 completely exposes a fin structure 112c and a fin structure 112d at the edge. Next, a second fin trimming C2 is performed to remove the exposed fin structures 112C and 112d, and the dashed line portion is a trimming range of the second fin trimming C2 as shown in fig. 6. After cutting, the fin structures 112c and 112d may still have the remaining portions 112c '/112 d', wherein the remaining portions 112c '/112 d' also protrude from the substrate 110 between the fin structures 112. In the present embodiment, the second fin structure cut C2 is cut along a second direction, i.e. the x-direction, which is the second direction perpendicular to the second fin structure cut C2 in the first direction of the first fin structure cut C1, but the invention is not limited thereto. After the second fin cut C2 is performed, the photoresist 36, the silicon-containing hardmask bottom antireflective layer 34, and the organic dielectric layer 32 may be removed. In the present embodiment, the hard mask layer 10 is removed by spin-on.
Two embodiments are presented below to form two sram cell arrays, respectively. Fig. 7 shows a (1,1,1) sram cell array in which each pass transistor (PG FinFET) shares a single active fin structure with a corresponding pull-down transistor (PD FinFET). Fig. 8 shows another (1,2,2) sram cell array, in which each pass transistor (PG FinFET) shares two active fin structures with a corresponding pull-down transistor (PD FinFET). In addition, the invention can also be applied to other types of static random access memory cell arrays or other devices with fin structures.
Next, after the second fin trimming C2 step of fig. 6 is completed, a portion of the fin structure 112 is removed to form a fin structure layout for straddling the transistor group of the sram cell array, as shown in fig. 7. Further, as shown in fig. 6, the fin structure 112 may include a plurality of active fin structures 112e/112f/112g/112h/112i/112j and a plurality of sacrificial fin structures 112k '/112 l'/112 m '/112 n'/112 o ', and at least a portion of the sacrificial fin structures 112 k'/112 l '/112 m'/112 n '/112 o' are removed to obtain a desired fin structure layout and form the same shaped fin structure. In detail, in the present embodiment, after removing portions of the sacrificial fin structures 112k '/112 l '/112 m '/112 n '/112 o ', five sacrificial fin structures 112k/112l/112m/112n/112o are formed, wherein the sacrificial fin structures 112k/112l/112m/112n/112o protrude from the substrate 110 between the fin structures 112, as shown in the left diagram of fig. 7, but the invention is not limited thereto. Thus, the distribution of the active fins 112e/112f/112g/112h forms one of the (1,1,1) SRAM cells U1 shown in the right diagram of FIG. 7. Furthermore, the active fin structures 112i/112j are respectively located on two sides of the (1,1,1) sram cell U1, and the two active fin structures 112i/112j can be respectively used as active fin structures in other sram cells. Five sacrificial fin structures 112k/112l/112m/112n/112o are located between each active fin structure 112e/112f/112g/112h/112i/112j, respectively. In the present embodiment, sacrificial fin structures 112k/112l/112m/112n/112o are respectively disposed between active fin structures 112e/112f/112g/112h/112i/112j according to the pitch of active fin structures 112e/112f/112g/112h/112i/112j, so that the pitches of the fin structures 112 are the same as each other and as the pitches of the fin structures in other regions, but the invention is not limited thereto. For example, since the pitch of the active fin structures in the logic region is generally smaller than the pitch of the active fin structures in sram cell U1, the present invention adds sacrificial fin structures 112k/112l/112m/112n/112o between the active fin structures 112e/112f/112g/112h/112i/112j in sram cell U1 to make the pitch of the fin structures 112 in sram cell U1 equal to or similar to the pitch of the active fin structures in the logic region.
Therefore, the present invention adds at least one sacrificial fin structure between the active fin structures to make the fin structures in the same area or different areas have similar spacing, even the same spacing, and further make the formed fin structures have similar width, profile or shape, thereby improving the performance of manufacturing process stability and device reliability. Because, when the width of the fin structure is different, the performance of the formed sram is affected; when the shape of the fin-shaped structure is different, the stability of the manufacturing process is affected. Furthermore, a maximum pitch in each fin structure is less than twice a minimum pitch in each fin structure (otherwise, a sacrificial fin structure may be added between the maximum pitches). Furthermore, the illustration of the embodiment shows only SRAM cell area A, and SRAM cell U1 is located in SRAM cell area A, but substrate 110 may further include a logic area, the pitch of each fin structure 112 in sram cell region a is preferably less than twice the pitch of the fin structures in the logic region (otherwise, when the pitch of each fin structure 112 in sram cell region a is greater than or equal to twice the pitch of the fin structures in the logic region, at least one additional sacrificial fin structure may be added between the pitches of fin structures 112) so that the width, shape, and profile of fin structures 112 in sram cell region U1 are the same as, or approximately the same as, the width, shape, and profile of the fin structures in the logic region.
The (1,1,1) -type sram cell U1 includes a two-step-up transistor (PU FinFET) PU1, a two-channel transistor (PG FinFET) PG1, and a two-step-down transistor (PD FinFET) PD 1. In the (1,1,1) sram cell U1, each pass transistor PG1 shares a single active fin structure 112h/112g with a corresponding buck transistor PD1, and a single sacrificial fin structure 112k is disposed between two active fin structures 112e/112f spanned by two adjacent boost transistors PU 1. In a preferred embodiment, the pitch P between the fins 112 is equal. Similarly, each pass transistor PG1 has a sacrificial fin structure 112l/112m between the single active fin structure 112h/112g shared by the corresponding buck transistor PD1 and the active fin structure 112f/112e spanned by the two boost transistors PU1 closest to the single active fin structure 112h/112 g; sacrificial fin structures 112o/112n are disposed between the shared active fin structures in two adjacent memory cells, i.e., between active fin structures 112h/112j and between active fin structures 112g/112i, respectively.
It is emphasized that the pitch P between the fins 112 directly affects the width w and shape of the formed fins 112. Specifically, when the pitch P between the fin structures 112 is larger, the gradient of the cross-sectional profile of the formed fin structure 112 is larger, i.e., the angle θ is larger; as the pitch P between the fin structures 112 is smaller, the gradient of the cross-sectional profile of the formed fin structure 112 is steeper, i.e., the angle θ is smaller. Therefore, when the pitch P between the fin structures 112 is different, the width and the profile gradient of each fin structure 112 are different. When the width and cross-sectional profile of each fin structure 112 are not uniform, the performance, such as the stability of the fabrication process and the reliability of the formed device, may be degraded. In the present embodiment, the sacrificial fin structures 112k/112l/112m/112n/112o are added between the active fin structures 112e/112f/112g/112h/112i/112j to adjust the pitch P between the fin structures 112, so that the pitch P of each fin structure 112 is as same as the pitch of the fin structures in other regions (e.g., logic regions) as possible. In the present embodiment, only a single sacrificial fin structure 112k/112l/112m/112n/112o is added between the active fin structures 112e/112f/112g/112h/112i/112j, but the invention is not limited thereto. The present invention may also selectively supplement the sacrificial fin structures 112k/112l/112m/112n/112o between the active fin structures 112e/112f/112g/112h/112i/112j, or supplement two or more sacrificial fin structures 112k/112l/112m/112n/112o between two adjacent active fin structures 112e/112f/112g/112h/112i/112j, depending on the pitch P between the fin structures 112 and the pitch between the fin structures in other regions.
Further, the (1,1,1) sram cell U1 may further include a cross fin 112 with a polysilicon gate 120, interconnect metal 130 connecting the transistors including pass transistor PG1, buck transistor PD1, and boost transistor PU1, and contact plug 140 physically connecting the polysilicon gate 120 and interconnect metal 130. The structure and operation of the (1,1,1) type sram cell U1 are well known in the art and therefore will not be described in detail.
In addition, the present invention is also applicable to a (1,2,2) type SRAM cell array, as shown in FIG. 8. The difference between SRAM cell U2 of type (1,2,2) and SRAM cell U1 of type (1,1,1) is that: the active fin structure 112h in the (1,1,1) sram cell U1 is replaced by two active fin structures 112h1/112h2, and a pass transistor (PG FinFET) PG2 and a corresponding pull-down transistor (PD FinFET) PD2 in the (1,2,2) sram cell U2 share the two active fin structures 112h1/112h 2; the active fin structure 112g of the (1,1,1) sram cell U1 is replaced by two active fin structures 112g1/112g2, and the other pass transistor (PG FinFET) PG2 of the (1,2,2) sram cell U2 shares the two active fin structures 112g1/112g2 with the corresponding one pull-down transistor (PD FinFET) PD 2. The active fin structure 112i on the side of the (1,1,1) sram cell U1 is replaced by two active fin structures 112i1/112i2, and the active fin structure 112j on the side of the (1,1,1) sram cell U1 is replaced by two active fin structures 112j1/112j 2. A single sacrificial fin 112k is still disposed between two active fins 112e/112f spanned by two adjacent boost transistors PU 2.
Since the pitch P1 between the two active fin structures 112h1/112h2, the pitch P2 between the two active fin structures 112i1/112i2, and the pitch P3 between the two active fin structures 112j1/112j2 are smaller than the pitch P4 between the other fin structures 112, the sacrificial fin structures 112k/112l/112m/112n/112o are disposed between the other fin structures 112 except that no sacrificial fin structure is disposed between the two active fin structures 112h1/112h2, between the two active fin structures 112i1/112i2, and between the two active fin structures 112j1/112j 2. Therefore, the pitch between the fin structures 112 can be adjusted in the present embodiment, so that the pitch of the fin structures 112 is as same as possible. In this way, the fin structures 112 formed have the same width and shape, thereby improving the reliability of the manufacturing process and further improving the performance of the sram.
In addition, after forming the active fin structures 112e/112f/112g (112g1/112g2)/112h (112h1/112h2)/112i (112i1/112i2)/112j (112j1/112j2) and the sacrificial fin structures 112k/112l/112m/112n/112o, an insulating structure 40 may be formed between the active fin structures 112e/112f/112g (112g1/112g2)/112h (112h1/112h2)/112i (112i1/112i2)/112j (112j1/112j2), wherein the active fin structures 112e/112f/112g (112g1/112g2)/112h (112h1/112h 2)/1/112 i2)/112j 1/2) protrude from the insulating structure 40, but insulating structure 40 covers all of sacrificial fin structures 112k/112l/112m/112n/112 o.
In summary, the present invention provides a sram cell array and a method for forming the same, wherein a plurality of fin structures are formed on a substrate by patterning, wherein the fin structures may include a plurality of active fin structures and a plurality of sacrificial fin structures, and then at least a portion of the sacrificial fin structures are removed, such that the sacrificial fin structures are added to a desired active fin structure layout, such that the pitch between the fin structures is the same or nearly the same, such that the width and shape of the fin structures are the same. The fin-shaped structures with the same width and shape formed by the invention can promote the stability of the manufacturing process and the reliability of the device.
In detail, each sram in the sram cell array formed in the present invention includes two step-up transistors, two channel transistors, and two step-down transistors. Each pass transistor (PG FinFET) and a corresponding buck transistor (PD FinFET) share at least one active fin structure, for example, the present invention can form a (1,1,1) type sram cell array in which each pass transistor and a corresponding buck transistor share only a single active fin structure, or the present invention can form a (1,2,2) type sram cell array in which each pass transistor and a corresponding buck transistor share only two active fin structures. It is emphasized that the present invention provides at least one sacrificial fin structure between two active fin structures across which two adjacent boost transistors in a sram cell straddle, such that the spacing between the two active fin structures (which typically have a larger pitch) may be similar to the spacing between other active fin structures in the sram cell, or the spacing between fin structures in other regions (e.g., logic regions). With the method of the present invention, a maximum pitch in each fin structure is less than twice a minimum pitch in each fin structure (otherwise, a sacrificial fin structure may be added between the maximum pitches).
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.
Claims (18)
1. A method of forming a Static Random Access Memory (SRAM) cell array, comprising:
patterning to form a plurality of fin structures on a substrate, wherein the fin structures comprise a plurality of active fin structures and a plurality of sacrificial fin structures, each channel fin transistor (PG FinFET) shares at least one active fin structure with a corresponding buck fin transistor (PD FinFET), each of two adjacent boost fin transistors (PU FinFETs) in a memory cell straddles one of the active fin structures, and at least one sacrificial fin structure is arranged between two active fin structures straddled by the two boost fin transistors; and
removing at least a portion of the sacrificial fin structures,
wherein at least one remaining sacrificial fin structure is disposed between the two active fin structures across which the two adjacent boosted fin transistors (PU FinFETs) in the memory cell after removing at least a portion of the sacrificial fin structures,
the substrate comprises a static random access memory unit area and a logic area, wherein the static random access memory units are positioned in the static random access memory unit area, and the pitch of the fin-shaped structures in the static random access memory unit area is smaller than twice of the pitch of the fin-shaped structures in the logic area.
2. The method of claim 1, wherein each SRAM comprises two boosting fintransistors, two channel fintransistors and two buck fintransistors.
3. The method of forming an array of static random access memory cells of claim 1, further comprising:
at least one of the sacrificial fin structures is disposed between the shared active fin structure and the two active fin structures across which one of the two boosting fin transistors (PU finfets) is closest to the shared active fin structure.
4. The method of forming an array of static random access memory cells of claim 1, further comprising:
at least one of the sacrificial fin structures is disposed between the active fin structures shared in two adjacent memory cells.
5. The method of forming an array of static random access memory cells of claim 1, further comprising:
the fin structures are trimmed prior to removing at least a portion of the sacrificial fin structures.
6. The method of claim 5, wherein the cutting the fin structures comprises a first fin structure cut and a second fin structure cut, wherein the first fin structure cut is cut in a first direction and the second fin structure cut is cut in a second direction.
7. The method of claim 6, wherein said first direction cut is perpendicular to said second direction cut.
8. The method of claim 7, wherein the first fin trimming comprises trimming tail ends of the fin structures, and the second fin trimming comprises removing edge-located ones of the fin structures.
9. The method of claim 1, wherein a maximum pitch of the fin structures is less than twice a minimum pitch of the fin structures.
10. An array of Static Random Access Memory (SRAM) cells, comprising:
a plurality of fin structures on a substrate, the fin structures including a plurality of active fin structures and a plurality of remaining sacrificial fin structures shorter than the plurality of active fin structures, wherein each channel fin transistor (PG FinFET) shares at least one active fin structure with a corresponding buck fin transistor (PD FinFET), each of two adjacent boost fin transistors (PU FinFETs) in a memory cell straddles one of the plurality of active fin structures, at least one of the remaining sacrificial fin structures is disposed between two of the active fin structures straddled by the two boost fin transistors,
the substrate comprises a static random access memory unit area and a logic area, wherein the static random access memory units are positioned in the static random access memory unit area, and the pitch of the fin structures in the static random access memory unit area is smaller than twice of the pitch of the fin structures in the logic area.
11. The sram cell array of claim 10, wherein each sram cell comprises two boost fin-transistors, two-channel fin-transistors, and two buck fin-transistors.
12. The sram cell array of claim 10, further comprising:
at least one of the remaining sacrificial fin structures is disposed between the shared active fin structure and the two active fin structures across which one of the two boosting fin transistors (PU finfets) is closest to the shared active fin structure.
13. The sram cell array of claim 10, further comprising:
at least one of the remaining sacrificial fin structures is disposed between the active fin structures shared in two adjacent memory cells.
14. The sram cell array of claim 10, further comprising:
a plurality of insulating structures is between the active fin structures and covers all of the remaining sacrificial fin structures.
15. The array of claim 10, wherein a maximum pitch of the fin structures is less than twice a minimum pitch of the fin structures.
16. The sram cell array of claim 10, wherein a profile of the fin structures in the sram cell region is the same as a profile of the fin structures in the logic region.
17. The sram cell array of claim 10, wherein each of the pass fin transistors (PG finfets) and the corresponding buck fin transistor (PD finfets) share only one of the active fin structures.
18. The sram cell array of claim 10, wherein each of the pass fin transistors (PG finfets) and the corresponding buck fin transistor (PD finfets) share only two of the active fin structures.
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| CN202010781720.1A CN111785721B (en) | 2017-06-27 | 2017-10-17 | SRAM cell array |
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| US15/635,165 US9953988B2 (en) | 2016-04-27 | 2017-06-27 | Method of forming static random-access memory (SRAM) cell array |
| US15/691,764 | 2017-08-31 | ||
| US15/691,764 US10050046B2 (en) | 2016-04-27 | 2017-08-31 | Static random-access memory (SRAM) cell array and forming method thereof |
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| CN111785721A (en) | 2020-10-16 |
| CN109148451A (en) | 2019-01-04 |
| CN111785721B (en) | 2023-06-06 |
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