CN109145333A

CN109145333A - A kind of device detection structure automation placement-and-routing method

Info

Publication number: CN109145333A
Application number: CN201710500677.5A
Authority: CN
Inventors: 陆宇
Original assignee: Shanghai Zhuo Micro System Technology Co Ltd
Current assignee: Shanghai Zhuo Micro System Technology Co Ltd
Priority date: 2017-06-27
Filing date: 2017-06-27
Publication date: 2019-01-04

Abstract

The present invention provides a kind of automation placement-and-routing methods of multiple transistor modular unit testing structures, wherein the transistor modular unit of the introducing parameter, forms test structure by several transistors.Tested transistor is intelligently connected with corresponding liner and completes placement-and-routing by the automatic method.The automatic method reduces the implementation complexity of transistor testing circuit and test structure under new process on a large scale, shortens the deadline, and improve reliability.

Description

A kind of device detection structure automation placement-and-routing method

Technical field

The present invention relates to analogue layout rear ends, especially with respect to the automatic placement and routing of device detection structure.

Background technique

IC design includes Front-end Design and two stages are designed in rear end, and Front-end Design is responsible for logic realization, usually It is the speech like sound using Verilog/VHDL, carries out the description of behavioral scaling.Rear end design refers to the gate leve for generating Front-end Design Netlist is laid out wiring by EDA design tool and carries out physical verification and finally generate the mistake of the GDS file for manufacture Journey, main responsibility have: chip makes physical structural analysis, logic analysis, establish rear end design cycle, laying out pattern wiring, Layout editing, gets in touch with fab and submits creation data domain physical verification.So-called GDS file is a kind of patterned text Part is a kind of format of integrated circuit diagram.

With the increase increasingly of mixed-signal designs complexity, development technology design tool packet (PDK, Process Design Kit) and to establish verifying reference flowchart be extremely important for reducing the market risk brought by expensive design repeatedly 's.In general, fab can customize the design component of PDK according to the requirement of technology, and each technique can have a set of right The PDK answered.

PDK is the complete process file set that provides for analog/mixed signal IC circuit design, be connection IC design and The data platform of IC technique manufacture.The content of PDK includes: device model (Device Model)；Symbol and view (Symbols & View)；Component descriptor format (CDF, Component Description Format) and Callback function；Parametrization is single First (Pcell, Parameterized Cell)；Technological document (Technology File)；Physical verification rule (PV Rule) File etc..

What wherein the parameter in parameterized units (Pcell) referred to is exactly CDF parameter, and it is fixed that their combination can be realized user The institute of system is functional, is the core of PDK.In fact, the library of PDK just refers to the intersection of all parameterized units.

In short, if having the PDK, IC of the optimization sets such as parameterized units structure, symbol and the rule by verifying The work of designer can free from the task of cumbersome fallibility and become high quality and rich in efficiency.

In traditional territory unit library, MOS transistor basic unit is only existed, layout drawing personnel are drawing matching MOS When transistor, the MOS transistor with parameter is first called, then further according to the MOS transistor dimensional parameters of required measurement, to each The territory unit of MOS transistor carries out parameter setting, is laid out wiring then according to matched principle.Whole process is from addition They are carried out parameter setting by MOS transistor, and the location layout in domain is connected to liner to wiring, links are all by drawing Personnel processed have been manually done.If MOS transistor quantity is very huge or size is varied, change operation it is very cumbersome, and It is also easy in careless middle generation mistake.

Summary of the invention

The present invention provides a kind of automation placement-and-routing methods of multiple transistor modular unit testing structures, to call in The data of required measurement transistor simultaneously generate domain, reduce the area of domain, improve the efficiency for drawing test structure domain, improve The stability of structure.

According to an embodiment of the invention, providing a kind of automation placement-and-routing of multiple transistor modular unit testing structures Method includes: several tested transistors and liner and the metal connecting line between them.

Optionally, the quantity of the transistor modular unit, automatically generates MOS transistor and by longitudinal arrangement.

Optionally, the grid length, grid width of the transistor modular unit and interdigital number allow area according to practical domain, press Left-justify arrangement in interval appropriate.

Optionally, the layout method of the test structure: liner longitudinal arrangement, its spacing on the left of domain meet technique most Small size or tested MOS transistor width.

Optionally, the layout method of the test structure: for liner at arrangement symmetrical above and below, centre is corresponding grid and substrate Liner, the liner of arrangement corresponding source and leakage symmetrical above and below.

Optionally, the wiring method of the test structure: regardless of tested MOS transistor parameter, the grid of various pieces, Source, leakage, which all merge, draws, and externally apparently only there are four outputs for a MOS transistor.

Optionally, the wiring method of the test structure: the liner in a tested MOS transistor corresponding one group of source and leakage, Institute's active area of the transistor is uniformly connected to the liner of the source corresponding to it, and all drain regions are uniformly connected to the lining of the leakage corresponding to it Pad.The liner of all tested MOS transistor corresponding one group of grid and substrate, the grid of all transistors are uniformly connected to unique grid lining Pad, and all substrates are uniformly connected to unique substrate pads.Therefore N number of transistor corresponds to N number of source liner, N number of leakage liner, 1 grid Liner and 1 substrate pads.

Detailed description of the invention

Fig. 1 is to generate MOS transistor parameterized module cellular construction schematic diagram by parameter；

Fig. 2 is to arrange layout structure schematic diagram symmetrical above and below after liner；

Fig. 3 is that the automation placement-and-routing of multiple transistor modular unit testing structures completes schematic diagram.

Specific embodiment

The present invention is further illustrated below in conjunction with attached drawing table and specific embodiment, the present embodiment is only used for illustrating substantially former Reason, is not intended to limit the present invention, the scope of the present invention should be defined by the scope defined by the claims..Read below with After attached drawing table is detailed description of the illustrated embodiment, the present invention will be evident for person of ordinary skill in the field.

As shown in table 1, the embodiment of the present invention contains 4 tested MOS transistors.

Metal-oxide-semiconductor quantity	Grid width W	Grid length L	Interdigital several Finger
				1	W1	L1	1
2	W1	L2	1
				3	W3	L1	1
4	W1	L1	2

Table 1 is tested MOS transistor number parameter table

Become parameterized module unit after the parameter of 4 tested MOS transistors is imported and generate domain, as shown in Figure 1, No. 1 MOS Pipe 101 is standard parameter W1, L1 and 1 interdigital number (Finger)；The grid width of No. 2 metal-oxide-semiconductors 102 and interdigital number are standard parameter W1,1, and the more a length of L2 of grid length；The grid length of No. 3 metal-oxide-semiconductors 103 and interdigital number are standard parameter L1,1, and grid width relatively width is W3；4 The grid width and grid length of number metal-oxide-semiconductor 104 are standard parameter W1, L1, and interdigital number is relatively mostly 2.So according to the present invention described in right Requirement 4 MOS transistor longitudinal direction left-justifys are arranged when generating domain, and since its upper and lower symmetrical structure is by 101, 102 points are placed on domain top half for one group, and 103,104 points are one group and are placed on domain lower half portion, and centre leaves a blank later to The grid and substrate pads to be laid out leave position.

It is indefinite that MOS transistor quantity is tested in practical application, may be far more than 4, and the parameter of each pipe is also not It is identical to the greatest extent.But the principle that parameterized module unit generates domain is constant: MOS transistor longitudinal direction left-justify arrangement, by the one of quantity Partly it is respectively placed in that domain or more is half side, and centre is left a blank.

Fig. 2 show the layout structure after addition liner (PAD), and the liner of requirement described in right is in domain according to the present invention Left side longitudinally arrangement symmetrical above and below, symmetrical centre are that liner 205 corresponding to common gate (G) and common substrate (Sub) are corresponding Liner 206.Under normal circumstances, the spacing between substrate meets technique minimum dimension, such as liner 201,202 and liner 207, Spacing between 208.And when padding corresponding MOS transistor grid length larger 102 or having multi-fork index 104, it can accordingly put The distance between wide liner has met placement-and-routing's demand, such as the spacing between liner 203,204 and liner 209,210.

It is indefinite that liner quantity is tested in practical application, it may be far more than 10.

(formula 1):

Pad quantity=tested MOS transistor quantity * 2+2

And the spacing between each liner is also to be not quite similar.But the principle for padding layout is constant: liner is located at vertical on the left of domain To arrangement, by intermediate G, the corresponding liner layout symmetrical above and below of Sub.

Fig. 3 show the MOS transistor test domain structure after the complete line of cloth, brilliant for the tested MOS other than multi-fork index Body pipe 104, source and leakage are attached directly to the corresponding liner in left side by metal wire 301,302, and grid and substrate are by global grid bus 303 and substrate bus 304 be uniformly connected in unique grid liner and substrate pads, save chip area in this way, while Facilitate cable management.And for the MOS transistor of multi-fork index 104, plural grid, source and leakage first will by metal 305, 306,307 connect, and form an entirety, and externally apparently a transistor only has four for requirement described in right according to the present invention A output, then wire laying mode is attached as other standards transistor.

The metal-oxide-semiconductor of the automation placement-and-routing of multiple transistor modular unit testing structures through the invention, new process is surveyed Amount domain is only needed to input parameter list as shown in Table 1 and can be automatically generated, and reduces the area of domain, is improved and is drawn test structure The efficiency of domain improves the stability of structure, reduces human cost, shortens test period.

The invention patent is not only limited to above-mentioned specific embodiment, and those of ordinary skill in the art are public according to the present invention The content opened can implement the present invention using other a variety of specific embodiments.Therefore, all using design structure of the invention And thinking, the design of some simple variations or change is done, protection scope of the present invention is both fallen within.

Claims

1. a kind of parameterized module unit of transistors is made of several transistors, which is characterized in that the modular unit provides The parameter for controlling transistor number, modifies the parameter, the number of adjustable transistor, and inside will make corresponding tune automatically It is whole, transistor is arranged by longitudinal direction.

2. modular unit as described in claim 1, which is characterized in that modular unit offer control transistor grid length (L), The parameter of grid width (W) and interdigital number (Finger) modifies the parameter, and the size of adjustable transistor, inside will be automatic Corresponding adjustment is made, matching connection relationship is still maintained, and left-justify mode arranges between each transistor, when grid length is larger Spacing between liner can change therewith.

3. modular unit as described in claim 1, which is characterized in that each transistor draws n item gold in the modular unit Belong to line, is connect for modular unit with external circuit；Wherein metal wire includes that substrate draws metal wire (1)；Grid draw metal wire (the interdigital number that quantity is the transistor)；Draw metal wire (the interdigital number that quantity is the transistor) in source；Metal wire (number is drawn in leakage Amount is that the interdigital number of the transistor subtracts one).

4. a kind of layout method for testing structure, which is characterized in that all transistors in modular unit as described in claim 1 It is that grid are laterally disposed, source and leakage branch on it under；Longitudinal arrangement between transistor, and be aligned by the leftmost side of grid, make For the basic disposing way for testing structure.

5. test structure layout method as claimed in claim 4, which is characterized in that the version of liner put using longitudinal column Graph structure, the spacing in surveyed transistor grid length and smaller interdigital number between liner meet technique minimum spacing；Surveying crystalline substance Liner spacing can suitably amplify when body pipe grid length and larger interdigital number or when other layouts need.

6. test structure layout method as claimed in claim 4, which is characterized in that liner is put using version symmetrical above and below Graph structure, symmetrical centre are the liners that a liner drawn as grid is drawn with one as substrate；In structure symmetrical above and below Liner respectively as source and leakage extraction.

7. a kind of wiring method for testing structure, which is characterized in that each transistor in layout method as claimed in claim 4 Source, leakage, grid and substrate are unified is connected by metal；For more interdigital structures, all sources are connected together, and all misses one It rises, all grid are also connected together, and externally apparently only there are four outputs for a transistor.

8. test structural wiring method as claimed in claim 7, which is characterized in that the corresponding one group of source of a transistor and leakage Liner, institute's active area of the transistor is uniformly connected to the liner of the source corresponding to it, and all drain regions are uniformly connected to corresponding to it Leakage liner.

9. test structural wiring method as claimed in claim 7, which is characterized in that the corresponding one group of grid of all transistors and substrate Liner, the grid of all transistors are uniformly connected to the liner of the grid corresponding to it, and all substrates are uniformly connected to the lining corresponding to it Subgaskets.