CN109119421A - The process of 1.5T SONOS flash memory - Google Patents
The process of 1.5T SONOS flash memory Download PDFInfo
- Publication number
- CN109119421A CN109119421A CN201810757746.5A CN201810757746A CN109119421A CN 109119421 A CN109119421 A CN 109119421A CN 201810757746 A CN201810757746 A CN 201810757746A CN 109119421 A CN109119421 A CN 109119421A
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- CN
- China
- Prior art keywords
- layer
- polysilicon
- selecting pipe
- polysilicon gate
- gate
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 90
- 229920005591 polysilicon Polymers 0.000 claims abstract description 90
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 21
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- 238000002347 injection Methods 0.000 claims abstract description 14
- 239000007924 injection Substances 0.000 claims abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 125000001475 halogen functional group Chemical group 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 abstract description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention discloses a kind of processes of 1.5T SONOS flash memory: the first step, forms selecting pipe gate oxide on a silicon substrate；Second step, the etching removal remaining gate oxide of substrate surface, re-forms ONO layer；The ONO layer of etching removal logic area, thermal oxide form gate oxide in logic area；It is defined again by photoresist, the source region injection of selecting pipe is carried out between the polysilicon gate of selecting pipe, then etch the ONO layer between removal selecting pipe polysilicon gate；Third step deposits the second polysilicon layer；4th step etches the second polysilicon layer, forms the polysilicon of the source region of the polysilicon gate of logic area, the polysilicon gate of storage tube and connection selecting pipe；5th step, deposit silicon nitride layer simultaneously etch；Carry out the source and drain injection of selecting pipe and logic area transistor.The present invention is directly led out the source region for connecting selecting pipe using polysilicon, and the distance between selecting pipe is limited only in the precision of photoetching, and there is no photoetching to cover inclined problem, reduces the area of single storage unit, improves integrated level.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly relate to a kind of process of 1.5T SONOS flash memory.
Background technique
SONOS (Semiconductor-Oxide- with low operating voltage, better COMS processing compatibility
Nitride-Oxide-Semiconductor) technology is widely used in various embedded electronic products such as financial IC card, automobile electricity
The application such as son.2-T SONOS (2 transistors) technology has obtained the favor of many applications due to its low-power consumption.But 2-T
The inherent disadvantage of structure is exactly its biggish chip area loss.
Relative to 2-T SONOS, the SONOS device of grid 1.5-T is divided more to save area.As shown in Figure 1, existing 1.5-T
SONOS has a contact hole 15 to draw the source of selecting pipe between two selecting pipes, partially in order to avoid photoetching set, two selections
The distance between pipe cannot be too small, therefore traditional method is unfavorable for further decreasing the area of single storage unit.
Summary of the invention
Technical problem to be solved by the present invention lies in a kind of process of 1.5T SONOS flash memory is provided, choosing can be reduced
The distance between pipe is selected, chip area is further reduced.
To solve the above problems, the process of 1.5T SONOS flash memory of the present invention, walks comprising following technique
It is rapid:
The first step, on a silicon substrate formed selecting pipe gate oxide, then successively deposit the first polysilicon layer, silicon oxide layer,
Silicon nitride layer；It is defined by photoresist, successively downward etch nitride silicon layer, silicon oxide layer and the first polysilicon layer, to form choosing
The polysilicon gate of pipe is selected, and the polysilicon gate side of selecting pipe is aoxidized, forms lateral oxidation layer；
Second step, the etching removal remaining gate oxide of substrate surface, re-forms ONO layer；The ONO of etching removal logic area
For layer to expose surface of silicon, thermal oxide forms gate oxide in logic area；It is defined again by photoresist, in the polycrystalline of selecting pipe
The source region injection of selecting pipe is carried out between Si-gate, then etches the ONO layer between removal selecting pipe polysilicon gate, by selecting pipe polycrystalline
Surface of silicon between Si-gate is exposed；
Third step deposits the second polysilicon layer, covers entire substrate；
4th step etches the second polysilicon layer, forms the polysilicon gate of logic area, the polysilicon gate of storage tube and connection
The polysilicon of the source region of selecting pipe；The silicon oxide layer that oxidation processes form surface is carried out to the surface of the second polysilicon layer again；Into
Row LDD and halo injection；
5th step, deposit silicon nitride layer simultaneously etch；Carry out the source and drain injection of selecting pipe and logic area transistor.
Further, in the first step, silicon oxide layer and silicon nitride layer are also remained on the polysilicon gate of selecting pipe.
It further, is using selection when etching removes the ONO layer between selecting pipe polysilicon gate in the second step
The same photoresist of the source region injection of selecting pipe is carried out between the polysilicon gate of pipe；Remaining ONO layer is covered on selecting pipe polycrystalline
Silica on Si-gate and grid, the side of silicon nitride and storage tube region substrate surface.
Further, in the third step, the second polysilicon layer of deposit directly connects between the polysilicon gate of selecting pipe
Touch surface of silicon.
Further, in the 4th step, by the second polysilicon directly by the polysilicon gate of selecting pipe after the completion of etching
Between region, i.e. the source region of selecting pipe directly leads out.
Further, in the 5th step, the silicon nitride layer of deposit covers entire substrate surface, after etching, remaining nitrogen
SiClx layer is covered on the silicon nitride layer side on the second polysilicon layer side and above the polysilicon gate of selecting pipe.
The process of 1.5T SONOS flash memory of the present invention, will using the source region that polysilicon is directly connected to selecting pipe
It is drawn, and the distance between selecting pipe is limited only in the precision of photoetching, and there is no photoetching to cover inclined problem, can reduce between selecting pipe
Distance, reduce the area of single storage unit, improve integrated level.
Detailed description of the invention
Fig. 1 is the sectional structure chart of existing 1.5T SONOS flash memory.
Fig. 2~6 are the processing step schematic diagrames of 1.5T SONOS flash memory of the present invention.
Fig. 7 is the flow chart of the process of 1.5T SONOS flash memory of the present invention.
Description of symbols
1 is substrate, and 2 be selecting pipe gate oxide, and 3 be the first polysilicon layer (selecting pipe polysilicon gate), and 4 be silica
Layer, 5 be silicon nitride layer, and 6 be ONO layer, and 7 be logic area gate oxide, and 8 be selecting pipe source region, and 9 be the (storage of the second polysilicon layer
Pipe polysilicon gate), 9-1 is the second polysilicon layer (logic area transistor polysilicon gate), and 9-2 is the second polysilicon layer (selecting pipe
Source region is drawn), 10 be silicon oxide layer, and 11 be LDD and Halo injection, and 12 be silicon nitride, and 13 be source and drain injection, and 14 be photoresist,
15 be contact hole.
Specific embodiment
The process of 1.5T SONOS flash memory of the present invention, includes following processing step:
The first step forms selecting pipe gate oxide 2 on the silicon substrate 1 of p-type, then successively deposits the first polysilicon layer 3, oxygen
SiClx layer 4, silicon nitride layer 5；It is defined by photoresist, successively downward etch nitride silicon layer, silicon oxide layer and the first polysilicon layer,
To form the polysilicon gate of selecting pipe, silicon oxide layer and silicon nitride layer are also remained on the polysilicon gate of selecting pipe.Again to selection
The polysilicon gate side of pipe is aoxidized, and lateral oxidation layer is formed.As shown in Figure 2.
Second step, the etching removal remaining gate oxide of substrate surface, re-forms ONO layer 6；Etching removal logic area
ONO layer one exposes surface of silicon, and thermal oxide forms gate oxide in logic area；It is defined again by photoresist, in selecting pipe
The source region 8 that selecting pipe is carried out between polysilicon gate is injected；Same photoresist is reused, etching removes between selecting pipe polysilicon gate
ONO layer, the surface of silicon between selecting pipe polysilicon gate is exposed.Remaining ONO layer is covered on selecting pipe polysilicon
Silica on grid and grid, the side of silicon nitride and storage tube area under control domain substrate surface.As shown in Figure 3.
Third step deposits the second polysilicon layer 9, covers entire substrate.Second polysilicon layer is between two selecting pipes
Region is connected directly between in substrate silicon.Polysilicon gate of the photoresist developing in logic area definition logic area.That is the polysilicon of logic area
Polysilicon, the storage tube polysilicon gate that selecting pipe source region is connected between grid, selecting pipe are to share the second polysilicon layer.Such as Fig. 4 institute
Show.
4th step etches the second polysilicon layer, forms the polysilicon gate of logic area, the polysilicon gate of storage tube and connection
The polysilicon of the source region of selecting pipe；The silicon oxide layer that oxidation processes form surface is carried out to the surface of the second polysilicon layer again；Into
Row LDD and halo injection；Oxidation forms oxide layer on the second polysilicon layer surface, carries out LDD and Halo and injects to form 11.Pass through
Polysilicon draws the source region of selecting pipe, avoids in traditional handicraft, the source region between selecting pipe polysilicon gate need to pass through contact
Hole connects extraction with metal, therefore reduces the area of single storage unit.The distance between selecting pipe is only limited in this method
In the precision of photoetching, there is no photoetching to cover inclined problem, therefore can reduce the distance between selecting pipe.As shown in Figure 5.
5th step, deposit silicon nitride layer 12 simultaneously etch, and the silicon nitride layer at the top of polysilicon gate is removed, only remaining side
Retain silicon nitride layer；Carry out the source and drain injection of selecting pipe and logic area transistor.As shown in Figure 5.Subsequent technique and traditional work
Skill is consistent, repeats no more.
The present invention sequentially forms storage tube ONO layer, logic area gate oxide after forming selection tube grid.Photoresist is aobvious
Shadow, region between two selecting pipes carry out the injection of selecting pipe source region, using same photoresist etch removal selecting pipe it
Between ONO layer on substrate, the substrate silicon at the selecting pipe source of heavy doping is exposed.Deposit the second polysilicon layer, light
Photoresist is developed in after logic area defines logic polysilicon gate, etches the second polysilicon layer.It is more that etching has been formed simultaneously logic area
Crystal silicon grid, storage tube polysilicon gate and the polysilicon for connecting selecting pipe source.Selecting pipe source is connected using the second polysilicon layer
It is drawn in area.The distance between selecting pipe can be reduced, reduce the area of single storage unit, improve integrated level.
The above is only a preferred embodiment of the present invention, is not intended to limit the present invention.Come for those skilled in the art
It says, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any modification, equivalent
Replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (6)
1. a kind of process of 1.5T SONOS flash memory, it is characterised in that: include following processing step:
The first step forms selecting pipe gate oxide on a silicon substrate, then successively deposits the first polysilicon layer, silicon oxide layer, nitridation
Silicon layer；It is defined by photoresist, successively downward etch nitride silicon layer, silicon oxide layer and the first polysilicon layer, to form selecting pipe
Polysilicon gate, and the polysilicon gate side of selecting pipe is aoxidized, forms lateral oxidation layer；
Second step, the etching removal remaining gate oxide of substrate surface, re-forms ONO layer；Etching removal logic area ONO layer with
Expose surface of silicon, thermal oxide forms gate oxide in logic area；It is defined again by photoresist, in the polysilicon gate of selecting pipe
Between carry out selecting pipe source region injection, then etch removal selecting pipe polysilicon gate between ONO layer, by selecting pipe polysilicon gate
Between surface of silicon expose；
Third step deposits the second polysilicon layer, covers entire substrate；
4th step etches the second polysilicon layer, forms the polysilicon gate of logic area, the polysilicon gate of storage tube and connection selection
The polysilicon of the source region of pipe；The silicon oxide layer that oxidation processes form surface is carried out to the surface of the second polysilicon layer again；Carry out LDD
And halo injection；
5th step, deposit silicon nitride layer simultaneously etch；Carry out the source and drain injection of selecting pipe and logic area transistor.
2. the process of 1.5T SONOS flash memory as described in claim 1, it is characterised in that: in the first step, selection
Silicon oxide layer and silicon nitride layer are also remained on the polysilicon gate of pipe.
3. the process of 1.5T SONOS flash memory as described in claim 1, it is characterised in that: in the second step, carving
Etching off is the source region note that selecting pipe is carried out between the polysilicon gate using selecting pipe when removing the ONO layer between selecting pipe polysilicon gate
The same photoresist entered；Remaining ONO layer is covered on the side of silica, silicon nitride on selecting pipe polysilicon gate and grid, and
The substrate surface in storage tube region.
4. the process of 1.5T SONOS flash memory as described in claim 1, it is characterised in that: in the third step, deposit
The second polysilicon layer directly contact surface of silicon between the polysilicon gate of selecting pipe.
5. the process of 1.5T SONOS flash memory as described in claim 1, it is characterised in that: in the 4th step, etching
After the completion by the second polysilicon directly by the region between the polysilicon gate of selecting pipe, i.e. the source region of selecting pipe is directly led out.
6. the process of 1.5T SONOS flash memory as described in claim 1, it is characterised in that: in the 5th step, deposit
Silicon nitride layer cover entire substrate surface, after etching, remaining silicon nitride layer is covered on the second polysilicon layer side, and
On silicon nitride layer side above the polysilicon gate of selecting pipe.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810757746.5A CN109119421A (en) | 2018-07-11 | 2018-07-11 | The process of 1.5T SONOS flash memory |
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| CN201810757746.5A CN109119421A (en) | 2018-07-11 | 2018-07-11 | The process of 1.5T SONOS flash memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110504273A (en) * | 2019-08-13 | 2019-11-26 | 上海华虹宏力半导体制造有限公司 | 1.5T SONOS flush memory device and process |
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| CN1681128A (en) * | 2004-03-17 | 2005-10-12 | 阿克特兰斯系统公司 | Flash memory with enhanced programming and erasing connections and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110504273A (en) * | 2019-08-13 | 2019-11-26 | 上海华虹宏力半导体制造有限公司 | 1.5T SONOS flush memory device and process |
| CN110504273B (en) * | 2019-08-13 | 2022-03-08 | 上海华虹宏力半导体制造有限公司 | 1.5T SONOS flash memory device and process method |
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Application publication date: 20190101 |