CN109087953A

CN109087953A - A kind of thin film transistor (TFT) and its manufacturing method

Info

Publication number: CN109087953A
Application number: CN201810932407.6A
Authority: CN
Inventors: 董波; 简锦诚; 杨帆; 王志军
Original assignee: Nanjing CEC Panda LCD Technology Co Ltd; Nanjing Huadong Electronics Information and Technology Co Ltd; Nanjing CEC Panda FPD Technology Co Ltd
Current assignee: Nanjing CEC Panda LCD Technology Co Ltd
Priority date: 2018-08-16
Filing date: 2018-08-16
Publication date: 2018-12-25

Abstract

This invention discloses a method for manufacturing thin-film transistors. A thin photoresist region, a photoresist-free region, and a thick photoresist region are simultaneously formed using a semi-transparent mask. By controlling the transmittance of the semi-transparent mask, the source/drain metal layers in the photoresist-free region and the photoresist in the thin photoresist region are etched simultaneously, reducing the photoresist ashing process in the thin photoresist region. Using dry etching to etch the source/drain metal layers reduces the original single-sided critical dimension loss from 2µm to below 1µm, effectively solving the problem of large critical dimension loss (CD Loss). Since the photoresist ashing process in the thin photoresist region and the etching of the source/drain metal layers in the photoresist-free region are performed simultaneously, the number of etching processes is reduced, improving production efficiency. Furthermore, this invention has no special requirements for the semiconductor target material, reducing production costs.

Description

A kind of thin film transistor (TFT) and its manufacturing method

Technical field

The present invention relates to technical field of liquid crystal display more particularly to a kind of thin film transistor (TFT) and its manufacturing methods.

Background technique

In panel display apparatus, TFT thin film transistor monitor has small in size, low-power consumption, manufacturing cost low and radiation The features such as low, in the manufacturing process of thin film transistor (TFT) array, needs to form thin film transistor (TFT) array on the transparent substrate Using a certain number of photomask boards are arrived, the photoetching processes such as film forming, exposure, etching are repeated, on substrate to form film Each insulating film layer of lead, terminal, electrode of transistor array etc., from the extensive life of Thin Film Transistor-LCD in 1993 Since production manufacture starts, in order to reduce raw production cost, the yield of product is improved, each manufacturer constantly passes through change film crystal The structure of pipe reduces photoetching process number, currently, the structure of thin film transistor (TFT) is comparatively more stable, is difficult to pass through Change thin-film transistor structure and reduces photoetching process number, it can only by improving to existing photoetching process itself.

In the prior art, based on semi-transparent on the basis of BCE (Back Channel Etching carries on the back channel-etch type structure) Exposure mask platemaking technology (Half-Tone Mask abbreviation HTM) can be further reduced photoetching number, be exposed using semi-transparent mask plate light shield Later, two sections of etching technics are needed to form thin film transistor (TFT) pattern, first segment etching technics needs to etch the source and drain of non-channel region Pole layer and semiconductor layer, the ashing of second stage photoresist, etch channel region source-drain electrode layer.

When etching in the first stage, when etching sheet metal and semiconductor layer, half-and-half due to etching agent (such as fluorine-containing ketone acid) Conductor layer (general semiconductor layer) etch rate is higher, can generate quarter situation, generally adopts in the prior art when etching three layers With etching respectively, need to etch three times, in addition channel etching area, needs to etch for six times altogether, and existing photoresist layer adhesiveness Multiple etching cannot be supported, is caused when channel region etches, etching liquid penetrates into, and metal layer is caused to be corroded.

Semiconductor layer uses etch resistant target, metal layer and semiconductor layer can once be etched, original six etchings Technique can be kept to 4 etching technics, solve the problems, such as that photoresist layer adhesiveness cannot support multiple etching, but key size penalty (CD Loss) is larger, unilateral more than 2um, and requiring semiconductor layer target is etch resistance target, and target cost improves.

Summary of the invention

To solve the above-mentioned problems, the present invention provides a kind of manufacturing methods of thin film transistor (TFT), can reduce crucial ruler Very little loss (CD Loss), while reducing etching number, improving production efficiency.And since semiconductor layer target is without particular/special requirement, drop Low target cost.

Technical solution provided by the invention is as follows:

The invention discloses a kind of manufacturing methods of thin film transistor (TFT), method includes the following steps:

The first step forms grid layer on the glass substrate, and pattern the grid to be formed in pixel region and with The scan line of grid connection and the grid in terminal area；

Second step forms gate insulating layer on grid layer；

Third step forms semiconductor layer on gate insulating layer；

4th step forms source-drain electrode layer on the semiconductor layer；

5th step forms photoresist layer on source-drain electrode layer, is exposed using semi-transparent mask plate to photoresist layer

Processing, semi-transparent mask plate be formed with photoresist layer covering pixel region and have photoresist layer cover terminal area and The terminal area of no photoresist layer covering；It is described have photoresist layer cover pixel region include glimmer resistance layer covering pixel region and The pixel region of thick photoresist layer covering；

6th step, the pixel region of source-drain electrode layer and glimmer the resistance layer covering of the terminal area covered to no photoresist layer is simultaneously Dry etching is carried out, so that the source-drain electrode layer of the photoresist layer of the pixel region of glimmer resistance layer covering and the terminal area without photoresist layer covering It has been carved simultaneously, the terminal area of no photoresist layer covering exposes semiconductor layer, and the pixel region of glimmer resistance covering exposes source-drain electrode Layer；

7th step exposes semiconductor layer to the terminal area that no photoresist layer covers and carries out wet etching；

8th step, the source-drain electrode layer exposed to the pixel region of glimmer resistance layer covering carry out dry etching；

9th step, the pixel region cover to thick photoresist layer and the terminal area for having photoresist layer to cover carry out photoresist layer stripping From.

Further, in six step of step the and the 8th step, dry etching carries out dry etching, the gaseous mixture using mixed gas Body is oxygen and chlorine or oxygen and fluosilicic acid.

Further, in six step of step the and the 8th step, when carrying out dry etching, first lead to oxygen and source-drain electrode layer is carried out Sidewall oxidation, then logical chlorine or fluosilicic acid perform etching source-drain electrode layer.

Further, semi-transparent mask plate includes full impregnated area, semi-transparent area and impermeable area, the semi-transparent area in the step 5 Transmitance be 15%~50%.

Further, the photoresist layer of the pixel region of glimmer resistance covering with a thickness of 0.4um~1um.

Further, wet etching solution metal etch rate used by the step 7 is much smaller than semiconductor layer etching speed Rate.

Further, the wet etching solution is oxalic acid, and the metal etch rate isIt is per second, the semiconductor layer wet etching Rate isIt is per second.

Further, the semiconductor layer is IGZO semiconductor layer.

Further, the semiconductor layer is multilayered structure, and subsurface material is IGZO, upper layer of material IGZTO.

Further, the source-drain electrode layer is double-layer metal structure, the first sub- metal layer including contacting with semiconductor layer With the second sub- metal layer contacted with the first sub- metal layer

Further, the material of the described first sub- metal layer is titanium, and the material of the second sub- metal layer is copper.

The invention also discloses a kind of thin film transistor (TFT)s, are manufactured using the manufacturing method of above-mentioned thin film transistor (TFT).

Compared with prior art, the present invention controls the thickness of photoresist layer by semi-transparent mask plate, realizes the source of terminal area The glimmer resistance layer of drain electrode layer and pixel region is completed by etching simultaneously, is performed etching by the way of dry etching to source-drain electrode layer, solution The excessive problem of key size loss of having determined, unilateral key size loss is reduced to 1um hereinafter, the present invention it is only necessary to carry out Etching technics can complete the production of thin film transistor (TFT) three times, can solve the adhesion issues of photoresist layer, the present invention for Semiconductor layer target is without particular/special requirement, while the present invention goes back improving production efficiency, reduces the use of etachable material, and reduction is produced into This.

Detailed description of the invention

Fig. 1 to Fig. 7 is a kind of manufacturing method flow diagram of thin film transistor (TFT) of the present invention.

Reference signs list: 1- pixel region, 2- terminal area, 3- glass substrate, 4- grid, 5- gate insulating layer, 6- Semiconductor layer, 7- source-drain electrode layer, the sub- metal layer of 71- first, the sub- metal layer of 72- second, 8- photoresist layer, 9- are covered without photoresist layer Terminal area, the terminal area that 10- has photoresist layer to cover, the pixel region of 11- glimmer resistance layer covering, the covering of 12- thickness photoresist layer Pixel region, the semi-transparent mask plate of 13-, 131- full impregnated area, the semi-transparent area 132-, the impermeable area 133-.

Specific embodiment

In the following with reference to the drawings and specific embodiments, the present invention is furture elucidated, it should be understood that these embodiments are merely to illustrate It the present invention rather than limits the scope of the invention, after the present invention has been read, those skilled in the art are to of the invention each The modification of kind equivalent form falls within the application range as defined in the appended claims.

To make simplified form, part related to the present invention is only schematically shown in each figure, they are not represented Its practical structures as product.In addition, there is identical structure or function in some figures so that simplified form is easy to understand Component only symbolically depicts one of those, or has only marked one of those.Herein, "one" is not only indicated " only this ", can also indicate the situation of " more than one ".

The manufacturing method schematic diagram of the embodiment of the present invention thin film transistor (TFT) as shown in Figure 1 to Figure 7 shows the, this method include with Lower step:

The first step, forms grid layer on glass substrate 3, and grid pattern layers form the grid 4 being located in pixel region 1 With the scan line (not shown) being connect with grid 4 and the grid 4 in terminal area 2；

Second step forms gate insulating layer 5 on grid layer；

Third step forms semiconductor layer 6 on gate insulating layer 5；

Wherein semiconductor layer 6 is made of IGZO material, and in other embodiments, the structure of semiconductor layer 6 not only limits It is formed on single layer structure, has the stacked architecture of double-deck or bilayer or more for semiconductor layer 6, is equally applicable to film of the invention The manufacturing method of transistor, such as the subsurface material of semiconductor layer 6 is IGZO, upper layer of material IGZTO.

4th step forms source-drain electrode layer 7, as shown in Figure 1 on semiconductor layer 6；

Wherein source-drain electrode layer 7 is double-layer metal structure, the first sub- metal layer 71 including contacting with semiconductor layer 6 and with the The second sub- metal layer 72 that one sub- metal layer 71 contacts, the material of the first sub- metal layer 71 are titanium, the material of the second sub- metal layer 72 Material is copper, and the etch rate of the source-drain electrode layer 7 is less than 6 etch rate of semiconductor layer.

5th step, on source-drain electrode layer 7 formed photoresist layer 8, as shown in Fig. 2, using semi-transparent mask plate 13 to photoresist layer 8 into Row exposure-processed, as shown in Figure 3；

Wherein semi-transparent mask plate 13 includes positioned at full impregnated area 131, the semi-transparent area 132 positioned at pixel region 1 of terminal area 2 And be respectively positioned on the impermeable area 133 of pixel region 1 and terminal area 2, wherein the transmitance in the semi-transparent area 132 be 15%~ 50%；In pixel region 1, semi-transparent area 132 is located at the raceway groove opening region of pixel region 1 and between impermeable area 133；? In terminal area 1, impermeable area 133 is located at the top of grid 4 and between full impregnated area 131.

In the impermeable area 133 of photoresist layer 8, the pixel region 12 of thick photoresist layer covering is formed, the terminal of photoresist layer covering is formed Region 10；Photoresist layer 8 forms the pixel region 11 of glimmer resistance layer covering in semi-transparent area 132；Photoresist layer 8 is in full impregnated area 131 Under, form the terminal area 9 that cover without photoresist layer, the photoresist layer 8 for the pixel region 11 that wherein glimmer resistance covers with a thickness of 0.4um~1um.

6th step carries out first time etching to photoresist layer 8 to semi-transparent mask plate 13: the terminal area 9 of no photoresist layer covering Source-drain electrode layer 7 and glimmer resistance layer covering pixel region 11 simultaneously perform etching (specially dry etching) so that glimmer resistance layer is covered The photoresist layer 8 of the pixel region 11 of lid and the source-drain electrode layer 7 of the terminal area 9 without photoresist layer covering have been carved simultaneously, such as Fig. 4 institute Show；

The terminal area 9 without photoresist layer covering of terminal area 2 exposes semiconductor layer 6, the pixel region of glimmer resistance covering 11 expose source-drain electrode layer 7, wherein and in the present embodiment, lithographic method uses dry etching, and dry etching carries out dry etching using mixed gas, The mixed gas is oxygen and chlorine or oxygen and fluosilicic acid, when carrying out dry etching, first leads to oxygen and carries out to source-drain electrode layer 7 Sidewall oxidation, then logical chlorine or fluosilicic acid perform etching source-drain electrode layer 7.

7th step carries out second to photoresist layer 8 to semi-transparent mask plate 13 and etches: positioned at the terminal region that no photoresist layer covers The semiconductor layer 6 in domain 9 carries out wet etching, as shown in Figure 5；

Wherein, wet etching solution metal etch rate is much smaller than semiconductor layer etch rate, and wet etching solution is oxalic acid, the gold Belonging to etch rate isPer second, the semiconductor layer wet etching rate isIt is per second, therefore the 7th will not etch positioned at pixel region The grid in domain 1.

8th step carries out third time etching to photoresist layer 8: to the source-drain electrode layer in the pixel region 11 of glimmer resistance layer covering 7 carry out dry etching and leak out the semiconductor layer 6 being located in pixel region 1, as shown in Figure 6；

Wherein, dry etching carries out dry etching using mixed gas, and the mixed gas is oxygen and chlorine or oxygen and fluorine silicon Acid first leads to oxygen and carries out sidewall oxidation, then logical chlorine or fluosilicic acid to source-drain electrode layer 7 to source-drain electrode layer 7 when carrying out dry etching It performs etching.

9th step, the pixel region 12 cover to thick photoresist layer and the terminal area 10 for having photoresist layer to cover carry out photoresist Layer 8 is removed, as shown in Figure 7.

The invention also discloses thin film transistor (TFT)s manufactured by a kind of manufacturing method as above-mentioned thin film transistor (TFT).

The preferred embodiment of the present invention has been described above in detail, but during present invention is not limited to the embodiments described above Detail can carry out a variety of equivalents to technical solution of the present invention (in full within the scope of the technical concept of the present invention Amount, shape, position etc.), these equivalents all belong to the scope of protection of the present invention.

Claims

1. A method for manufacturing a thin film transistor, characterized in that the method comprises the following steps:

In the first step, a gate layer is formed on the glass substrate, and a gate located in the pixel area, a scanning line connected to the gate, and a gate located in the terminal area are formed by patterning;

In the second step, a gate insulating layer is formed on the gate layer;

The third step is to form a semiconductor layer on the gate insulating layer;

The fourth step is to form a source and drain layer on the semiconductor layer;

The fifth step is to form a photoresist layer on the source and drain layers, and use a semi-transparent mask to expose the photoresist layer

processing, the semi-transparent mask plate forms a pixel area covered by a photoresist layer, a terminal area covered by a photoresist layer, and a terminal area covered by a non-photoresist layer; the pixel area covered by a photoresist layer includes a thin photoresist layer covered Pixel area and pixel area covered by thick photoresist layer;

The sixth step is to simultaneously perform dry etching on the source and drain layers of the terminal area covered by the thin photoresist layer and the pixel area covered by the thin photoresist layer, so that the photoresist layer of the pixel area covered by the thin photoresist layer and the terminal area covered by the non-photoresist layer The source and drain layers of the photoresist are engraved at the same time, the semiconductor layer is exposed in the terminal area covered by no photoresist layer, and the source and drain layer is exposed in the pixel area covered by thin photoresist layer;

In the seventh step, wet etching is performed on the exposed semiconductor layer in the terminal area not covered by the photoresist layer;

The eighth step is dry etching the source and drain layers exposed in the pixel area covered by the thin photoresist layer;

In the ninth step, the photoresist layer is stripped on the pixel area covered by the thick photoresist layer and the terminal area covered by the photoresist layer.

2. The manufacturing method of a thin film transistor according to claim 1, characterized in that: in the sixth step and the eighth step of the step, the dry etching uses a mixed gas for dry etching, and the mixed gas is oxygen and chlorine or oxygen and fluosilicic acid.

3. The manufacturing method of a thin film transistor according to claim 2, characterized in that: in the sixth step and the eighth step of the step, when performing dry etching, oxygen is first passed through to oxidize the sidewall of the source and drain layers, The source and drain layers are etched by flowing chlorine gas or fluosilicic acid.

4. The manufacturing method of a thin film transistor according to claim 1, characterized in that: the semi-transparent mask in the step 5 includes a fully transparent area, a semi-transparent area and an opaque area, and the transparent area of the semi-transparent area The rate is 15% to 50%.

5 . The method for manufacturing a thin film transistor according to claim 1 , wherein the thickness of the photoresist layer in the pixel area covered by the thin photoresist is 0.4 um-1 um.

6 . The method for manufacturing a thin film transistor according to claim 1 , wherein the metal etching rate of the wet etching solution used in the seventh step is much lower than the etching rate of the semiconductor layer. 7 .

7. The manufacturing method of a thin film transistor according to claim 6, characterized in that: the wet etching solution is oxalic acid, and the metal etching rate is The wet etching rate of the semiconductor layer is

8. The method for manufacturing a thin film transistor according to claim 1, wherein the semiconductor layer is an IGZO semiconductor layer.

9. The manufacturing method of a thin film transistor according to claim 1, characterized in that: the source and drain layers are a double-layer metal structure, including a first sub-metal layer in contact with the semiconductor layer and a sub-metal layer in contact with the first sub-metal layer. The second sub-metal layer.

10. A thin film transistor, characterized in that it is manufactured by the method for manufacturing a thin film transistor according to any one of claims 1-9.