CN109065509A - Chip-packaging structure and preparation method thereof with single cofferdam and outer Mobile Communication hole - Google Patents
Chip-packaging structure and preparation method thereof with single cofferdam and outer Mobile Communication hole Download PDFInfo
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- CN109065509A CN109065509A CN201810910132.6A CN201810910132A CN109065509A CN 109065509 A CN109065509 A CN 109065509A CN 201810910132 A CN201810910132 A CN 201810910132A CN 109065509 A CN109065509 A CN 109065509A
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- substrate
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- electroplating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
Abstract
本发明揭示了一种带有单围堰及外移通孔的芯片封装结构及其制作方法，封装结构包括：封装基板，具有若干外部引脚；滤波器芯片，具有若干电极；若干互连结构，用于导通若干电极及若干外部引脚；围堰，与芯片下表面及基板上表面配合而围设形成空腔；其中，围堰位于若干电极的内侧，封装基板具有若干通孔，互连结构包括相互导通的第一互连结构及第二互连结构，第一互连结构导通电极，第二互连结构通过通孔而导通外接引脚，通孔位于第一互连结构远离空腔的一侧。本发明通过设置围堰形成空腔，可以有效避免在封装结构制作过程中或是在封装结构使用过程中外界物质进入空腔内部而影响滤波器芯片的正常使用，从而提高封装结构的整体性能。
The invention discloses a chip packaging structure with a single cofferdam and outwardly shifted through holes and a manufacturing method thereof. The packaging structure includes: a packaging substrate with a number of external pins; a filter chip with a number of electrodes; a number of interconnection structures , used to connect some electrodes and some external pins; cofferdams, cooperating with the lower surface of the chip and the upper surface of the substrate to form a cavity; wherein, the cofferdams are located inside the electrodes, and the packaging substrate has a number of through holes for mutual The interconnection structure includes a first interconnection structure and a second interconnection structure that are connected to each other. The first interconnection structure conducts electrodes, and the second interconnection structure conducts external pins through through holes. The through holes are located in the first interconnection. The side of the structure facing away from the cavity. The present invention forms a cavity by setting cofferdams, which can effectively prevent foreign substances from entering the cavity during the manufacturing process of the packaging structure or during the use of the packaging structure and affect the normal use of the filter chip, thereby improving the overall performance of the packaging structure.
Description
Technical field
The present invention relates to field of semiconductor package more particularly to a kind of chip package knots with single cofferdam and outer Mobile Communication hole
Structure and preparation method thereof.
Background technique
RF IC (RFIC) is widely used in wireless device, for example, cellular telephone.
RFIC is on matrix the discrete of transmission line, matching network and inductance coil, resistance, capacitor and transistor etc
Element is combined together the subsystem for providing and capable of transmitting and receive high-frequency signal, for example, in about 0.1 to 100 gigabits
In the range of conspicuous (GHz), the encapsulation of RFIC differs markedly from the encapsulation of digital integrated electronic circuit, because the encapsulation is often radio frequency electrical
The a part on road, moreover, because the rf electric field and/or magnetic field energy of RFIC complexity and any neighbouring insulator and conductor are mutual
Effect, in order to meet wireless industrial increasing demand, RFIC encapsulation development is tried to provide more small and exquisite, more cheap, performance more
High adapts to the device of more bare die radio-frequency modules, while providing higher reliability and using unleaded solder and other " greens
" material.The one chip encapsulation that single or multiple bare die RFIC is encapsulated individually is to solve the small size and inexpensive demand of RFIC
Direct solution, and be used for most of RFIC now.
Microelectromechanical systems (MEMS) permits the controlled conversion between miniature scale mechanical movement and specified electric signal,
For example, consistent with specified frequency, MEMS is being widely used for RFIC.
Based on mechanical movement, RF MEMS is able to achieve fabulous signal quality for radio frequency band filter, and citing comes
It says, SAW filter converts electrical signals into mechanical wave, and the latter propagates before its converted back into electric signals along piezo-electric crystal matrix
When be delayed by；BAW filter realizes expected special resonance using volume mass motion；And in RF switch, electric signal
For controlling the movement of microelectrode, switch is opened or closed.
Present MEMS technology grows up from semiconductor fabrication process, however, mechanical fortune associated with MEMS
Dynamic packaging structure and the requirement for requiring to be totally different from traditional semiconductor integrated circuit, specifically, in all MEMS collection
Inside circuit, some materials must be moved freely uninterruptedly, and therefore, MEMS integrated circuit must be shielded in movement material
Small vacuum or air pocket are formed around material to allow them to move while to protect them.
And in the prior art, a closing and reliable cavity can not be formed to realize the protection of circuit or other structures.
Summary of the invention
The purpose of the present invention is to provide a kind of chip-packaging structure with single cofferdam and outer Mobile Communication hole and its production sides
Method.
One of for achieving the above object, an embodiment of the present invention provides a kind of with single cofferdam and outer Mobile Communication hole
Chip-packaging structure, comprising:
Package substrate has the upper surface of base plate and base lower surface being oppositely arranged, the side tool of the base lower surface
There are several external pins；
Filter chip, has the chip upper surface that is oppositely arranged and a chip lower surface, the chip lower surface with it is described
Upper surface of base plate is arranged face-to-face, and the chip lower surface has several electrodes；
Several interconnection structures, for several electrodes and several external pins to be connected；
Cofferdam cooperates with the chip lower surface and the upper surface of base plate and encloses to set to form cavity；
Wherein, the cofferdam is located at the inside of several electrodes, and the package substrate has several through-holes, the interconnection structure
The first interconnection structure and the second interconnection structure including mutual conduction, first interconnection structure are connected the electrode, and described the
The external pin is connected by the through-hole in two interconnection structures, and the through-hole is located at first interconnection structure far from described
The side of cavity.
As the further improvement of an embodiment of the present invention, first interconnection structure includes metal column and scolding tin, institute
Stating the second interconnection structure includes electroplated layer, and the electrode is connected in the metal column, and the external pin, institute is connected in the electroplated layer
Scolding tin is stated for the metal column and the electroplated layer to be connected.
As the further improvement of an embodiment of the present invention, the electroplated layer includes connected positioned at table on the substrate
First electroplated layer in face, the second electroplated layer positioned at the through-hole wall and the third electroplated layer positioned at the base lower surface,
The scolding tin coats the metal column and is connected with first electroplated layer, and the third electroplated layer connects the external pin.
As the further improvement of an embodiment of the present invention, the first electroplated layer for connecting the scolding tin extends to the base
The width of plate upper surface is greater than the width that corresponding third electroplated layer extends to the base lower surface.
As the further improvement of an embodiment of the present invention, first electroplated layer is connected close to the side of the cavity
The cofferdam.
As the further improvement of an embodiment of the present invention, several electrodes, which enclose, to be set described in the Internal periphery to be formed connection
Cofferdam.
As the further improvement of an embodiment of the present invention, the chip lower surface covers the upper surface in the cofferdam,
The upper surface of base plate covers the lower surface in the cofferdam.
As the further improvement of an embodiment of the present invention, the encapsulating structure further includes remote positioned at the package substrate
The plastic packaging layer of side from the base lower surface, the plastic packaging layer coat the cofferdam lateral area and the filter simultaneously
Chip, the plastic packaging layer fills the through-hole, and the encapsulating structure further includes being set to the base lower surface and exposing
The soldermask layer of the external pin.
One of for achieving the above object, an embodiment of the present invention provides a kind of with single cofferdam and outer Mobile Communication hole
The production method of chip-packaging structure, comprising steps of
S1: providing filter chip, has the chip upper surface being oppositely arranged and chip lower surface, the chip following table
Face has several electrodes；
S2: metal column is formed in the lower surface of the electrode；
S3: providing package substrate, has the upper surface of base plate and base lower surface being oppositely arranged；
S4: in forming several through-holes on the package substrate；
S5: electroplated layer is formed in the upper surface of base plate of the through-hole wall and the connection through-hole wall, base lower surface；
S6: cofferdam is formed in the upper surface of base plate；
S7: in putting scolding tin on the electroplated layer between the through-hole and the cofferdam；
S8: the filter chip is assembled to the package substrate, the chip lower surface and the upper surface of base plate
Setting face-to-face, the cofferdam are located at the inside of several electrodes, and on the cofferdam and the chip lower surface and the substrate
Surface engagement and enclose to set to form cavity, the metal column and the electroplated layer is connected in scolding tin；
S9: external pin is formed below the electroplated layer.
As the further improvement of an embodiment of the present invention, step S5, S6, S7 are specifically included:
The second photoresist film and third photoresist film are respectively formed in the upper surface of base plate and the base lower surface；
In the second photoresist film exposure and imaging formed the second hole, second hole expose the through-hole and
Upper surface of base plate；
In the third photoresist film exposure and imaging formed third hole, the third hole expose the through-hole and
Base lower surface；
The first electroplated layer is formed in being exposed to outer upper surface of base plate, forms the second plating in being exposed to outer through-hole wall
Layer forms third electroplated layer in being exposed to outer base lower surface；
Remove the second photoresist film and third photoresist film；
Cofferdam is formed in the upper surface of base plate, the cofferdam connects one of first electroplated layer far from the through-hole
Side；
In first electroplated layer close to the region point scolding tin in the cofferdam；
Step S9 is specifically included:
Plastic packaging layer is formed far from the side of the base lower surface in the package substrate, the plastic packaging layer coats institute simultaneously
Cofferdam lateral area and the filter chip are stated, and the plastic packaging layer fills the through-hole；
Soldermask layer is formed in base lower surface, the soldermask layer coats the base lower surface and third plating simultaneously
Layer；
Several 4th holes are formed in the soldermask layer exposure and imaging, the 4th hole exposes the third plating
Layer；
In forming ball grid array in several 4th holes.
Compared with prior art, the beneficial effects of the present invention are: present embodiments forms cavity by setting cofferdam, can
With effectively avoid in encapsulating structure manufacturing process or in encapsulating structure use process external substance enter cavity inside and
The normal use for influencing filter chip, to improve the overall performance of encapsulating structure.
Detailed description of the invention
Fig. 1 is the encapsulating structure cross-sectional view of first embodiment of the invention；
Fig. 2 is the birds-eye perspective of the encapsulating structure part-structure of first embodiment of the invention；
Fig. 3 is the production method block diagram of the encapsulating structure of first embodiment of the invention；
Fig. 4 a- Fig. 4 s is the production method flow chart of the encapsulating structure of first embodiment of the invention；
Fig. 5 is the encapsulating structure cross-sectional view of second embodiment of the invention；
Fig. 6 is the birds-eye perspective of the encapsulating structure part-structure of second embodiment of the invention；
Fig. 7 is the production method block diagram of the encapsulating structure of second embodiment of the invention；
Fig. 8 a- Fig. 8 s is the production method flow chart of the encapsulating structure of second embodiment of the invention.
Specific embodiment
Below with reference to specific embodiment shown in the drawings, the present invention will be described in detail.But these embodiments are simultaneously
The present invention is not limited, structure that those skilled in the art are made according to these embodiments, method or functionally
Transformation is included within the scope of protection of the present invention.
In each diagram of the application, for the ease of illustration, structure or partial certain sizes can be relative to other knots
Structure or part are exaggerated, and therefore, are only used for the basic structure of the theme of diagram the application.
In addition, the term of the representation space relative position used herein such as "upper", " top ", "lower", " lower section " is
A unit as shown in the drawings or feature are described for the purpose convenient for explanation relative to another unit or feature
Relationship.The term of relative space position can be intended to include equipment in use or work other than orientation as shown in the figure not
Same orientation.For example, being described as being located at other units or feature " below " or " under " if the equipment in figure overturn
Unit will be located at other units or feature " top ".Therefore, exemplary term " lower section " can include above and below both
Orientation.Equipment can otherwise be directed (be rotated by 90 ° or other directions), and be interpreted accordingly it is used herein with it is empty
Between relevant description language.
Join Fig. 1, is cuing open for the chip-packaging structure 100 with single cofferdam and outer Mobile Communication hole of first embodiment of the invention
View.
Encapsulating structure 100 includes package substrate 10, filter chip 20, several interconnection structures 30 and cofferdam 40.
Package substrate 10 has the upper surface of base plate 11 and base lower surface 12 being oppositely arranged, the side of base lower surface 12
With several external pins 121.
Here, package substrate 10 is the loading plate for carrying chip, and package substrate 10 can be printing made of organic resin
Circuit board is also possible to glass substrate or ceramic substrate etc..
External pin 121 can be ball grid array (Ball Grid Array, BGA), pad etc., and encapsulating structure 100 is logical
Crossing external pin 121 can be electrically connected with realizations such as other chips or substrates, and here, external pin 121 is with ball grid array 121
For, external pin 121 protrudes out the lower surface of encapsulating structure 100.
Filter chip 20 has the chip upper surface 21 and chip lower surface 22, chip lower surface 22 and base being oppositely arranged
Plate upper surface 11 is arranged face-to-face, and chip lower surface 22 has several electrodes 221.
Here, filter chip 20 can be surface acoustic wave filter chip (Surface Acoustic Wave, SAW)
Or bulk acoustic wave filter chip (Bulk Acoustic Wave, BAW), but not limited to this, 20 surface of filter chip
Active region (Active Zone) needs to work normally under the contact of no foreign object or coverage condition, that is to say, that needs
A cavity is formed in the lower section of filter chip 20 to protect the active region.
The lower surface of electrode 221 is flushed with chip lower surface 22, i.e., electrode 221 is embedded in filter chip 20, and sudden and violent
Expose electrode surface.
Electrode 221 protrudes out chip lower surface 22 towards the direction far from chip upper surface 21, and but not limited to this.
In general, the size of filter chip 20 is less than the size of package substrate 10.
Several interconnection structures 30 are for being connected several electrodes 221 and several external pins 121.
Cofferdam 40 and chip lower surface 22 and upper surface of base plate 11 cooperate and enclose to set to form cavity S, the corresponding filtering of cavity S
The active region on 20 surface of device chip.
Here, cofferdam 40 is located at the inside of several electrodes 221, and package substrate 10 has several through-holes 13, interconnection structure 30
The first interconnection structure and the second interconnection structure including mutual conduction, the first interconnection structure conduction electrode 221, the second interconnection structure
External pin 121 is connected by through-hole 13, through-hole 13 is located at side of first interconnection structure far from cavity S.
It should be noted that " the second interconnection structure passes through through-hole 13 " refers to that at least partly structure of the second interconnection structure is worn
Corresponding through-hole 13 is crossed, to realize the interconnection of electrode 221 and external pin 121.
Present embodiment by setting cofferdam 40 formed cavity S, it is possible to prevente effectively from encapsulating structure manufacturing process or
It is that external substance enters the normal use for inside cavity S and influencing filter chip 20 in encapsulating structure use process, thus
Improve the overall performance of encapsulating structure 100.
In addition, through-hole 13 is located at side of first interconnection structure far from cavity S, the i.e. external pin of base lower surface 12
121 can be located at filter chip 20 towards shifting outside the two sides of filter chip 20 convenient for providing the substrate 10 of encapsulating structure 100
Lower zone arranges other chip buried spaces in advance, consequently facilitating realize high-performance and small size multi-chip 2.5D or
3D stacks integration packaging and mould group.
In conjunction with Fig. 2, several electrodes 221 in array distribution in chip lower surface 22, and between having between adjacent electrode 221
Every there is a space, cofferdam 40 is located in the space, i.e., cofferdam 40 is located at the interior of several electrodes 221 between two column electrodes 221
Side.
Cofferdam 40 is closed cyclic structure, and chip lower surface 22 covers the upper surface in cofferdam 40, and upper surface of base plate 11 covers
The lower surface in lid cofferdam 40, in this way, cofferdam 40, chip lower surface 22 and upper surface of base plate 11 complement each other to form case type sky
Chamber S.
Cofferdam 40 and the mutually adjacent setting of several electrodes 221.
Cofferdam 40 is made of photaesthesia insulating materials, and but not limited to this.
In the present embodiment, encapsulating structure 100 further includes coating 40 lateral area of cofferdam and filter chip 20 simultaneously
Plastic packaging layer 50, and plastic packaging layer 50 is located at side of the package substrate 10 far from base lower surface 12.
Here, " 40 lateral area of cofferdam " refers to all open areas of the side positioned at cofferdam 40 far from cavity S, also
It is to say, plastic packaging layer 50 coats open area all around filter chip 20, and plastic packaging layer 50 is located at the upper of package substrate 10
Side.
Plastic packaging layer 50 can be EMC (Expoy Molding Compound) plastic packaging layer, enclose since present embodiment utilizes
Weir 40 can stop external substance to enter cavity S, without considering whether plastic packaging layer 50 can influence in cavity S because of problem of materials
Protection zone, therefore, the range of choice of 50 material of plastic packaging layer expands significantly, and then can evade the choosing of specific capsulation material
It selects, substantially widen plastic packaging making technology window and effectively reduce cost.
In the present embodiment, encapsulating structure 100 further includes being set to base lower surface 12 and exposing external pin 121
Soldermask layer 60.
Continue to join Fig. 1 and Fig. 2, in the present embodiment, the first interconnection structure includes metal column 311 and scolding tin 331, and second
Interconnection structure includes electroplated layer 321,311 conduction electrode 221 of metal column, the conducting external pin 121 of electroplated layer 321, the use of scolding tin 331
In conducting metal column 311 and electroplated layer 321, and the lower section of electroplated layer 321 connects external pin 121.
Electroplated layer 321 is extended to upper surface of base plate 11 and base lower surface 12 respectively from 13 inner wall of through-hole, electroplated layer 321
Lower surface is plane.
It should be noted that base lower surface 12 is also equipped with electroplated layer 321 far from the region of through-hole 13 and is located at plating
The external pin 121 of 321 lower section of layer.
Here, metal column 311 is copper post 311, and electroplated layer 321 is layers of copper 321, and but not limited to this.
Scolding tin 331 is coated on the outside of copper post 311, and the one end of scolding tin 331 far from copper post 311 be located at upper surface of base plate
11 layers of copper 321 be combined with each other, so as to conduction electrode 221 and external pin 121.
The advantage that copper post 311 and scolding tin 331 is arranged is: (1) scolding tin 331 is molten condition in reflow soldering process, just
It is combined in copper post 311, and combines effect preferable；(2) contact area between scolding tin 331 and layers of copper 321 is big, and electricity can be improved
Property transmission performance, also can be improved the strong degree that scolding tin 331 is combined with layers of copper 321；(3) copper post 311 has already taken up a part of sky
Between, the raw material usage amount of scolding tin 331 can be reduced when scolding tin 331 is set in the through-hole 13 at this time, reduces the weldering of scolding tin 331
Technology difficulty is connect, weld interval is shortened, and then improves welding production capacity；(4) 311 appearance of copper post is significant, can be used as identification
It is detected and possible defect recognition with improving recognition efficiency convenient for automatic aspect in portion.
In the present embodiment, layers of copper 321 is including being connected positioned at the first layers of copper 3211 of upper surface of base plate 11, positioned at logical
Second layers of copper 3212 of 13 inner wall of hole and third layers of copper 3213 positioned at base lower surface 12, scolding tin 331 coat metal column 311 simultaneously
It is connected with the first layers of copper 3211, third layers of copper 3213 connects external pin.
The width that first layers of copper 3211 of connection scolding tin 331 extends to upper surface of base plate 11 is greater than corresponding third electroplated layer
3213 extend to the width of base lower surface 12.
Here, on the one hand, upper surface of base plate 11 and base lower surface 12 are provided with layers of copper 321, and layers of copper 321 can be improved
The strong degree combined with package substrate 10；On the other hand, the first layers of copper 3211 extends towards 221 direction of electrode, is convenient for scolding tin 331
Connect the first layers of copper 3211, and since scolding tin 331 at this time does not enter through-hole 13, through-hole 13 can towards moving outside two sides so that
The external pin 121 of base lower surface 12 can move in addition.
In addition, the first layers of copper 3211 connects cofferdam 40 close to the side of cavity S.
Copper post 311 is laid in the intermediate region of electrode 221, scolding tin 331 surround copper post 311 and scolding tin 331 and cofferdam 40 it
Between have gap, at this point, in the gap and its extended segment be filled with plastic packaging layer 50.
An embodiment of the present invention also provides a kind of production side of chip-packaging structure with single cofferdam and outer Mobile Communication hole
Method, in conjunction with the explanation and Fig. 3, Fig. 4 a to Fig. 4 s of the aforementioned chip-packaging structure 100 with single cofferdam and outer Mobile Communication hole, production side
Method comprising steps of
S1: ginseng Fig. 4 a provides filter chip 20, has the chip upper surface 21 being oppositely arranged and chip lower surface
22, chip lower surface 22 has several electrodes 221；
S2: ginseng Fig. 4 b to Fig. 4 e forms metal column 311 in the lower surface of electrode 221；
It specifically includes:
Join Fig. 4 b, forms the first photoresist film 70 in chip lower surface 22；
Join Fig. 4 c, forms several first holes 71 in 70 exposure and imaging of the first photoresist film, the first hole 71 exposes
Electrode 221；
Join Fig. 4 d, in forming several copper posts 311 in several first holes 71,；
Join Fig. 4 e, removes the first photoresist film 70.
S3: ginseng Fig. 4 f provides package substrate 10, has the upper surface of base plate 11 and base lower surface 12 being oppositely arranged；
S4: ginseng Fig. 4 g, in forming several through-holes 13 on package substrate 10；
S5: ginseng Fig. 4 h to Fig. 4 k, in 13 inner wall of through-hole and upper surface of base plate 11, the base lower surface of connection 13 inner wall of through-hole
12 form electroplated layer 321；
It specifically includes:
Join Fig. 4 h, is respectively formed the second photoresist film 90 and third photoresist in upper surface of base plate 11 and base lower surface 12
Film 92；
Join Fig. 4 i, forms the second hole 91 in 90 exposure and imaging of the second photoresist film, the second hole 91 exposes through-hole
13 and upper surface of base plate 11, third hole 93 is formed in 92 exposure and imaging of third photoresist film, third hole 93 exposes logical
Hole 13 and base lower surface 12；
Join Fig. 4 j, the first layers of copper 3211 is formed in being exposed to outer upper surface of base plate 11, in the through-hole 13 outside being exposed to
Wall forms the second layers of copper 3212, forms third layers of copper 3213 in being exposed to outer base lower surface 12；
Join Fig. 4 k, removes the second photoresist film 90 and third photoresist film 92.
S6: ginseng Fig. 4 l and Fig. 4 m forms cofferdam 40 in upper surface of base plate 11；
It specifically includes:
Join Fig. 4 l, lays photaesthesia insulating film 80 in upper surface of base plate 11；
Join Fig. 4 m, exposure and imaging forms cofferdam 40, and cofferdam 40 is located at the inside of several through-holes 13, the connection of cofferdam 40 first
Side of the layers of copper 3211 far from through-hole 13.
It should be noted that being formed since independent package substrate 10 can be divided by the large substrates of wafer scale, molding is enclosed
When weir 40, can on large substrates the multiple cofferdam 40 of straight forming, then carry out the segmentation of large substrates again and obtain having single
The single package substrate 10 in cofferdam 40, in this way, being greatly improved packaging efficiency, certainly, cofferdam 40 is also plastic in filter core
On piece 20.
S7: ginseng Fig. 4 n, in point scolding tin 331 on the electroplated layer 321 between through-hole 13 and cofferdam 40；
It specifically includes:
Join Fig. 4 n, in the first layers of copper 3211 close to the region point scolding tin 331 in cofferdam 40.
Filter chip 20 is assembled to package substrate 10, chip lower surface 22 and 11 face of upper surface of base plate by S8: ginseng Fig. 4 o
It is provided opposite to, cofferdam 40 is located at the inside of several electrodes 221, and cofferdam 40 and chip lower surface 22 and upper surface of base plate 11 cooperate
And enclose to set to form cavity S, metal column 311 and electroplated layer 321 is connected in scolding tin 331；
After the step further include:
Join Fig. 4 p, forms plastic packaging layer 50 far from the side of base lower surface 12 in package substrate 10, plastic packaging layer 50 wraps simultaneously
40 lateral area of cofferdam and filter chip 20 are covered, and plastic packaging layer 50 fills through-hole 13.
S9: ginseng Fig. 4 q to Fig. 4 s forms external pin 121 below electroplated layer 321.
It specifically includes:
Join Fig. 4 q, forms soldermask layer 60 in base lower surface 12, soldermask layer 60 coats base lower surface 12 and third simultaneously
Layers of copper 3213；
Join Fig. 4 r, forms several 4th holes 61 in 60 exposure and imaging of soldermask layer, the 4th hole 61 exposes third copper
Layer 3213；
Join Fig. 4 s, in formation ball grid array 121 in several 4th holes 61.
Other explanations of the production method of the encapsulating structure of present embodiment can saying with reference to above-mentioned encapsulating structure 100
Bright, details are not described herein.
Join Fig. 5, is the cross-sectional view of the encapsulating structure 100a of second embodiment of the invention.
Encapsulating structure 100a includes package substrate 10a, filter chip 20a, several interconnection structure 30a and cofferdam 40a.
Package substrate 10a has the upper surface of base plate 11a and base lower surface 12a being oppositely arranged, base lower surface 12a's
Side has several external pin 121a.
Here, package substrate 10a is the loading plate for carrying chip, and package substrate 10a can be print made of organic resin
Printed circuit board is also possible to glass substrate or ceramic substrate etc..
External pin 121a can be ball grid array (Ball Grid Array, BGA), pad etc., encapsulating structure 100a
It can be electrically connected with realizations such as other chips or substrates by external pin 121a, here, external pin 121a is with ball bar battle array
For arranging 121a, external pin 121a protrudes out the lower surface of encapsulating structure 100a.
Filter chip 20a has the chip upper surface 21a and chip lower surface 22a being oppositely arranged, chip lower surface 22a
It is arranged face-to-face with upper surface of base plate 11a, chip lower surface 22a has several electrode 221a.
Here, filter chip 20a can be surface acoustic wave filter chip (Surface Acoustic Wave, SAW)
Or bulk acoustic wave filter chip (Bulk Acoustic Wave, BAW), but not limited to this, the surface filter chip 20a
Active region (Active Zone) needs to work normally under the contact of no foreign object or coverage condition, that is to say, that needs
A cavity is formed in the lower section of filter chip 20a to protect the active region.
The lower surface of electrode 221a is flushed with chip lower surface 22a, i.e., electrode 221a is embedded in filter chip 20a,
And expose electrode surface.
Electrode 221a protrudes out chip lower surface 22a towards the direction far from chip upper surface 21a, and but not limited to this.
In general, the size of filter chip 20a is less than the size of package substrate 10a.
Several interconnection structure 30a are for being connected several electrode 221a and several external pin 121a.
Cofferdam 40a includes positioned at the first cofferdam 41a of the inside of several electrode 221a and on the outside of several electrode 221a
The second cofferdam 42a, the first cofferdam 41a and chip lower surface 22 and the cooperation of upper surface of base plate 11 and enclose to set to form cavity S, the sky
The active region on the surface chamber S respective filter chip 20a.
Here, package substrate 10a has several through-hole 13a, and interconnection structure 30 includes the first interconnection structure of mutual conduction
And external pin is connected by through-hole 13a in second interconnection structure, the first interconnection structure conduction electrode 221a, the second interconnection structure
121a, through-hole 13a are located at side of first interconnection structure far from cavity S.
It should be noted that " the second interconnection structure passes through through-hole 13a " refers at least partly structure of the second interconnection structure
Across corresponding through-hole 13a, to realize the interconnection of electrode 221a and external pin 121a.
Present embodiment forms cavity S by the first cofferdam 41a of setting, it is possible to prevente effectively from encapsulating structure manufacturing process
In or external substance enters the normal use for inside cavity S and influencing filter chip 20a in encapsulating structure use process,
To improve the overall performance of encapsulating structure 100a.
In addition, since cofferdam 40a has certain height, it, may can not when the lower surface area of cofferdam 40a is too small
The cofferdam 40a of the height is supported, collapsing phenomenon occurs so as to cause cofferdam 40a, if the cofferdam 40a of present embodiment includes being located at
The first cofferdam 41a on the inside of dry through-hole 13a and the second cofferdam 42a on the outside of several through-hole 13a, cofferdam 40a have enough
Big lower surface improves the stability of entire cofferdam 40a；In addition the upper surface cofferdam 40a can be with filter chip 20a following table
Filter chip 20a lower surface whole region outside the region cavity S of face combines, and further increases the forming stability of cavity S.
Moreover, through-hole 13a is located at side of first interconnection structure far from cavity S, the i.e. external pin of base lower surface 12a
121a can be convenient for encapsulating structure 100a subsequent and other chips or other substrates etc. towards shifting outside the two sides of filter chip 20a
It is combined with each other, that is, provides enough combination spaces.
In conjunction with Fig. 6, several electrode 221a have in array distribution in chip lower surface 22a, and between adjacent electrode 221a
It is spaced, there is a space between two column electrode 221a, the first cofferdam 41a is located in the space, i.e. the first cofferdam 41a is located at several
The inside of electrode 221a, the second cofferdam 42a are located at outside the space, i.e. the second cofferdam 42a is located at the outside of several electrode 221a.
That is, several electrode 221a, which enclose, sets the Internal periphery to be formed the first cofferdam 41a of connection, several electrode 221a, which enclose, to be set
The outer profile of formation connects the second cofferdam 42a.
It should be noted that can be independent from each other between the first cofferdam 41a and the second cofferdam 42a, such as first encloses
Weir 41a is the first cyclic structure, and the first cyclic structure connects the inside of several electrode 221a, and the second cofferdam 42a is second cyclic annular
Structure, the second cyclic structure connect the outside of several electrode 221a.
Certainly, be also possible between the first cofferdam 41a and the second cofferdam 42a it is interconnected, at this point, the first cofferdam 41a
Between the second cofferdam 42a by third cofferdam 43a realize interconnection, third cofferdam 43a between adjacent electrode 221a or
Person is other regions, that is to say, that cofferdam 40a at this time is covered with cavity S periphery, and cofferdam 40a is covered with electrode 221a periphery.
In the present embodiment, chip lower surface 22a cover the first cofferdam 41a upper surface, and chip lower surface 22a with
The upper surface portion of second cofferdam 42a is overlapped, and upper surface of base plate 11a covers lower surface and the second cofferdam 42a of the first cofferdam 41a
Lower surface.
Second cofferdam 42a is located at filtering towards the lateral border that the direction far from the first cofferdam 41a extends up to the second cofferdam 42a
Between the lateral border and through-hole 13a of device chip 20a, but not limited to this.
Cofferdam 40a is made of photaesthesia insulating materials, and but not limited to this.
In the present embodiment, encapsulating structure 100a further include coat simultaneously region that the second cofferdam 42a is exposed and
The plastic packaging layer 50a of filter chip 20a, plastic packaging layer 50a fill through-hole 13a, and to be located at package substrate 10a separate by plastic packaging layer 50a
The side of base lower surface 12a.
Plastic packaging layer 50a can be EMC (Electro Magnetic Compatibility) plastic packaging layer, due to this embodiment party
Formula can stop external substance to enter cavity S using cofferdam 40a, without consider plastic packaging layer 50a whether can because of problem of materials and
The protection zone in cavity S is influenced, therefore, the range of choice of plastic packaging layer 50a material expands significantly, and then can be effectively reduced into
This.
In the present embodiment, encapsulating structure 100a further includes being set to base lower surface 12a and exposing external pin
The soldermask layer 60a of 121a.
Continue to join Fig. 5 and Fig. 6, in the present embodiment, the first interconnection structure includes metal column 311a and scolding tin 331a, the
Two interconnection structures include electroplated layer 321a, and external pin 121a, weldering is connected in metal column 311a conduction electrode 221a, electroplated layer 321a
Tin 331a is for being connected metal column 311a and electroplated layer 321a, and the lower section of electroplated layer 321a connects external pin 121a.
Electroplated layer 321a is extended to upper surface of base plate 11a and base lower surface 12a respectively from through-hole 13a inner wall, electroplated layer
321 lower surface is plane.
It should be noted that base lower surface 12a is also equipped with electroplated layer 321a far from the region of through-hole 13a and is located at electricity
External pin 121a below coating 321a.
Here, metal column 311a is copper post 311a, and electroplated layer 321a is layers of copper 321a, and but not limited to this.
Scolding tin 331a is coated on the outside of copper post 311a, and the one end of scolding tin 331a far from copper post 311a be located on substrate
The layers of copper 321a of surface 11a be combined with each other, so as to conduction electrode 221a and external pin 121a.
The advantage that copper post 311a and scolding tin 331a is arranged is: (1) scolding tin 331a is molten condition in reflow soldering process,
Convenient in conjunction with copper post 311a, and combine effect preferable；(2) contact area between scolding tin 331a and layers of copper 321a is big, can be with
Electrical transmission performance is improved, strong degree of the scolding tin 331a in conjunction with layers of copper 321a also can be improved；(3) copper post 311a already takes up
A part of space can reduce the raw material usage amount of scolding tin 331a when scolding tin 331a is arranged in through-hole 13a at this time, reduce
The welding procedure difficulty of scolding tin 331a, shortens weld interval, and then improves welding production capacity；(4) copper post 311a appearance is significant,
Identification part be can be used as to improve recognition efficiency, and then convenient for the detection of automatic aspect and possible defect recognition.
In the present embodiment, layers of copper 321a includes connected positioned at the first layers of copper 3211a of upper surface of base plate 11a, position
The second layers of copper 3212a in through-hole 13a inner wall and third layers of copper 3213a, scolding tin 331a the cladding gold positioned at base lower surface 12a
Belong to column 311a and is connected with the first layers of copper 3211a, third layers of copper 3213a connection external pin.
The width that the first layers of copper 3211a of connection scolding tin 331a extends to upper surface of base plate 11a is greater than corresponding third electricity
Coating 3213a extends to the width of base lower surface 12a.
Here, on the one hand, upper surface of base plate 11a and base lower surface 12a are provided with layers of copper 321a, and layers of copper can be improved
Strong degree of the 321a in conjunction with package substrate 10a；On the other hand, the first layers of copper 3211a extends towards the direction electrode 221a, is convenient for
Scolding tin 331a connection the first layers of copper 3211a, and since scolding tin 331a at this time does not enter through-hole 13a, through-hole 13a can be towards outside two sides
It moves, so that the external pin 121a of base lower surface 12a can be moved in addition.
In addition, the first layers of copper 3211a partly overlaps (i.e. the first cofferdam at this time close to the region of cavity S and the first cofferdam 41a
The section of 41a is L-shaped), meanwhile, the first layers of copper 3211a is formed with the second cofferdam 42a close to the overlying regions of through-hole 13a.
Copper post 311a is laid in the intermediate region of electrode 221a, scolding tin 331a encirclement copper post 311a and scolding tin 331a and cofferdam
There is gap between 40a, since the two sides of scolding tin 331a at this time are surrounded by the first cofferdam 41a and the second cofferdam 42a, plastic packaging layer
50a does not enter in the gap.
An embodiment of the present invention also provides a kind of production method of encapsulating structure, in conjunction with saying for aforementioned encapsulation structure 100a
Bright and Fig. 7, Fig. 8 a to Fig. 8 s, production method comprising steps of
S1: ginseng Fig. 8 a provides filter chip 20a, has the chip upper surface 21a being oppositely arranged and chip lower surface
22a, chip lower surface 22a have several electrode 221a；
S2: ginseng Fig. 8 b to Fig. 8 e forms metal column 311a in the lower surface of electrode 221a；
It specifically includes:
Join Fig. 8 b, forms the first photoresist film 70a in chip lower surface 22a；
Join Fig. 8 c, forms several first hole 71a, the first hole 71a exposure in the first photoresist film 70a exposure and imaging
Electrode 221a out；
Join Fig. 8 d, in forming several copper post 311a in several first hole 71a；
Join Fig. 8 e, removes the first photoresist film 70a.
S3: ginseng Fig. 8 f provides package substrate 10a, has the upper surface of base plate 11a and base lower surface being oppositely arranged
11b；
S4: ginseng Fig. 8 g, in forming several through-hole 13a on package substrate 10a；
S5: ginseng Fig. 8 h to Fig. 8 k in through-hole 13a inner wall and connects under the upper surface of base plate 11a of through-hole 13a inner wall, substrate
Surface 12a forms electroplated layer 321a；
It specifically includes:
Join Fig. 8 h, is respectively formed the second photoresist film 90a and third light in upper surface of base plate 11a and base lower surface 12a
Photoresist film 93a；
Join Fig. 8 i, forms the second hole 91a, the second hole 91a in the second photoresist film 90a exposure and imaging and expose logical
Hole 13a and upper surface of base plate 11a forms third hole 94a in third photoresist film 93a exposure and imaging, and third hole 93a is sudden and violent
Expose through-hole 13a and base lower surface 12a；
Join Fig. 8 j, forms the first layers of copper 3211a in being exposed to outer upper surface of base plate 11a, the through-hole 13a outside being exposed to
Inner wall forms the second layers of copper 3212a, forms third layers of copper 3213a in being exposed to outer base lower surface 12a；
Join Fig. 8 k, removes the second photoresist film 90a and third photoresist film 93a.
S6: ginseng Fig. 8 l and Fig. 8 m, cofferdam 40a is formed in upper surface of base plate 11a, cofferdam 40a includes the first cofferdam 41a and the
Two cofferdam 42a；
It specifically includes:
Join Fig. 8 l, lays photaesthesia insulating film 80a in upper surface of base plate 11a；
Join Fig. 8 m, exposure and imaging forms cofferdam 40a, and cofferdam 40a includes the first cofferdam on the inside of several through-hole 13a
41a and the second cofferdam 42a, the first cofferdam 41a partly overlap with the first layers of copper 3211a close to the region of cavity S, the second cofferdam
42a is located at the first layers of copper 3211a close to the top in the region of through-hole 13a；
It should be noted that being formed since independent package substrate 10a can be divided by the large substrates of wafer scale, molding is enclosed
When the 40a of weir, can on large substrates the multiple cofferdam 40a of straight forming, then carry out the segmentation of large substrates again and obtain having single
The single package substrate 10a of a cofferdam 40a, in this way, being greatly improved packaging efficiency, certainly, cofferdam 40a is also plastic to be filtered
On device chip 20a.
S7: ginseng Fig. 8 n, in point scolding tin 331a on the electroplated layer 321a between the first cofferdam 41a and the second cofferdam 42a；
It specifically includes:
Join Fig. 8 n, in point scolding tin 331a on the first layers of copper 3211a being located among the first cofferdam 41a and the second cofferdam 42a.
Filter chip 20a is assembled to package substrate 10a, chip lower surface 22a and upper surface of base plate by S8: ginseng Fig. 8 o
11a is arranged face-to-face, and the first cofferdam 41a is located at the inside of several electrode 221a, and the second cofferdam 42a is located at several electrode 221a's
Outside, and the first cofferdam 41a and chip lower surface 22a and upper surface of base plate 11a cooperates and encloses to set to form cavity S, scolding tin 331a
Metal column 311a and electroplated layer 321a is connected；
After the step further include:
Join Fig. 8 p, forms plastic packaging layer 50a far from the side of the lower surface substrate 10a in package substrate 10a, plastic packaging layer 50a is same
When coat the region and filter chip 20a that the second cofferdam 42a is exposed, and plastic packaging layer 50a fills through-hole 13a.
S9: ginseng Fig. 8 q to Fig. 8 s forms external pin 121a below electroplated layer 321a.
It specifically includes:
Join Fig. 8 q, in base lower surface 12a formed soldermask layer 60a, soldermask layer 60a coat simultaneously base lower surface 12a and
Third layers of copper 3213a；
Join Fig. 8 r, forms several 4th hole 61a in soldermask layer 60a exposure and imaging, the 4th hole 61a exposes third
Layers of copper 3213a；
Join Fig. 8 s, in formation ball grid array 121a in several 4th hole 61a.
Other explanations of the production method of the encapsulating structure of present embodiment can saying with reference to above-mentioned encapsulating structure 100a
Bright, details are not described herein.
Cofferdam 40 (and 40a, 40b) of the invention is located at the inside and outside of electrode 221, and the outside in the second cofferdam 42
Edge is located between the lateral border of filter chip 20 and the lateral border of package substrate 10a, in other embodiments, cofferdam 40
The inside of electrode 221 can be located at, alternatively, the lateral border in the second cofferdam 42 can be flushed with the lateral border of package substrate 10, and or
Person is the lateral border in the second cofferdam 42 is flushed with the lateral border of filter chip 20 etc..
To sum up, present embodiment forms cavity S by setting cofferdam 40, it is possible to prevente effectively from encapsulating structure manufacturing process
In or external substance enters the normal use for inside cavity S and influencing filter chip 20 in encapsulating structure use process,
To improve the overall performance of encapsulating structure 100；In addition, there are many forms for the interconnection structure 30 of present embodiment, it can be effective
Electrical transmission performance is improved, the stability of entire encapsulating structure 100 can also be effectively improved.
It should be appreciated that although this specification is described in terms of embodiments, but not each embodiment only includes one
A independent technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should will say
As a whole, the technical solution in each embodiment may also be suitably combined to form those skilled in the art can for bright book
With the other embodiments of understanding.
The series of detailed descriptions listed above only for feasible embodiment of the invention specifically
Protection scope bright, that they are not intended to limit the invention, it is all without departing from equivalent implementations made by technical spirit of the present invention
Or change should all be included in the protection scope of the present invention.
Claims (10)
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Effective date of registration: 20200616 Address after: 313200 No. 926 Changhong East Street, Fuxi Street, Deqing County, Huzhou City, Zhejiang Province (Mogan Mountain National High-tech Zone) Applicant after: Zhejiang Rongcheng Semiconductor Co.,Ltd. Address before: 215123 Jiangsu city Suzhou Industrial Park 99 Jinji Hu Road 99 Suzhou Nancheng NW-05 building 301 Applicant before: Fu Wei |
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