CN109063323A - A kind of generation method of random test use-case that verifying SDRAM - Google Patents
A kind of generation method of random test use-case that verifying SDRAM Download PDFInfo
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Abstract
The invention discloses a kind of generation methods of random test use-case for verifying SDRAM, using the characteristic parameter and verifying demand for being verified SDRAM as Program Generating entrance restrictive condition, the combination producing random test program method of constraint diagram limitation instruction is jumped according to the state machine of SDRAM, the validity and high efficiency that ensure that test and verify program are of great significance to SDRAM test coverage is improved；Method of the invention is using single instrction template library and fixed instruction combinatorial libraries as the basis for generating test program, after the technology upgrading for being verified object SDRAM is regenerated, as long as being updated to instruction database, restriction on the parameters, which is carried out, according to the SDRAM being verified just is suitable for new test verifying demand, it is applied widely without carrying out a large amount of database update maintenance.
Description
Technical field
The invention belongs to reservoir designs to analyze verification technique field, be related to a kind of random test use-case for verifying SDRAM
Generation method.
Background technique
Synchronous DRAM (Synchronous Dynamic Random Access Memory, referred to as
SDRAM) there is the advantage that access speed is fast, storage density is high, unit storage unit is at low cost, be widely used in the master of computer
It deposits.The rapid development of SDRAM technology, has developed to DDR4 and DDR5 via DDR, DDR2, DDR3 via the SDR of the first generation.Mesh
Before, DDR3 has been widely used in all kinds of computers, and DDR4 product has been introduced to the market, and memory manufacturer has started to carry out DDR5
The exploitation of product.Formulation of the JEDEC to every generation SDRAM product standard plays important function for SDRAM successful application, into
Row SDRAM design analysis, verifying will follow the SDRAM standard of JEDEC formulation.
It is divided by built-in function, the structure of SDRAM mainly by address control, logic control, Data Transmission Controlling and is deposited
Store up the big funtion part of array four composition.In addition to the continuous diminution of process, single metal-oxide-semiconductor and data storage capacity are as SDRAM
Cells of memory arrays structure do not change；Other three funtion parts are then as the update of SDRAM technology is constantly updated
Variation.Complete " 0 " developed for the different faults model such as address, data adhesion, solid " 0 ", solid " 1 " entirely " 1 ", in step, walking,
The test cases such as leapfrog cannot meet address control, logic control and Data Transmission Controlling this three parts designing technique and constantly send out
The verifying requirement of exhibition, it is difficult to take into account demand of both the fault coverage of design analysis verifying and the execution efficiency of test.For
Guarantee that fault coverage needs to run a large amount of routine test use-case and carries out design analysis simulating, verifying and flow before flow
Functional test afterwards, expend flood tide server replicating machine when and when ATE test machine, design analysis simulating, verifying and test have become
The bottleneck of SDRAM technology development.How to solve traditional SDRAM verification test cases fault coverage and execution efficiency it is low lack
It is sunken, the fault coverage and testing efficiency of analysis verifying are improved, development cost is reduced, is that current SDRAM product test is verified urgently
Problem to be solved.
Summary of the invention
It is an object of the invention to overcome the fault coverage and testing efficiency of above-mentioned analysis verifying of the existing technology
Low defect provides a kind of generation method of random test use-case for verifying SDRAM.
Aiming at the problems existing in the prior art, the present invention provides a kind of random test use-case generation side for verifying SDRAM
Method.
In order to achieve the above objectives, the present invention is achieved by the following scheme:
A kind of generation method of random test use-case that verifying SDRAM, comprising the following steps:
Step 1: establishing SDRAM operational order template, operational order is divided into single instrction and fixed Combination instructs, generate single
Instruction database and fixed instruction combinatorial libraries, for the random call of instruction, to construct test command combination producing test program；
Step 2: the characteristic parameter for being verified SDRAM is extracted, the clock cycle interval between random combine to limit order,
It avoids generating exceeded test and verify program, so that the clock cycle interval between operational order sequence is met SDRAM working index and want
It asks；
Step 3: setting is verified the permission operating mode of SDRAM, to determine the working condition of SDRAM；The mode of determination is posted
The operand of storage and extended mode register operational order traverses range, carries out to the relevant parameter area of logical function verification
Setting；
Step 4: emphasis covering function module being wanted according to verifying, to random test program additional restrictions are generated, to mention
Height generates the execution efficiency of test program；
Step 5: according to the restrictive condition of aforementioned 4 steps, test instruction being synthesized；According to the instruction pair of generation
The state of SRRAM is updated, and the legitimacy for carrying out stochastic instruction combined sequence filters selection, filters out illegal instruction sequence, raw
At effective test program；Guiding performance limitation is carried out to stochastic instruction combined sequence, guarantees the high efficiency of test program, improve with
The quality of machine test program.
Compared with prior art, the invention has the following advantages:
Legal single instrction template library and fixed Combination instruction database are established the present invention provides a kind of, to be verified SDRAM's
Characteristic parameter and verifying demand are Program Generating entrance restrictive condition, jump constraint diagram limitation instruction according to the state machine of SDRAM
Combination producing random test program method, ensure that the validity and high efficiency of test and verify program, to improve SDRAM test
Coverage rate is of great significance；
Compared with traditional method of generating test program, the present invention solves fixed algorithm generation SDRAM test program and refers to
Combined sequence is enabled to fix, it is difficult to traverse the operational order combination technique problem allowed in SDRAM State Machine；
The present invention can be according to the specific design conditions and test verifying purpose limitation rank addresses range of SDRAM and effectively finger
Combination is enabled, is realized to the emphasis module of SDRAM or the verifying of block combiner, the specific aim for generating random test program is improved, it is raw
At test program can take into account between test coverage and testing efficiency of both demand；
Method of the invention is using single instrction template library and fixed instruction combinatorial libraries as the basis for generating test program, in quilt
After the technology upgrading of identifying object SDRAM is regenerated, as long as being updated to instruction database, parameter is carried out according to the SDRAM being verified
Constraint is just suitable for new test verifying demand, applied widely without carrying out a large amount of database update maintenance.
Detailed description of the invention
Fig. 1 is the general frame that SDRAM random test use-case of the present invention generates；
Fig. 2 is the main program flow chart for generating random test use-case.
Specific embodiment
The invention will be described in further detail with reference to the accompanying drawing:
Referring to Fig. 1 and 2, the present invention verifies the generation method of the random test use-case of SDRAM, comprising the following steps:
(1) SDRAM operational order template is established, operational order is divided into single instrction and fixed Combination instructs, generation singly refers to
Library and fixed instruction combinatorial libraries are enabled, for the random call of instruction, to construct test command combination producing test program.
The step (1) carries out as follows:
(1.1) using the command truth table being verified in SDRAM databook as foundation, with TCL (Test Command
Language) language establishes all operational order templates of SDRAM permission；
(1.2) single instrction template is divided into two classes；According to the state machine transition diagram of SDRAM, will independently execute just changeable
The instruction template of SDRAM state forms independent operation instruction database；It must be combined by permanent order and operation is carried out just to SDRAM
Demand model with practical significance combines in a fixed order, constitutes fixed Combination operational order library.
(2) it is verified the characteristic parameter extraction of SDRAM, the clock cycle interval between random combine to limit order is kept away
Exempt to generate exceeded test and verify program, the clock cycle interval between operational order sequence is made to meet the requirement of SDRAM working index.
The step (2) carries out as follows:
(2.1) for the design of same sdram memory particle, the address Bank is identical with row address, and column address sum number
It is related according to line I/O range；According to SDRAM memory array structure, the address Bank, row address, column address and data line I/O are determined
Range；
(2.2) the numeralization processing of time parameter, according to completion precharge time tRP, rank addresses latch time tRC, read
Write time tRCDEtc. the clock cycle t of absolute time parameter and SDRAMCKSize, absolute time parameter divided by the clock cycle,
In the case where capable of dividing exactly, directly take quotient as numeralization result；In the case where there is remainder, no matter the size of remainder carries out
Carry.
(3) it is verified the setting of the permission operating mode of SDRAM, to determine the working condition of SDRAM；Determine Mode register
The operand of device and extended mode register operational order traverses range, sets to the relevant parameter area of logical function verification
It is fixed.
The step (3) carries out as follows:
(3.1) mode register operand range is set: 0/1 selects read-write burst-length BL as 4 or 8,0/1 selection burst
2~9 clock cycle of data latency, 0/1 selection after type B T is serial or interval, 000~111 corresponding selection column address strobe
Digital Logic locking whether is allowed to reset；
(3.2) extended mode register operand range is set: 0/1 chooses whether enabled Digital Logic lock function, 0/1
Output data obtaining mode, 0/1 selection are defeated when selecting single-ended/differential data acquisition mode, 0/1 8 I/O data line structures of selection
Data and data acquisition function enable/not enabled, 000~111 corresponding selection column address strobe additional data waiting 2~9 out
Clock cycle.
(4) emphasis covering function module is wanted according to verifying, to random test program additional restrictions are generated, to improve life
At the execution efficiency of test program.
The step (4) carries out as follows:
(4.1) when emphasis verifying storage array, limitation or cancellation into/out low-power consumption mode relevant to logic control
The calling of order is verified the number that SDRAM enters low-power consumption mode in the user control interface input for generating program, it is subsequent
The calling into low-power consumption mode instruction is carried out according to restrictive condition when generating test program；
(4.2) all storage units of SDRAM are come, there are the physical location storage lists farthest/close away from address pins entrance
Member corresponds to address and data transfer path temporal constraint storage unit the most nervous；In the Bank that step (2.1) provide
Location, row address, column address range according to design to physical address additional limitation, for the corresponding Bank of timing anxiety unit
Location, row address, column address are activated, are written, are pre-charged, reading combined command operation, are generated single for the storage of timing anxiety
First random test program；
(4.3) for the adhesion of storage unit itself, coupling, solid " 0 ", solid " 1 " mistake, increase the back of write storage unit
Scape data format increases storage array full 0, complete 1,55 (H), AA (H) write/read back on the basis of data change at random
Scape data；
(4.4) setting generates mode register in random test program and traverses number, is verified according to traversal number change
The working condition of SDRAM carries out corresponding random test order group according to the operating mode of SDRAM mode register configuration setting
It closes, with emphasis verifying logic control function.
(5) according to the restrictive condition of aforementioned 4 steps, test instruction is synthesized；According to the instruction of generation to SRRAM
State be updated, the legitimacy for carrying out stochastic instruction combined sequence filters selection, filters out illegal instruction sequence, generates effective
Test program；Guiding performance limitation is carried out to stochastic instruction combined sequence, guarantees the high efficiency of test program, improves random test
The quality of program.
The step 5 carries out as follows:
(5.1) it determines by step 2,4 and generates random test program parameter restrictive conditions and emphasis validation test module
Range is limited, test journey is generated as instructing combination to the address range of SDRAM, data width, time cycle and additional limitation
The primary condition of sequence；
(5.2) the setting SDRAM mode register combined command in the fixed Combination instruction database called, provides in step 3
The original operating state of SDRAM is determined in parameter area, the shape is called in the selection instructed based on original operating state
Allow the single instrction library executed under state；
(5.3) limitation is oriented to the combination of instruction, is weighted instruction and calls；SDRAM is in a certain state for the first time
When, all selectable instructions or combined command sequence assign identical priority 0, single instrction of every calling or combined command
When sequence, called priority adds 1；
(5.4) SDRAM generating state after the instruction that operating is chosen jumps, and is carried out according to state machine transition diagram to SDRAM
State updates, and the operational order allowed under new state will whether there is or not quantify in step 2.2 by SDRAM state transition instruction is caused
The requirement of time, when the clock cycle interval number between the instruction chosen under new state and the instruction for entering the state is unsatisfactory for
When time parameter requires, it is inserted into non-operation instruction before the instruction of the calling under new state, is drawn with occupying the clock cycle to meet
Play the time requirement of state transition instruction operation；
(5.5) when turning again to step 5.3, in SDRAM, in the state, there is also selectable low priority levels to instruct
When, never call the high instruction of priority level；Instruction is weighted by this guiding and calls control, avoids the random test generated always
A certain instructing combination is repeated, guarantees the high efficiency of random test use-case.
(5.6) state of each permission passes through instructing combination by different combination of paths at least in SDRAM State Machine
After traversal is primary, at this time in each state there is no the combination of order when the instruction of 0 priority, can be completed, output is given birth to
At random test program.
The principle of the present invention:
As user's input control interface whether the present invention is limited using the design parameter and instruction that are verified SDRAM, establish
Operational order library constructs SDRAM operational order, testing background data and accessed storage unit by principal function method of calling
The test case of address random combine.Main program calls single instrction function or macro progress test command group according to restriction on the parameters
It closes, according to SDRAM to the execution of test case come real-time synchronization more new state.The possible operation order of same state is carried out excellent
First grade weighting processing, guarantees that test case traverses the state of SDRAM in different ways, improves the validity of test case.According to
Design certainty factor realizes the independent of tetra- composition parts of SDRAM, combination or the spy to some functional module to constraint is called
Different part carries out the functional verification and test of emphasis, improves the specific aim of validation test, effectively solves fault coverage and verifying
Contradiction between testing efficiency.
Using be verified SDRAM design parameter and verifying demand as generate random test use-case input condition, to life
At random test use-case provide of both restrict.One, user carries out parameter extraction according to the SDRAM being verified, such as
The range of the address Bank, row address and column address is determined according to the size of sdram size；According to completion precharge, rank addresses
The clock cycle size of the absolute time parameter such as latch, access time and SDRAM, is indicated exhausted with the clock cycle of numeralization
To time parameter.Referred to according to the specific address Bank, row address and column address come the correlation called when limiting Test cases technology
Enable the interval range that operating parameter changes at random；According to the numeralization of absolute time parameter come qualified call precharge, reading and writing etc.
Clock cycle interval between dependent instruction.Two, user interface function is provided, the random test use-case of generation can be carried out
Limitation is deposited including instruction type (whether excluding certain instruction), the length for generating test case, the background data of Writing/Reading, access
Storage area domain it is selected etc..According to the concrete condition that SDRAM is designed, restriction on the parameters is carried out, the harshest to SDRAM physical location
Storage unit, temporal constraint the most nervous order, address and data transfer path and design change or what's new part
Carry out emphasis verifying；Relevant instruction can then be excluded for mature inheritance design part to call, reduction generates test and uses
The length of example improves the specific aim that test case verifies different functional modules or block combiner.
The effect of operational order, so that the state of SDRAM jumps；According to operational order truth table, it is mono- to establish SDRAM
Library function is instructed, in case main program, which calls, carries out command in combination generation test case.To guarantee to generate the verifying effect of test case
Rate is instructed for only executing just efficient operation by permanent order under certain state, by single instrction library function according to fixed group
Conjunction is sequentially generated macro-instruction, and principal function carries out macro-call when needed.It avoids introducing legal but nothing in the test case of generation
The command in combination of practical significance, to guarantee to generate the validity of test case.
The most basic requirement of test case is legitimacy, and the test case of generation will meet the standard criterion of SDRAM, can
The legal execution on the SDRAM being verified.According to the restrictive condition that the SDRAM parameter area being verified and user input, main journey
Sequence carries out single instrction library function call and macro-call, carries out instructing combination and generates test case.The foundation of instructing combination is JEDEC
Defined SDRAM state transition figure.The state transition of SDRAM is realized by executing instruction, and every instruction has its phase
Associated state, the structure of test case determine the mode of SDRAM ergodic state.Test case can be real by the combination of instruction
The institute that existing different modes quickly traverse SDRAM is stateful；It to the state real-time update of SDRAM, is limited, is protected for instructing combination
Demonstrate,prove the legitimacy of test case；It realizes test case legitimacy and high efficiency, is that random test use-case generates the most key portion
Point.
Priority weighted controls the calling of operational order, when SDRAM is in a certain state for the first time, all instructions that can be executed
Or instruction sequence priority having the same, every calling single instrction library function or macro, corresponding instruction or instruction sequence
Priority adds 1.When SDRAM is in some state for the first time, the operational order of all possible operations is assigned identical under the state
Priority, priority level are 0.The instruction of principal function random call rank 0, it is 1 that the instruction being called to, which becomes priority,
Instruction；SDRAM runs the instruction of test case sequence combination, is jumped according to the instruction generating state of operation, when SDRAM is returned again
When returning to this state, in the state there is also when the low instruction of optional priority level, it is not capable of calling the high finger of priority level
It enables.By this control, avoids the random test use-case generated from repeating certain instructing combination, SDRAM is caused to enter endless loop shape
State, to guarantee the high efficiency of random test use-case.To operational order carry out priority weighted control when to non-operation instruction into
Row specially treated because SDRAM can carry out the instruction when being in any state, and executes the instruction and will not change
The state of SDRAM calls it in generating random test use-case and is intended merely to meet so non-operation instruction does not have priority
The needs of SDRAM instruction execution cycle.
Embodiment:
Being verified sdram size is 256Mb, type DDR2, structure are as follows: 16,4 bank (BA0- of 4x 4Meg x
BA1), 8K row address (A0-A12), 512 column address (A0-A8), data width 16bit (D0-D15), data rate 667MHz,
Line activating is instructed to the minimum interval t between column access instructionRCDFor 15ns, precharge time tRPFor 15ns, row access cycle
Minimum interval tRCFor 55ns.
(1) it according to the command truth table of 256M DDR2SDRAM, is built with TCL (Test Command Language) language
Vertical whole single operation instruction template；The single instrction template of 256M DDR2SDRAM has: chip is not selected, do-nothing operation, writes, read,
Band preliminary filling autotelegraph, band precharge reading, line activating, precharge, configuration mode, automatic refreshing；
| Single instrction | CKEn-1 | CKEn | /CS | /RAS | /CAS | /WE | BA0 | BA1 | A10 | Addr | D0-15 |
| Do-nothing operation | H | X | L | H | H | H | X | X | X | X | X |
| It writes | H | X | L | H | L | L | V | V | L | V | V |
| It reads | H | X | L | H | L | H | V | V | L | V | V |
| Band preliminary filling autotelegraph | H | X | L | H | L | L | V | V | H | V | V |
| Band precharge is read | H | X | L | H | L | H | V | V | H | V | V |
| Line activating | H | X | L | L | H | H | V | V | V | V | X |
| Precharge | H | X | L | L | H | L | V | V | V | V | X |
| Configuration mode | H | X | L | L | L | L | V | V | X | V | X |
| It is automatic to refresh | H | X | L | L | L | H | V | V | X | X | V |
(2) according to 256M DDR2SDRAM state machine transition diagram, all single operations in addition to configuration mode are instructed into building
For single instrction library；
(3) combination is fixed to configuration mode single instrction, according to the permanent order of register 2,3,1,0 successively to deposit
Numerical value is written in device, is inserted into non-operation instruction according to timing requirements and forms fixed instruction combinatorial libraries, to the shape of 256M DDR2SDRAM
State register is effectively configured, and operating mode is set；
(4) combined command operand OPCODE is determined2、OPCODE3、OPCODE1And OPCODE0To 256M DDR2SDRAM
It is initialized: for the SDRAM operand OPCODE of DDR2 type2、OPCODE3It is retention, OPCODE2=000 (H),
OPCODE3=000 (H), to the 0-12 one-to-one Addr0-Addr12 with extended register 1 and extended register 2
Write-in 0；OPCODE1=008 (H)；Extended register the 0th control DLL it is enabled whether, Addr0 write-in 0, enable DLL；
Addr0 write-in 1, does not enable DLL；The additional number for waiting clock cycle AL of 3rd to the 5th control selections column address strobe,
Addr3,4,5=000~100 (B) corresponding selection AL=0~4；OPCODE1=008 (H) corresponding enabled DLL, AL=1；
OPCODE0Length BL, Addr0,1 are read and write in=442 (H), 0-2 control bursts of register, and 2=010 (B) corresponds to BL=4,
Addr0,1,2=011 (B) corresponds to BL=8；Addr3=0, corresponding outburst type are sequence type, Addr3=1, corresponding burst class
Type is cabinet-type；Addr4,5,6=011 (B), corresponding CL=3, Addr4,5,6=100 (B), corresponding CL=4, Addr4,5,6
=101 (B), corresponding CL=5；Addr7=0, corresponding normal mode of operation, Addr7=1, corresponding memory enter test job
Mode；Addr8=0, corresponding DLL reset operating mode, Addr8=1, corresponding DLL normal mode of operation；Addr9,10,11=
001~101 (B) is corresponding in turn to selection 2~6 and writes the recovered clock period；Addr12 retains, write-in 0；
(5) according to 256M DDR2SDRAM structure, Bank address range: 0-3 (H), row address range: 0-1FFF is determined
(H), column address range: 0-1FF (H), data I/O:D0-D15；
(6) clock cycle t is obtained according to data rate 667MHzCKThus=3ns obtains line activating instruction to column access instruction
Between to be at least spaced 5 clock cycle, it is 5 clock cycle that precharge command, which executes the time, minimum 19 of row access interval
Clock cycle；
(7) condition limitation is carried out to the random test program of generation, inputs restrictive condition 1, the present embodiment limits 256M
DDR2SDRAM enters low power mode of operation, and not allowing CKE is low level state, CKE ≠ L；
(8) 256M DDR2SDRAM original operating state 2: normal mode of operation is determined by step (4), it is multiple without DLL
Position, without 200 clock cycle for waiting DLL stable are inserted into after this instruction, writing the recovered clock period is 5, at n-th
The rising edge of clock latched reading instruction, start continuously to export 4 16 data, each data in the n-th+AL+CL clock cycle
Each bit width it is identical as clock half cycle；
(9) whether process 3, which allows write/read operation to judge, is carried out to 256M DDR2SDRAM original operating state, at this time
256Mb DDR2SDRAM does not carry out activation operation, is in Idle state, does not allow to carry out write/read operation；
(10) it by N branch, carries out instructing selection with prioritized operation under idle state and call into process 4；For the first time
When into the idle state, it is 0 that optional instruction, which has three kinds of activation operation, automatic refresh operation, do-nothing operation priority,；Same
It is random one selected under state when instruction identical there are multiple lowest priorities；
(12) enter process 5, priority is carried out to called instruction and adds 1；
(13) enter process 6, state update is carried out to 256Mb DDR2SDRAM according to called instruction；
(14) enter process 7, judge instruction priority level can be selected under 256Mb DDR2SDRAM new state；?
Each state traversal is primary in state machine, after available instruction is called all in random test program, can terminate pair
The calling of instruction terminates 13 into process, exports random test program；
The concrete condition that step (11) to step (14) are executed after calling to three in step (10) optional instructions is further
It elaborates:
(15) activation instruction is chosen, determines the address Bank and the row address of activation；Activation instruction priority adds 1,256Mb
DDR2SDRAM state updates, and the address Bank and row address have determined that storage unit is active；Write in active state/
Reading instruction priority is 0, into process 3, write/read operation is allowed to judge；
(16) automatic refresh operation is chosen to instruct, automatic refreshing instruction priority adds 1,256Mb DDR2SDRAM state more
Newly, it is in automatic Flushing status；It is 0 that Flushing status instruction priority is exited under automatic Flushing status, into process 3；Pass through N points
Branch, is again introduced into process 4, and only exiting Flushing status instruction can call, and after calling the instruction, state update is carried out, into sky
Not busy state still can be that 0 activation instruction is called to priority when again passing by process 4；
(17) non-operation instruction is chosen, non-operation instruction priority adds 1,256Mb DDR2SDRAM state to update, locates again
In idle state, although optional instruction has activation operation, automatic refresh operation, three kinds of do-nothing operation, priority is 0 only sharp
Work operation, two kinds of automatic refresh operation；Activation instruction is chosen just to carry out the operation of step (15)；Automatic refresh operation is chosen to carry out
Step (16) operation；
(18) activation instruction is called, if allow write/read operation process 3 to enter process 8 by Y-branch, carrying out Writing/Reading is
No judgement at the same level；
(19) when write operation instruction is identical with read operation instruction priority, the progress write operation of process 9 is entered by Y-branch and is referred to
It enables and calling, write operation is carried out to the column address in the Bank activated in step (15)；Column address allowed band 0-1FF (H) appoints
Meaning determines one；At this time according to verifying needs, the address for selecting the corresponding column address of critical storage unit to instruct as write operation
Operand；
(20) initialization value of the register write-in determined according to step (4), CL=4, AL=1 are writing into process 10
After WL=CL+AL-1=4 non-operation instruction of waiting is write in insertion after instruction is called, burst-length is provided for the address location of write-in
BL=4 16 random data, data persistence length are half clock cycle；
(21) enter process 5 and 1 is added to write operation instruction priority, repeat step 17-18 and be again introduced into process 8, write/
Read operation judgement whether at the same level calls read operation instruction into process 11 by N branch；The address Bank and column ground of reading instruction
Location range must be the address selection Bank of 9 write command of process and column address in step (19)；
(22) initialization value of the register write-in determined according to step (4), CL=4, AL=1 are writing into process 12
After WL=CL+AL=5 non-operation instruction of waiting is write in insertion after instruction is called, it is expected that the address location read exports step (20)
The data being written in process 10, data persistence length are half clock cycle；
(23) enter process 5, carry out read operation instruction priority and add 1；256Mb DDR2SDRAM shape is carried out into process 6
State updates, and into process 7, after all optional instructions all at least traverse once, there is no pass through N points when the instruction of 0 rank
Branch enters end 13, and generating use-case terminates, and exports random test use-case.
It also have the advantage that
The present invention solves the combination of hand-coding SDRAM test case instruction sequence and fixes, it is difficult to realize that SDRAM is system-level
Profound test verifying, according to the range for the SDRAM limitation stochastic parameter variation being verified, when Test cases technology pair
The state of SDRAM carries out real-time synchronization update, is weighted random selection to the optional instruction under same state, guarantees that test is used
Example by it is legal it is effective in a manner of traverse all working state of SDRAM, realize that the high intensity of SDRAM is surveyed in complicated order combination
Examination ensure that test verifying coverage rate.Optional instructing combination in random test use-case, realization pair are limited according to design conditions
The emphasis module of SDRAM or the verifying of block combiner improve the specific aim of random test use-case, take into account test coverage and test
Demand of both between efficiency.The generation that test case is carried out by single instrction function and macro-call mode, is being verified object
As long as being updated when variation to single instrction library function, updated without the maintenance of mass data library, convenient for application.
The above content is merely illustrative of the invention's technical idea, and this does not limit the scope of protection of the present invention, all to press
According to technical idea proposed by the present invention, any changes made on the basis of the technical scheme each falls within claims of the present invention
Protection scope within.
Claims (6)
1. a kind of generation method for the random test use-case for verifying SDRAM, which comprises the following steps:
Step 1: establishing SDRAM operational order template, operational order is divided into single instrction and fixed Combination instructs, generates single instrction
Library and fixed instruction combinatorial libraries, for the random call of instruction, to construct test command combination producing test program；
Step 2: extracting the characteristic parameter for being verified SDRAM, the clock cycle interval between random combine to limit order avoids
Exceeded test and verify program is generated, the clock cycle interval between operational order sequence is made to meet the requirement of SDRAM working index；
Step 3: setting is verified the permission operating mode of SDRAM, to determine the working condition of SDRAM；Determine mode register
Range is traversed with the operand of extended mode register operational order, the relevant parameter area of logical function verification is set
It is fixed；
Step 4: emphasis covering function module being wanted according to verifying, to random test program additional restrictions are generated, to improve life
At the execution efficiency of test program；
Step 5: according to the restrictive condition of aforementioned 4 steps, test instruction being synthesized；According to the instruction of generation to SRRAM
State be updated, the legitimacy for carrying out stochastic instruction combined sequence filters selection, filters out illegal instruction sequence, generates effective
Test program；Guiding performance limitation is carried out to stochastic instruction combined sequence, guarantees the high efficiency of test program, improves random test
The quality of program.
2. the generation method of the random test use-case of verifying SDRAM according to claim 1, which is characterized in that step 1
The specific method is as follows:
Step 1.1: using the command truth table being verified in SDRAM databook as foundation, establishing SDRAM with TCL language allows
All operational order templates；
Step 1.2: single instrction template is divided into two classes；According to the state machine transition diagram of SDRAM, will independently execute can change
The instruction template of SDRAM state forms independent operation instruction database；It must be combined by permanent order and operation is carried out just to SDRAM
Demand model with practical significance combines in a fixed order, constitutes fixed Combination operational order library.
3. the generation method of the random test use-case of verifying SDRAM according to claim 1, which is characterized in that step 2
The specific method is as follows:
Step 2.1: the design for same sdram memory particle, the address Bank is identical with row address, and column address and data
Line I/O range is related；According to SDRAM memory array structure, determine the address Bank, row address, column address and data line I/O model
It encloses；
Step 2.2: the numeralization processing of time parameter, according to completion precharge time tRP, rank addresses latch time tRC, read-write
Time tRCDEtc. the clock cycle t of absolute time parameter and SDRAMCKSize, absolute time parameter is divided by the clock cycle, in energy
In the case where enough dividing exactly, directly take quotient as numeralization result；In the case where there is remainder, and though the size of remainder carry out into
Position.
4. the generation method of the random test use-case of verifying SDRAM according to claim 1, which is characterized in that step 3
The specific method is as follows:
Step 3.1: the setting of mode register operand range:
0/1 selects to read and write burst-length BL to be 4 or 8；0/1 selects outburst type BT for serial or interval；000~111 corresponding choosing
Select 2~9 clock cycle of data latency after column address strobe；0/1 chooses whether that Digital Logic is allowed to lock reset；
Step 3.2: the setting of extended mode register operand range:
0/1 chooses whether enabled Digital Logic lock function；0/1 selects single-ended/differential data acquisition mode；0/1 8 I/ of selection
Output data obtaining mode when O data cable architecture；0/1 selection output data and data acquisition function enable/do not enable；000~
111 corresponding selection column address strobe additional datas wait 2~9 clock cycle.
5. the generation method of the random test use-case of verifying SDRAM according to claim 3, which is characterized in that step 4
The specific method is as follows:
Step 4.1: when emphasis verifies storage array, limitation or cancellation into/out low-power consumption mode relevant to logic control
The calling of order is verified the number that SDRAM enters low-power consumption mode in the user control interface input for generating program, it is subsequent
The calling into low-power consumption mode instruction is carried out according to restrictive condition when generating test program；
Step 4.2: all storage units of SDRAM being come, there are the physical location storage lists farthest/close away from address pins entrance
Member corresponds to address and data transfer path temporal constraint storage unit the most nervous；In the Bank that step 2.1 provides
Location, row address, column address range according to design to physical address additional limitation, for the corresponding Bank of timing anxiety unit
Location, row address, column address are activated, are written, are pre-charged, reading combined command operation, are generated single for the storage of timing anxiety
First random test program；
Step 4.3: for the adhesion of storage unit itself, coupling, solid " 0 ", solid " 1 " mistake, increasing the back of write storage unit
Scape data format increases storage array full 0, complete 1,55 (H), AA (H) write/read back on the basis of data change at random
Scape data；
Step 4.4: setting generates mode register in random test program and traverses number, is verified according to traversal number change
The working condition of SDRAM carries out corresponding random test order group according to the operating mode of SDRAM mode register configuration setting
It closes, with emphasis verifying logic control function.
6. verifying the generation method of the random test use-case of SDRAM according to claim 3 or 5, which is characterized in that step
5 the specific method is as follows:
Step 5.1: being determined by step 2 and step 4 and generate random test program parameter restrictive condition and emphasis validation test mould
The limitation range of block generates the address range of SDRAM, data width, time cycle and additional limitation as instructing combination and surveys
Try the primary condition of program；
Step 5.2: the setting SDRAM mode register combined command in the fixed Combination instruction database of calling provides ginseng in step 3
The original operating state of SDRAM is determined in number range, the state is called in the selection instructed based on original operating state
The lower single instrction library for allowing to execute；
Step 5.3: limitation being oriented to the combination of instruction, instruction is weighted and calls；SDRAM is in a certain state for the first time
When, all selectable instructions or combined command sequence assign identical priority 0, single instrction of every calling or combined command
When sequence, called priority adds 1；
Step 5.4:SDRAM generating state after the instruction that operating is chosen jumps, and carries out shape to SDRAM according to state machine transition diagram
State updates, the operational order allowed under new state will by cause the instruction of SDRAM state transition whether there is or not quantify in step 2.2 when
Between requirement, when chosen under new state instruction and enter the state instruction between clock cycle interval number be unsatisfactory for when
Between parameter request when, be inserted into non-operation instruction before the instruction of the calling under new state, caused with occupying the clock cycle to meet
The time requirement of state transition instruction operation；
Step 5.5: when turning again to step 5.3, in SDRAM, in the state, there is also selectable low priority levels to instruct
When, never call the high instruction of priority level；Instruction is weighted by this guiding and calls control, avoids the random test generated always
A certain instructing combination is repeated, guarantees the high efficiency of random test use-case；
Step 5.6: the state of each permission passes through instructing combination by different combination of paths at least time in SDRAM State Machine
Go through it is primary after, at this time in each state there is no when the instruction of 0 priority, that is, complete the combination of order, export generation
Random test program.
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111045880A (en) * | 2019-12-17 | 2020-04-21 | 湖南长城银河科技有限公司 | Chip testing method, verification system and storage medium |
| CN111506345A (en) * | 2020-06-29 | 2020-08-07 | 深圳市芯天下技术有限公司 | Non-flash memory instruction combination verification method, system, storage medium and terminal |
| CN112256572A (en) * | 2020-10-21 | 2021-01-22 | 海光信息技术股份有限公司 | Random test case generation method and device, electronic equipment and storage medium |
| CN112365917A (en) * | 2020-12-04 | 2021-02-12 | 深圳市芯天下技术有限公司 | Nonvolatile memory instruction combination verification method and device, storage medium and terminal |
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| US12040030B2 (en) | 2022-03-31 | 2024-07-16 | Changxin Memory Technologies, Inc. | Method and device for generating command sequence, method and device for testing, and storage medium |
| CN118642762A (en) * | 2024-08-14 | 2024-09-13 | 北京开源芯片研究院 | Instruction processing method, device, electronic device and readable storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1684047A (en) * | 2004-12-24 | 2005-10-19 | 清华大学 | A Verification Method Based on Boundary Conditions and Self-checking Random Test for CPU Constraint Generation |
| US20060179369A1 (en) * | 2005-02-10 | 2006-08-10 | International Business Machines Corporation | Memory built-in self test engine apparatus and method with trigger on failure and multiple patterns per load capability |
| CN101673236A (en) * | 2009-10-13 | 2010-03-17 | 中国人民解放军国防科学技术大学 | Full-covered automatic generating method of test case package of microprocessor |
-
2018
- 2018-07-28 CN CN201810849996.1A patent/CN109063323B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1684047A (en) * | 2004-12-24 | 2005-10-19 | 清华大学 | A Verification Method Based on Boundary Conditions and Self-checking Random Test for CPU Constraint Generation |
| US20060179369A1 (en) * | 2005-02-10 | 2006-08-10 | International Business Machines Corporation | Memory built-in self test engine apparatus and method with trigger on failure and multiple patterns per load capability |
| CN101673236A (en) * | 2009-10-13 | 2010-03-17 | 中国人民解放军国防科学技术大学 | Full-covered automatic generating method of test case package of microprocessor |
Non-Patent Citations (1)
| Title |
|---|
| 于伽等: "随机测试程序发生器的设计与实现", 《微电子学与计算机》 * |
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| CN112365917A (en) * | 2020-12-04 | 2021-02-12 | 深圳市芯天下技术有限公司 | Nonvolatile memory instruction combination verification method and device, storage medium and terminal |
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