CN109037350A - Thin film transistor (TFT) and preparation method thereof, array substrate - Google Patents

Abstract

The invention provides a thin film transistor, a preparation method thereof, and an array substrate. The thin film transistor includes a substrate, a gate, a gate insulating layer, a first metal layer, an active layer, a second metal layer, a passivation layer, and a gate Provided on the substrate, the gate insulating layer covers the gate, the first metal layer includes a first electrode and a second electrode arranged at intervals on the gate insulating layer, and the second metal layer includes a source electrode and a drain electrode arranged at intervals, One end of the active layer is sandwiched between the first electrode and the source, the other end of the active layer is sandwiched between the second electrode and the drain, and the passivation layer covers the source, the drain, and the exposed active layer The contact performance between the active layer and the second metal layer is improved by sandwiching the active layer between the first metal layer and the second metal layer. In the preparation method of the present invention, the first metal layer and the second metal layer are formed through two patterning processes, thereby avoiding chamfering.

Description

Thin film transistor and its preparation method, array substrate

technical field

The present invention relates to the technical field of array substrate manufacturing, in particular to a thin film transistor, a preparation method thereof, and an array substrate.

Background technique

Thin-film-transistor active-matrix liquid crystal display (TFTAMLCD) has become the leading technology and research and development hotspot in the field of information display because of its high information content, multi-gray scale and ability to realize color video display. With the development of TFTAMLCD to large area and high definition, the requirements for metal electrode materials are getting higher and higher. On the one hand, the resistance of the metal electrode is required to be low to reduce image distortion caused by signal delay; on the other hand, the thermal stability and adhesion of the metal film are better. Therefore, the preparation of metal thin films and circuits with low resistivity, good thermal stability and adhesion has become the focus of research and development.

In the existing TFT, in order to improve the contact performance of the TFT electrode, the TFT electrode usually adopts a multi-layer metal structure, as shown in Figure 1, wherein the TFT electrode includes a first metal layer 4 and a second metal layer 6, the first metal layer Layer 4 is in contact with active layer 5 . In the existing TFT manufacturing process, the first metal material layer and the second metal material layer with good adhesion are deposited on the active layer 5, and then etched by a photolithography process. The different metals are in the same etching solution and mutually Contacting or passing through other conductors, due to the different corrosion potentials, will cause localized corrosion of the contact parts of the first metal material layer and the second metal material layer, that is, galvanic corrosion (galvanic corrosion), and chamfering will appear, as shown in Figure 1 As shown in the dotted line box, the occurrence of chamfered corners is likely to cause abnormalities such as subsequent passivation film faults and TFT electrical instability, and even reduce product yield.

Contents of the invention

In order to solve the above problems, the present invention provides a thin film transistor and its preparation method, and an array substrate, which can improve the contact performance between the active layer and the second metal layer, avoid chamfering, and improve the electrical performance of the thin film transistor.

The specific technical solution proposed by the present invention is to provide a thin film transistor, which includes a substrate, a gate, a gate insulating layer, a first metal layer, an active layer, a second metal layer, and a passivation layer. The gate is disposed on the substrate, the gate insulating layer covers the gate, the first metal layer includes a first electrode and a second electrode disposed on the gate insulating layer at intervals, and the second The metal layer includes a source electrode and a drain electrode arranged at intervals, one end of the active layer is interposed between the first electrode and the source electrode, and the other end of the active layer is interposed between the second electrode and the second electrode. Between the electrode and the drain, the passivation layer covers the exposed surfaces of the source, the drain, and the active layer.

Further, the source is in contact with the first electrode, and the drain is in contact with the second electrode.

Further, the adhesion between the first metal layer and the gate insulating layer is greater than the adhesion between the second metal layer and the gate insulating layer.

Further, the material of the second metal layer is copper.

Further, the material of the first metal layer is selected from one of molybdenum, chromium and titanium.

The present invention also provides an array substrate, and the array substrate includes any one of the above thin film transistors.

The present invention also provides a preparation method of a thin film transistor, the preparation method comprising the steps of:

providing a substrate;

forming a gate and a gate insulating layer on the substrate, the gate insulating layer covering the gate;

forming a first metal layer on the gate insulating layer, the first metal layer including a first electrode and a second electrode disposed on the gate insulating layer at intervals;

An active layer and a second metal layer are formed on the first metal layer, the second metal layer includes a source electrode and a drain electrode arranged at intervals, and one end of the active layer is sandwiched between the first electrode and the drain electrode. Between the source electrodes, the other end of the active layer is interposed between the second electrode and the drain electrode;

A passivation layer is deposited, and the passivation layer covers the exposed surfaces of the source electrode, the drain electrode and the active layer.

Further, forming the active layer and the second metal layer on the first metal layer specifically includes:

depositing an active material layer on the first metal layer;

Coating a third photoresist layer on the active material layer, exposing the third photoresist layer through a third photomask, patterning the third photoresist layer, and forming a third photoresist region;

The active material layer not covered by the third photoresist region is removed by an etching process to form an active layer, one end of the active layer is in contact with the first electrode and covers part of the first electrode, the active layer is The other end of the source layer is in contact with the second electrode and covers part of the second electrode;

depositing a second metal material layer on the gate insulating layer, the first electrode, the second electrode and the active layer;

A fourth photoresist layer is coated on the second metal material layer, and the fourth photoresist layer is exposed through a fourth photomask to pattern the fourth photoresist layer to form fourth photoresist layers spaced apart from each other. photoresist area;

The second metal material layer not covered by the fourth photoresist region is removed by an etching process to form a second metal layer, the second metal layer includes a source electrode and a drain electrode arranged at intervals, and the active layer One end is interposed between the first electrode and the source, the other end of the active layer is interposed between the second electrode and the drain, and the source and the first The drain electrode is in contact with the second electrode.

Further, forming an active layer and a second metal layer on the first metal layer includes:

depositing an active material layer on the first metal layer;

depositing a second metal material layer on the active material layer;

A third photoresist layer is coated on the second metal material layer, and the third photoresist layer is subjected to grayscale exposure through a third photomask to pattern the third photoresist layer to form a third photoresist layer. a resisting area, the third photoresisting area includes a middle part and side parts located on both sides of the middle part, the thickness of the middle part is smaller than the thickness of the side parts;

The active material layer and the second metal material layer not covered by the third photoresist region are removed by an etching process to form an active layer, one end of the active layer is in contact with the first electrode, and the active layer is in contact with the first electrode. The other end of the source layer is in contact with the second electrode;

Performing ashing treatment on the third photoresist region to remove the middle part and reduce the thickness of the side part, and retain part of the side part;

The second metal material layer not covered by the part of the side is removed by an etching process to form a second metal layer, the second metal layer includes a source electrode and a drain electrode arranged at intervals, and one end of the active layer is clamped It is disposed between the first electrode and the source, and the other end of the active layer is sandwiched between the second electrode and the drain.

The thin film transistor proposed by the present invention includes an active layer, a source electrode, a drain electrode, and a first electrode and a second electrode arranged at intervals, and one end of the active layer is sandwiched between the first electrode and the source electrode , the other end of the active layer is sandwiched between the second electrode and the drain, and the active layer is raised by sandwiching the active layer between the first metal layer and the second metal layer. Contact performance with the second metal layer. In the preparation method of the present invention, the first metal layer and the second metal layer are formed through two patterning processes, thereby avoiding chamfering and improving the electrical performance of the thin film transistor.

Description of drawings

The technical solutions and other beneficial effects of the present invention will be apparent through the detailed description of specific embodiments of the present invention in conjunction with the accompanying drawings.

FIG. 1 is a structural schematic diagram of chamfered corners during the preparation process of an existing thin film transistor;

2 is a schematic structural diagram of an array substrate in Embodiment 1 of the present invention;

3a-3f are the flow charts of the preparation method of the thin film transistor in Example 1;

4a-4e are the flow charts for the preparation of the gate and gate insulating layer in Example 1;

5a to 5d are the flow charts for the preparation of the first metal layer in Example 1;

6a to 6d are the flow charts for the preparation of the active layer in Example 1;

7a to 7d are the flow charts for the preparation of the second metal layer in Example 1;

8 is a schematic structural diagram of an array substrate in Embodiment 2 of the present invention;

9a to 9j are flow charts of the manufacturing method of the thin film transistor in the second embodiment.

Detailed ways

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. Rather, the embodiments are provided to explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to particular intended uses. In the drawings, the same reference numerals will be used to denote the same elements throughout.

The invention provides a thin film transistor, which includes a substrate, a gate, a gate insulating layer, a first metal layer, an active layer, a second metal layer, and a passivation layer, and the gate is arranged on the substrate, The gate insulating layer covers the gate, the first metal layer includes a first electrode and a second electrode arranged at intervals on the gate insulating layer, the second metal layer includes a source electrode and a drain electrode arranged at intervals, and one end of the active layer is sandwiched between Between the first electrode and the source electrode, the other end of the active layer is sandwiched between the second electrode and the drain electrode, and the passivation layer covers the exposed surfaces of the source electrode, the drain electrode and the active layer.

The present invention also provides a preparation method of a thin film transistor, the preparation method comprising the following steps:

providing a substrate;

forming a gate and a gate insulating layer on the substrate, and the gate insulating layer covers the gate;

forming a first metal layer on the gate insulating layer, the first metal layer including a first electrode and a second electrode disposed on the gate insulating layer at intervals;

An active layer and a second metal layer are formed on the first metal layer, the second metal layer includes a source electrode and a drain electrode arranged at intervals, one end of the active layer is sandwiched between the first electrode and the source electrode, and the active layer The other end of is sandwiched between the second electrode and the drain;

A passivation layer is deposited, and the passivation layer covers the exposed surfaces of the source electrode, the drain electrode, and the active layer.

The thin film transistor proposed by the present invention includes an active layer, a source electrode, a drain electrode, and a first electrode and a second electrode arranged at intervals, and one end of the active layer is sandwiched between the first electrode and the source electrode , the other end of the active layer is sandwiched between the second electrode and the drain, and the active layer is raised by sandwiching the active layer between the first metal layer and the second metal layer. Contact performance with the second metal layer. In the preparation method of the present invention, the first metal layer and the second metal layer are formed through two patterning processes, thereby avoiding the occurrence of chamfered corners through one patterning process, and improving the electrical performance of the thin film transistor.

The structure and preparation method of the thin film transistor of the present invention will be described in detail below through two specific examples.

Example 1

Referring to FIG. 2, the array substrate in this embodiment includes a plurality of thin film transistors 10, and the plurality of thin film transistors are arranged in an array. The thin film transistor 10 includes a substrate 1 , a gate 2 , a gate insulating layer 3 , a first metal layer 4 , an active layer 5 , a second metal layer 6 , and a passivation layer 7 . The gate 2 is arranged on the substrate 1, the gate insulating layer 3 covers the gate 2, the first metal layer 4 includes a first electrode 41 and a second electrode 42 arranged at intervals on the gate insulating layer 3, and the second metal layer 6 includes The source electrode 61 and the drain electrode 62 arranged at intervals, the source electrode 61 is located on the first electrode 41 and is in contact with the first electrode 41, the drain electrode 62 is located on the second electrode 42 and is in contact with the second electrode 42, and the active layer 5 includes The source contact end 51, the back channel portion 52, and the drain contact end 53, the source contact end 51 is sandwiched between the first electrode 41 and the source electrode 61 and covers part of the first electrode 41, and the drain contact end 53 is sandwiched Set between the second electrode 42 and the drain 62 and cover part of the second electrode 42, the back channel portion 52 is located between the first electrode 41 and the second electrode 42 and corresponds to the gate 2, and the passivation layer 7 covers the The source electrode 61 , the drain electrode 62 , and the exposed surface of the active layer 5 .

In this embodiment, the adhesion between the first electrode 41 and the second electrode 42 and the gate insulation layer 3 is greater than the adhesion between the source electrode 61 and the drain electrode 62 and the gate insulation layer 3 . The material of the gate insulating layer 3 is an insulating material. Preferably, the material of the second metal layer 6 is copper. Since copper has excellent properties such as low impedance and high conductivity, it has become a mainstream electrode conductive metal material. However, copper and gate The adhesion between the insulating layers is poor, therefore, the first metal layer 4 is arranged between the second metal layer 6 and the gate insulating layer 3, the second metal layer 6 is in contact with the first metal layer 4, and the first metal layer 4 The material is selected from one of molybdenum, chromium, and titanium, and the first metal layer 4 and the gate insulating layer 3 have good adhesion, thereby reducing the resistivity of the metal electrode while improving the thermal stability of the metal electrode and adhesion. Wherein, the metal electrode in this embodiment refers to the source electrode 61 or the drain electrode 62 .

In this embodiment, the source contact terminal 51 is provided between the first electrode 41 and the source electrode 61, and the drain contact terminal 53 is provided between the second electrode 42 and the drain electrode 62. By sandwiching the active layer 5 Between the first metal layer 4 and the second metal layer 6 , the contact performance between the active layer 5 and the second metal layer 6 is improved.

The array substrate in this embodiment further includes a pixel electrode 8, and the pixel electrode 8 is connected to the drain electrode 62 through a via hole.

Referring to Figures 3a-3f, this embodiment also provides the first embodiment of the method for manufacturing the above-mentioned thin film transistor. In the first embodiment, the method includes the steps of:

S1. Provide a substrate 1, as shown in FIG. 3a;

S2, 4 form a gate 2 and a gate insulating layer 3 on the substrate 1, and the gate insulating layer 3 covers the gate 2, as shown in FIG. 3b;

S3, 4 forming a first metal layer 4 on the gate insulating layer 3, the first metal layer 4 includes a first electrode 41 and a second electrode 42 disposed on the gate insulating layer 3 at intervals, as shown in FIG. 3c;

S4, 4 Form an active layer 5 on the first metal layer 4, the active layer 5 includes a source contact end 51, a back channel portion 52, and a drain contact end 53, and the source contact end 51 is in contact with the first electrode 41 And cover part of the first electrode 41, the drain contact end 53 is in contact with the second electrode 42 and covers part of the second electrode 42, the back channel part 52 is located between the first electrode 41 and the second electrode 42 and corresponds to the gate 2 , as shown in Figure 3d;

S5, forming a second metal layer 6 on the first metal layer 4 and the active layer 5, the second metal layer 6 includes a source electrode 61 and a drain electrode 62 arranged at intervals, the source electrode 61 is located on the first electrode 41, and the drain electrode 62 is located on the second electrode 42, the source contact terminal 51 is sandwiched between the first electrode 41 and the source electrode 61, the drain contact terminal 53 is sandwiched between the second electrode 42 and the drain electrode 62, the source electrode 61 and the The first electrode 41 is in contact, and the drain 62 is in contact with the second electrode 42, as shown in FIG. 3e;

S6, depositing a passivation layer 7, the passivation layer 7 covers the exposed surfaces of the source electrode 61, the drain electrode 62, and the active layer 5, as shown in FIG. 3f.

In the preparation method of this embodiment, the first metal layer 4 and the second metal layer 6 are obtained through two patterning processes, thereby avoiding the formation of the first metal layer 4 and the second metal layer 6 due to different etching solutions. Different etching rates of the metal materials cause localized corrosion at the contact portion between the first metal layer 4 and the second metal layer 6 and chamfering occurs, resulting in faults in the subsequent passivation layer and electrical instability of the thin film transistor, etc., improving production quality. Rate.

Referring to Figures 4a-4e, specifically, step S2 includes:

S21, sequentially depositing a gate material layer 20 and a first photoresist layer 100 on the substrate 1, as shown in FIG. 4a;

S22. Exposing the first photoresist layer 100 through the first photomask to pattern the first photoresist layer to form a first photoresist region, as shown in FIG. 4b;

S23, removing the gate material layer 20 not covered by the first photoresist region through an etching process to form a gate 2, as shown in FIG. 4c;

S24, removing the first photoresist region through a photoresist ashing process, as shown in FIG. 4d;

S25, depositing a gate insulating layer 3 on the substrate 1 and the gate 2, the gate insulating layer 3 covers the gate 2, as shown in FIG. 4e.

5a-5d, specifically, step S3 includes:

S21, sequentially depositing a first metal material layer 40 and a second photoresist layer 101 on the gate insulating layer 3, as shown in FIG. 5a;

S22, exposing the second photoresist layer 101 through the second photomask to pattern the second photoresist layer to form second photoresist regions spaced apart from each other, as shown in FIG. 5b;

S23, removing the first metal material layer 40 not covered by the second photoresist region through an etching process to form the first metal layer 4, the first metal layer 4 includes the first electrodes 41 and the first electrodes 41 arranged on the gate insulating layer 3 at intervals The second electrode 42, as shown in Figure 5c;

S24, removing the second photoresist region through a photoresist ashing process, as shown in FIG. 5d.

Referring to Figures 6a-6d, specifically, step S4 includes:

S41, sequentially depositing an active material layer 50 and a third photoresist layer 102 on the first metal layer 4, as shown in FIG. 6a;

S42. Exposing the third photoresist layer 102 through a third photomask to pattern the third photoresist layer to form a third photoresist region, as shown in FIG. 6b;

S43, removing the active material layer 50 not covered by the third photoresist region through an etching process to form an active layer 5, the active layer 5 includes a source contact terminal 51, a back channel portion 52, and a drain contact terminal 53 , the source contact end 51 is in contact with the first electrode 41 and covers a part of the first electrode 41, the drain contact end 53 is in contact with the second electrode 42 and covers a part of the second electrode 42, and the back channel portion 52 is located between the first electrode 41 and Between the second electrodes 42 and corresponding to the gate 2, as shown in FIG. 6c;

S44, removing the third photoresist region through a photoresist ashing process, as shown in FIG. 6d.

Referring to Figures 7a-7d, specifically, step S5 includes:

S51, depositing a second metal material layer 60 and a fourth photoresist layer 103 on the gate insulating layer 3, the first metal layer 4, and the active layer 5, as shown in FIG. 7a;

S52, exposing the fourth photoresist layer 103 through a fourth photomask to pattern the fourth photoresist layer to form fourth photoresist regions spaced apart from each other, as shown in FIG. 7b;

S53, removing the second metal material layer 60 not covered by the fourth photoresist region through an etching process to form a second metal layer 6, the second metal layer 6 includes source electrodes 61 and drain electrodes 62 arranged at intervals, and the source electrodes are in contact The terminal 51 is interposed between the first electrode 41 and the source 61, the drain contact terminal 53 is interposed between the second electrode 42 and the drain 62, the source 61 is in contact with the first electrode 41, and the drain 62 is in contact with the second electrode 41. The two electrodes 42 are in contact, as shown in Figure 7c;

S54, removing the fourth photoresist region through a photoresist ashing process, as shown in FIG. 7d.

When preparing the array substrate, after step S6, the passivation layer needs to be patterned through the fifth photomask process, via holes are formed on the passivation layer, and then a pixel electrode material layer is deposited on the passivation layer , the pixel electrode material layer is patterned through the sixth mask process to obtain the pixel electrode 8, and the entire preparation process of the array substrate requires six masks.

Example 2

Referring to FIG. 8 , the difference between this embodiment and Embodiment 1 is that the source 61 is not in contact with the first electrode 41 , and the drain 62 is not in contact with the second electrode 42 .

Referring to Figures 9a to 9j, the preparation method of this embodiment adopts a half-tone mask process, and the preparation method includes steps:

S1. Provide a substrate 1, as shown in FIG. 9a;

S2, forming a gate 2 and a gate insulating layer 3 on the substrate 1, and the gate insulating layer 3 covers the gate 2, as shown in FIG. 9b;

S3, forming a first metal layer 4 on the gate insulating layer 3, the first metal layer 4 includes a first electrode 41 and a second electrode 42 arranged at intervals on the gate insulating layer 3, as shown in FIG. 9c;

S4, sequentially depositing an active material layer 50, a second metal material layer 60, and a third photoresist layer 70 on the first metal layer 4, as shown in FIG. 9d;

S5. Perform grayscale exposure on the third photoresist layer 70 through the third photomask to pattern the third photoresist layer to form a third photoresist region, the third photoresist region includes a middle part and two sides of the middle part The side part, the thickness of the middle part is smaller than the thickness of the side part, as shown in Figure 9e;

S6. Remove the active material layer 50 and the second metal material layer 60 not covered by the third photoresist region through an etching process to form the active layer 5. As shown in FIG. 9f, the active layer 5 includes a source contact terminal 51. The back channel portion 52, the drain contact end 53, the source contact end 51 extends to the surface of the first electrode 41, the drain contact end 53 extends to the surface of the second electrode 42, and the back channel portion 52 is located on the first electrode 41. Between the electrode 41 and the second electrode 42 and corresponding to the gate 2;

S7. Perform ashing treatment on the third photoresist area to remove the middle part and reduce the thickness of the side part, and retain part of the side part, as shown in FIG. 9g;

S8. Remove the second metal material layer 60 not covered by part of the side through an etching process to form a second metal layer 6. The second metal layer 6 includes a source electrode 61 and a drain electrode 62 arranged at intervals, and a source contact terminal 51 sandwiched between the first electrode 41 and the source 61, and the drain contact 53 is sandwiched between the second electrode 42 and the drain 62, as shown in FIG. 9h;

S9. Remove the third photoresist region by a photoresist ashing process, as shown in FIG. 9i

S10, depositing a passivation layer 7, the passivation layer 7 covers the exposed surfaces of the source electrode 61, the drain electrode 62, and the active layer 5, as shown in FIG. 9j.

Steps S1 to S3 in this embodiment are the same as those in Embodiment 1, and will not be repeated here. When preparing the array substrate, after step S10, the passivation layer needs to be patterned through the fourth photomask process, via holes are formed on the passivation layer, and then a pixel electrode material layer is deposited on the passivation layer , the pixel electrode material layer is patterned through the fifth photomask process to obtain the pixel electrode 8, and the entire preparation process of the array substrate requires five photomasks. Therefore, in this embodiment, the active layer 5 and the second metal layer 6 are formed on the first metal layer 4 through a half-tone mask process in the manufacturing method of the thin film transistor. Compared with the first embodiment, a photomask can be saved, thereby simplifying The preparation process reduces the preparation cost.

The above description is only the specific implementation of the present application. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present application, some improvements and modifications can also be made. It should be regarded as the protection scope of this application.

Claims (9)

1. a kind of thin film transistor (TFT), which is characterized in that including substrate, grid, gate insulation layer, the first metal layer, active layer, second Metal layer, passivation layer, the grid are set on the substrate, and the gate insulation layer covers the grid, the first metal layer Including the first electrode and second electrode being arranged at intervals on the gate insulation layer, the second metal layer includes spaced Source electrode and drain electrode, one end of the active layer are located between the first electrode and the source electrode, the active layer it is another End is located between the second electrode and the drain electrode, and it is exposed that the passivation layer is covered in the source electrode, drain electrode, active layer Surface.

2. thin film transistor (TFT) according to claim 1, which is characterized in that the source electrode is contacted with the first electrode, institute Drain electrode is stated to contact with the second electrode.

3. thin film transistor (TFT) according to claim 2, which is characterized in that the first metal layer and the gate insulation layer Adhesion is greater than the adhesion of the second metal layer and the gate insulation.

4. thin film transistor (TFT) according to claim 3, which is characterized in that the material of the second metal layer is copper.

5. thin film transistor (TFT) according to claim 4, which is characterized in that the material of the first metal layer be selected from molybdenum, chromium, One of titanium.

6. a kind of array substrate, which is characterized in that including the thin film transistor (TFT) as described in claim 1-4 is any.

7. a kind of preparation method of thin film transistor (TFT), which is characterized in that the preparation method comprising steps of

One substrate is provided；

Grid and gate insulation layer are formed over the substrate, and the gate insulation layer covers the grid；

The first metal layer is formed on the gate insulation layer, the first metal layer includes being arranged at intervals on the gate insulation layer First electrode and second electrode；

Active layer, second metal layer are formed on the first metal layer, the second metal layer includes spaced source electrode And drain electrode, one end of the active layer are located between the first electrode and the source electrode, the other end folder of the active layer Between the second electrode and the drain electrode；

Deposit passivation layer, the passivation layer are covered in the exposed surface of the source electrode, drain electrode, active layer.

8. preparation method according to claim 7, which is characterized in that form active layer, the on the first metal layer Two metal layers specifically include:

Active material is deposited on the first metal layer；

It is coated with third photoresist layer on the active material, the third photoresist layer is exposed by third road light shield, Make the third photoresist pattern layers, forms third photoresist region；

It is removed by etch process not by the active material of the third photoresist region overlay, forms active layer, it is described active One end of layer is contacted with the first electrode and covering part first electrode, the other end of the active layer and the second electrode Contact simultaneously covering part second electrode；

The second metal material layer is deposited on the gate insulation layer, first electrode, second electrode and active layer；

It is coated with the 4th photoresist layer on second metal material layer, the 4th photoresist layer is exposed by the 4th light shield Light makes the 4th photoresist pattern layers, forms the 4th photoresist region being spaced apart from each other；

It is removed by etch process not by the second metal material layer of the 4th photoresist region overlay, forms second metal layer, The second metal layer includes spaced source electrode and drain electrode, and one end of the active layer is located in the first electrode and institute State between source electrode, the other end of the active layer is located between the second electrode and the drain electrode, the source electrode with it is described First electrode contact, the drain electrode are contacted with the second electrode.

9. preparation method according to claim 7, which is characterized in that form active layer, the on the first metal layer Two metal layers include:

Active material is deposited on the first metal layer；

The second metal material layer is deposited on the active material；

Third photoresist layer is coated on second metal material layer, and ash is carried out to the third photoresist layer by third road light shield Rank exposure, makes the third photoresist pattern layers, forms third photoresist region, third photoresist region includes middle part and position In the side of the middle part two sides, the thickness of the middle part is less than the thickness of side；

It is removed by etch process not by the active material of the third photoresist region overlay, the second metal material layer, is formed Active layer, one end of the active layer are contacted with the first electrode, and the other end of the active layer connects with the second electrode Touching；

Ashing processing is carried out to third photoresist region, to remove middle part and reduce the thickness of side, retains portion sides；

The second metal material layer not covered by the portion sides is removed by etch process, forms second metal layer, it is described Second metal layer includes spaced source electrode and drain electrode, and one end of the active layer is located in the first electrode and the source Between pole, the other end of the active layer is located between the second electrode and the drain electrode.