CN109037209B - Integrated circuit layout structure - Google Patents

Abstract

The present invention discloses an integrated circuit layout structure, comprising a conducting semiconductor device and a conducted semiconductor device, wherein at least one metal layer of the conducting semiconductor device extends to insert into or cover at least one metal layer of the conducted semiconductor device, the extended metal layer of the conducting semiconductor device is a conducting metal layer, the metal layer inserted into or covered by the conducted semiconductor device is a conducted metal layer, the conducting metal layer is connected to other metal layers of the conducting semiconductor device through contact holes, and the conducting metal layer has no contact with the conducted semiconductor device. The layout structure of the present invention can make adjacent semiconductor devices meet the temperature coupling or induction requirements under the premise of meeting the minimum physical rules of the integrated circuit layout.

Description

Integrated Circuit Layout Structure

Technical Field

The present invention relates to the field of integrated circuits, and in particular to an integrated circuit layout structure.

Background Art

When manufacturing integrated circuit layout structures in the field of integrated circuits, due to certain functional requirements, the working environment (especially temperature) of two semiconductor devices needs to be kept as consistent or as close as possible, so as to compensate for the impact of differences in the working environment on device performance. Usually, when designing the layout structure, the physical positions of two semiconductor devices with the same working environment requirements are made as close as possible. However, since the integrated circuit layout needs to follow certain physical rules, there is a minimum physical distance limit between any devices. The distance between semiconductor devices must meet the minimum physical distance allowed, and semiconductor devices cannot be unlimitedly close. Therefore, there are semiconductor devices with the same working environment requirements, but the working environment (temperature coupling or induction) cannot be met due to the minimum physical distance limit, resulting in the situation that the performance of the semiconductor device cannot be guaranteed.

Summary of the invention

The technical problem to be solved by the present invention is to provide an integrated circuit layout structure that enables adjacent semiconductor devices to meet the requirements of the working environment (temperature coupling or induction) under the premise of meeting the minimum physical rules of the integrated circuit layout.

In order to solve the above technical problems, the integrated circuit layout structure provided by the present invention includes at least one metal layer of a conducting semiconductor device extending into or covering at least one metal layer of a conducted semiconductor device, the extended metal layer of the conducting semiconductor device is a conducting metal layer, the metal layer inserted into or covered by the conducted semiconductor device is a conducted metal layer, the conducting metal layer is connected to other metal layers of the conducting semiconductor device through contact holes, and the conducting metal layer has no contact with the conducted semiconductor device.

The integrated circuit layout structure is further improved, the conducting metal layer is arranged on the mth metal layer of the conducting semiconductor device, and the conducted metal layer is arranged on the nth metal layer of the conducted semiconductor, m≥1, n≥1.

Further improving the integrated circuit layout structure, when the conducted metal layer is the top metal layer of the conducted device, the conducting metal layer extends to cover the conducted metal layer;

When the conducted metal layer is not a top metal layer of the conducted device, the conducting metal layer extends into the conducted metal layer.

The integrated circuit layout structure is further improved. When the conducted metal layer is not the top metal layer of the conducted device, the conducting metal layer is extended to form a finger-like structure which is inserted into the conducted metal layer. The distance between the finger-like structure of the conducting metal layer and the conducted metal layer is the minimum physical distance that can be achieved by the existing process.

The integrated circuit layout structure is further improved, when the conducted metal layer is the top metal layer of the conducted device, the conducting metal layer is the top metal layer of the conducting device.

The integrated circuit layout structure is further improved, the conducting metal layer and the conducted metal layer are arranged in one-to-one correspondence, and the conducting metal layer is inserted into the nearest conducted metal layer.

The integrated circuit layout structure is further improved. When the number of conducting metal layers and the number of conducted metal layers are different, the conducting metal layer is inserted into the nearest conducted metal layer.

Further improving the integrated circuit layout structure, when the conductive metal layer covers the conductive metal layer, the distance d1 between the conductive metal layer and the conductive metal layer is 0.1 micrometers to 2.0 micrometers;

When the conducting metal layer is inserted into the conducted metal layer, the distance d2 between the conducting metal layer and the adjacent metal layer of the conducted metal layer is 0.1 micrometers to 2.0 micrometers.

The semiconductor device has at least 2-4 or even more metal layers connected to each other. The thickness of each metal layer is usually 0.5 microns to 4 microns. These metal layers have good thermal conductivity and are very suitable for heat conduction. The present invention utilizes the thermal conductivity of the metal layer to cover two (or even more) adjacent semiconductor devices with a conductive metal layer under the premise of meeting the minimum physical rules of the integrated circuit layout, so that each semiconductor device meets the designed temperature coupling or induction requirements.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments:

FIG. 1 is a partial cross-sectional view of a first embodiment of the present invention.

FIG. 1 a is a partial cross-sectional view of a first embodiment of the finger-shaped structure of the present invention.

FIG. 1 b is a partial cross-sectional view of a second embodiment of the finger-shaped structure of the first embodiment of the present invention.

FIG. 2 a is a partial cross-sectional view of a first embodiment of the second embodiment of the present invention.

FIG. 2 b is a partial cross-sectional view of a second embodiment of the present invention in a second form.

FIG. 2 c is a partial cross-sectional view of a third embodiment of the second embodiment of the present invention.

FIG. 3 a is a partial cross-sectional view of a first embodiment of the third embodiment of the present invention.

FIG. 3b is a partial cross-sectional view of the second embodiment of the third embodiment of the present invention.

FIG. 4 is a partial cross-sectional view of a fourth embodiment of the present invention.

Reference numerals

A is a conducting semiconductor device

B is the conducted semiconductor device

C is the conductive metal layer

D is the conductive metal layer

P is the substrate

Va is the conductive semiconductor device connection hole

Vb is the conducting semiconductor device connection hole

a1 is the first metal layer of the conductive semiconductor device

b1 is the first metal layer of the conductive semiconductor device

ax is the top metal layer of the conductive semiconductor device

by is the top metal layer of the semiconductor device being conducted

AM is a metal layer in the middle of a conductive semiconductor device

am' is a metal layer in the middle of another conductive semiconductor device

am'+1 is the metal layer above a metal layer in the middle of another conducting semiconductor device, and bn is a metal layer in the middle of the conducted semiconductor device.

am-1 is the metal layer below a metal layer in the middle of a conductive semiconductor device

am+1 is the metal layer above a metal layer in the middle of the conductive semiconductor device

bn-1 is the metal layer below a metal layer in the middle of the conductive semiconductor device

bn+1 is the metal layer above a metal layer in the middle of the conductive semiconductor device

d1 is the distance between the conducting metal layer and the conducted metal layer

d2 is the distance between the conducting metal layer and the adjacent metal layer to be conducted.

F is a finger-like structure

DETAILED DESCRIPTION

The integrated circuit layout structure provided by the present invention includes a conducting semiconductor device A and a conducted semiconductor device B. The conducting semiconductor device A and the conducted semiconductor device B are named relative to their functions, that is, the device is used as a conducting semiconductor device A relative to a certain semiconductor device X, but the device can also be used as a conducted semiconductor device B relative to a certain device Y.

At least one metal layer of the conducting semiconductor device A extends to the conducted semiconductor device B and inserts into or covers at least one metal layer of the conducted semiconductor device B. The extended metal layer of the conducting semiconductor device is named conducting metal layer C. The metal layer inserted into or covered by the conducted semiconductor device B is the conducted metal layer D. The conducting metal layer C is connected to other metal layers of the conducting semiconductor device through connecting holes, and the conducting metal layer C has no contact with the conducted semiconductor device.

As shown in FIG1, a partial cross-sectional view of the first embodiment of the present invention (other metal layers and semiconductor device structures are omitted), the first metal layer a1 of the conducting semiconductor device A is used as the conducting metal layer C, and the first metal layer b1 of the conducted semiconductor device B is used as the conducted metal layer D. Since the first metal layer of the semiconductor device is used as the conducting metal layer and the conducted metal layer, an insertion structure is adopted to form a finger-shaped structure F. The finger-shaped structure is inserted into the conducted metal layer D without contacting the conducted device B, and its insertion can be divided into two forms. One kind of finger-shaped structure is located on one side of the conducted metal layer, and the connection hole of the conducted semiconductor is located on the other side, as shown in FIG1a (other metal layers and semiconductor device structures are omitted). The other kind of finger-shaped structure is located in the middle of the conducted metal layer, and the connection holes of the conducted semiconductor are located on both sides of the finger-shaped structure, as shown in FIG1b (other metal layers and semiconductor device structures are omitted).

In the second embodiment of the present invention, when the conducted metal layer D is the top metal layer by of the conducted device B, the conducting metal layer C extends to cover the conducted metal layer D. The specific structure mainly includes the following three forms: x＞m＞1, y＞n＞1;

The first form is shown in FIG. 2a (other metal layers and semiconductor device structures are omitted), the top metal layer ax of the conducting semiconductor device A serves as the conducting metal layer C, and the top metal layer by of the conducted semiconductor device B serves as the conducted metal layer D. The top metal layer ax of the conducting semiconductor device A can be extended to cover the top metal layer by of the conducted semiconductor device B.

The second form is shown in FIG. 2b (other metal layers and semiconductor device structures are omitted), where a middle metal layer am of the conducting semiconductor device A is the conducting metal layer C, and the top metal layer by of the conducted semiconductor device B is the conducted metal layer D. Then the middle metal layer am of the conducting semiconductor device A extends upward to reach above the top metal layer by of the conducted semiconductor device B, and then extends horizontally to cover the top metal layer by of the conducted semiconductor device B.

The third form is shown in FIG. 2c (other metal layers and semiconductor device structures are omitted), where some middle metal layers of the conducting semiconductor device A serve as the conducting metal layer C. In this embodiment, the am and am-1 layers are taken as examples but are not limited to two layers, and multiple layers may be combined as the conducting metal layer C. The top metal layer by of the conducted semiconductor device B serves as the conducted metal layer D. Then the middle metal layers am and am-1 of the conducting semiconductor device A extend upward to the top metal layer by of the conducted semiconductor device B, and then extend horizontally to cover the top metal layer by of the conducted semiconductor device B.

In the third embodiment of the present invention, when the conducted metal layer D is the middle metal layer bn of the conducted device B, the conducting metal layer C extends and inserts into the conducted metal layer D. The specific structure mainly includes the following two forms: x＞m＞1, y＞n＞1;

The first form is shown in FIG3a (other metal layers and semiconductor device structures are omitted), the top metal layer ax of the conducting semiconductor device A serves as the conducting metal layer C, and the middle metal layer bn of the conducted semiconductor device B serves as the conducted metal layer D. The top metal layer ax of the conducting semiconductor device A extends and inserts into the middle metal layer bn of the conducted semiconductor device B, where n＞m＞1. In FIG3a, the middle metal layer bn of the conducted semiconductor device B is not shown in a side view because it is blocked by the top metal layer ax of the conducted semiconductor device A (i.e., the insertion form of FIG1a).

Correspondingly, the insertion form of the top metal layer ax of the conducting semiconductor device A extending and inserting into the middle metal layer bn of the conducted semiconductor device B can refer to the insertion forms of FIG. 1a and FIG. 1b.

The second form is shown in FIG3b (other metal layers and semiconductor device structures are omitted), the middle metal layer am of the conducting semiconductor device A serves as the conducting metal layer C, and the middle metal layer bn of the conducted semiconductor device B serves as the conducted metal layer D. The middle metal layer am of the conducting semiconductor device A extends and inserts into the middle metal layer bn of the conducted semiconductor device B, x＞m＞1, y＞n＞1. In FIG3b, the middle metal layer bn of the conducted semiconductor device B is blocked by the middle metal layer am of the conducting semiconductor device A in a side view and is not shown (i.e., the insertion form of FIG1a).

The intermediate metal layer am of the conducting semiconductor device A and the intermediate metal layer bn of the conducted semiconductor device B adopt the principle of proximity, that is, the distance between the two layers is as close as possible. Accordingly, the insertion form of the intermediate metal layer am of the conducting semiconductor device A extending and inserting into the intermediate metal layer bn of the conducted semiconductor device B can refer to the insertion forms of FIG. 1a and FIG. 1b.

In the above embodiments, when the conductive metal layer C covers the conducted metal layer D, the distance d1 between the conductive metal layer C and the conducted metal layer D is 0.1 micrometers to 2.0 micrometers;

When the conducting metal layer C is inserted into the conducted metal layer D, the distance d1 between the conducting metal layer C and the adjacent metal layer of the conducted metal layer D is 0.1 micrometers to 2.0 micrometers. Assuming that bn is the conducted metal layer, its adjacent metal layers are the bn-1 metal layer (lower metal layer) and the bn+1 metal layer (upper metal layer), that is, the distance d2 between the conducting metal layer C and the metal layer bn+1 above the conducted metal layer D is 0.1 micrometers to 2.0 micrometers, or the distance d2 between the conducting metal layer C and the metal layer bn-1 below the conducted metal layer D is 0.1 micrometers to 2.0 micrometers.

The fourth embodiment of the present invention has two conducting semiconductor devices, one conducting semiconductor device is named A1, the other conducting semiconductor device is named A2, and a conducted semiconductor B. The top metal layer metal ax of the conducting semiconductor device A1 is used as the conducting metal layer, the top metal by of the conducted semiconductor B is used as the conducted metal layer (relative to the semiconductor device A1), the middle metal layer am' of the other conducting semiconductor device A2 is used as the conducting metal layer, and the middle metal layer bn of the conducted semiconductor B is used as the conducted metal layer (relative to the semiconductor device A2), that is, the conducted semiconductor device B has two conducted metal layers (by, bn).

The present invention has been described in detail above through specific implementation modes and embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may also make many variations and improvements, which should also be regarded as the protection scope of the present invention.

Claims (6)

1. An integrated circuit layout structure comprising a conductive semiconductor device and a conductive semiconductor device, characterized in that: at least one metal layer of the conductive semiconductor device extends into or covers at least one metal layer of the conductive semiconductor device so that the conductive semiconductor device and the conductive semiconductor device meet the designed temperature coupling or temperature sensing requirements; the conductive semiconductor device extension metal layer is a conductive metal layer, the conductive semiconductor device is inserted into the metal layer or the covered metal layer is a conductive metal layer, the conductive metal layer is connected with other metal layers of the conductive semiconductor device through a contact hole, and the conductive metal layer is in non-contact with the conductive semiconductor device; the distance between the conductive metal layer and the conductive metal layer meets the minimum physical rule of the integrated circuit layout;

The conductive metal layer is arranged on the mth metal layer of the conductive semiconductor device, the conductive metal layer is arranged on the nth metal layer of the conductive semiconductor, m is more than or equal to 1, and n is more than or equal to 1; when the conductive metal layer is the top metal layer of the conductive device, the conductive metal layer extends to cover the conductive metal layer;

When the conductive metal layer is not the top metal layer of the conductive device, the conductive metal layer extends into the conductive metal layer.

2. The integrated circuit layout structure of claim 1 wherein: when the conductive metal layer is not the top metal layer of the conductive device, the conductive metal layer extends to form an interposed finger structure to be inserted into the conductive metal layer, and the distance between the interposed finger structure of the conductive metal layer and the interposed conductive metal layer is the minimum physical distance which can be realized by the prior art.

3. The integrated circuit layout structure of claim 1 wherein: when the conductive metal layer is the top metal layer of the conductive device, the conductive metal layer is the top metal layer of the conductive device.

4. The integrated circuit layout structure of claim 2 wherein: the conductive metal layers and the conductive metal layers are arranged in one-to-one correspondence, and the conductive metal layers are inserted into the conductive metal layers closest to each other.

5. The integrated circuit layout structure of claim 2 wherein: the conductive metal layer is inserted into the nearest conductive metal layer.

6. The integrated circuit layout structure of any of claims 1-5 wherein:

When the conductive metal layer covers the conductive metal layer, the distance d1 between the conductive metal layer and the conductive metal layer is 0.1-2.0 micrometers; when the conductive metal layer is inserted into the conductive metal layer, the distance d2 between the conductive metal layer and the adjacent metal layer of the conductive metal layer is 0.1 micrometers-2.0 micrometers.