CN109004021A - A kind of preparation method of bipolar junction transistor - Google Patents

Abstract

The invention provides a method for preparing a bipolar transistor and a semiconductor device formed therefor for testing, including a main chip area and a scribe lane area, forming a substrate of a first conductivity type and an epitaxial layer, and the epitaxial layer is formed on the substrate On the upper surface of the bottom, a base area is formed in the main chip area of the epitaxial layer, the base contact area runs through the base area and is connected to the epitaxial layer, and a main chip emission area connected to the base area is formed above the base area, and a connection with the epitaxial layer scribing line area is formed above the base area. The scribing track emission area connected by the epitaxial layer forms a metal layer on the base area, the main chip emission area and the scribing line emission area respectively, wherein the metal layer on the base area is electrically connected to the base area as a base pad, and the main chip emission area The metal layer on the top is electrically connected to the emission area of the main chip as an emitter pad, and the metal layer on the emission area of the scribing line is electrically connected to the emission area of the scribing line as a collector pad for testing.

Description

A kind of preparation method of bipolar transistor

technical field

The invention relates to the technical field of semiconductors, in particular to a method for preparing a bipolar transistor.

Background technique

General bipolar transistors have two basic structures: PNP type and NPN type. Among these three layers of semiconductors, the middle layer is called the base region, and the outer two layers are called the emitter region and the collector region. Usually the collector of the device is on the back of the silicon wafer, so after the front process is completed, due to the presence of a natural oxide layer on the front of the silicon wafer and some other layers (such as silicon nitride, polycrystalline, etc.) The contact between the collector and the test bench is very bad, and the contact resistance is very large.

Contents of the invention

The invention provides a method for preparing a bipolar transistor, and obtains a semiconductor device used for testing, so that after the front-side process is completed in a foundry, the initial test of the chip is safer and more accurate.

On the one hand, the present invention provides a kind of preparation method of bipolar transistor, comprising:

providing a substrate of a first conductivity type;

An epitaxial layer of the first conductivity type is formed on the surface of the substrate, and both the substrate and the epitaxial layer include a main chip area and a scribe lane area;

forming a base region in the main chip region of the epitaxial layer;

forming a base contact region of a second conductivity type, the base contact region penetrating through the base region and connected to the epitaxial layer;

Forming a main chip emission region connected to the base region above the base region, and forming a scribing path emission region connected to the epitaxial layer above the scribing path region of the epitaxial layer;

Metal layers are respectively formed on the base area, the main chip emission area and the scribe lane emission area, wherein the metal layer on the base area is electrically connected to the base area as a base pad, and the main The metal layer on the emitting area of the chip is electrically connected to the emitting area of the main chip as an emitter pad, and the metal layer on the emitting area of the scribing lane is electrically connected to the emitting area of the scribing lane as a collector pad for testing .

In another aspect, the present invention provides a semiconductor device for testing, including a main chip area and a scribe lane area, and the semiconductor device includes:

A substrate of the first conductivity type and an epitaxial layer of the first conductivity type, the epitaxial layer is formed on the upper surface of the substrate, and both the substrate and the epitaxial layer include a main chip area and a scribe lane area;

A base region of the second conductivity type formed on the upper surface of the main chip region of the epitaxial layer and connected to the epitaxial house;

a base contact region of a second conductivity type connected to the epitaxial layer through the base region;

A main chip emitter region connected to the base region formed above the base region;

a scribing-street emitter region connected to the epitaxial layer formed above the scribing-street region of the epitaxial layer;

a base pad formed above the base region and connected to the base contact region;

An emitter pad, formed above the emitting area of the main chip and connected to the emitting area of the main chip;

A collector pad for testing is formed above the scribing lane emission area and connected to the scribing lane emission area.

In the technical solution of the embodiment of the present invention, by optimizing the device design, the emitter metal contact is introduced in the scribe lane area without affecting any performance of the customer's main chip area. The test block is introduced into the chip track area, so that the initial test of the chip can be directly carried out after the foundry completes the front process.

Furthermore, the test block is formed by the same process as the emitter, and the test block can form a good ohmic contact with the substrate, which solves the problem of inaccurate test data due to lack of back process. At the same time, because the width of the test electrode in the scribing lane is much smaller than that of the scribing lane, after the customer completes the backside process, it will not have any impact on the subsequent dicing and packaging.

Description of drawings

The accompanying drawings are used to provide further understanding of the present invention, together with the embodiments of the present invention, are used to explain the present invention, and do not constitute a limitation to the present invention.

Fig. 1 is a schematic flow chart of a method for preparing a bipolar transistor provided by an embodiment of the present invention;

Fig. 2 is a schematic structural diagram after the base area of the main chip area is completed provided by an embodiment of the present invention;

Fig. 3 is a schematic structural diagram after forming an emission region in the main chip region and the scribe lane region provided by an embodiment of the present invention;

Fig. 4 is a schematic structural view of the emitter polycrystalline formed in the main chip area and the scribe lane area provided by the embodiment of the present invention;

5 is a schematic structural diagram of a semiconductor device after forming a metal layer provided by an embodiment of the present invention;

FIG. 6 is a top view of a semiconductor device provided by an embodiment of the present invention.

Explanation of reference signs:

1: main chip area; 2: scribe area; 3: substrate; 4 epitaxial layer; 5: oxide layer; 6: silicon dioxide protective layer; 11: base area; 12: base contact area; 13: main chip Emitter polycrystalline; 23: Emitter polycrystalline in scribing lane; 14: Emitting area of main chip; 24: Emitting area in scribing lane; 15: Base pad; 16: Emitter pad; 26: Collector pad.

Detailed ways

The preferred embodiments of the present invention will be described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

The manufacturing method of the bipolar transistor provided by the embodiment of the present invention will be described in detail below with reference to the accompanying drawings 1 to 6 .

Some embodiments of the present invention provide a method for manufacturing a bipolar transistor, please refer to FIG. 1 , which is a schematic flowchart of a method for manufacturing a bipolar transistor provided by an embodiment of the present invention.

As shown in FIG. 1 , the method in this embodiment of the present invention may include the following steps S101—step S111.

S101: Provide a substrate of a first conductivity type.

For the convenience of the following description, it is hereby explained that the transistor can be of NPN type or PNP type. When the transistor is of NPN type, the first conductivity type is P-type, and the second conductivity type is N-type. , when the transistor is of PNP type, the first conductivity type is N type, and the second conductivity type is P type. In the following embodiments, the transistor is described as an example of NPN type, but it is not limited thereto.

Specifically, please refer to FIG. 2. The substrate 3 is used as the carrier of the transistor and mainly plays a supporting role. The substrate in the embodiment of the present invention is made of lightly doped N-type material, and the material includes silicon, germanium, germanium Silicon, gallium arsenide and other semiconductor materials, those skilled in the art can select the type of the semiconductor substrate 3 according to the semiconductor device formed on the semiconductor substrate 3, so the type of the semiconductor substrate 3 should not limit the scope of the present invention protected range. In this embodiment, the semiconductor substrate 3 is a single crystal silicon substrate.

In other embodiments of the present invention, it also includes forming a buried layer in the substrate 3 .

S103: Form an epitaxial layer of the first conductivity type on the surface of the substrate, and both the substrate and the epitaxial layer include a main chip area and a scribe lane area.

Specifically, referring to FIG. 2, the epitaxial layer 4 is formed on the upper surface of the substrate 3, and after all the silicon dioxide is removed from the upper surface of the substrate 3, a layer of lightly doped first conductivity type material is epitaxially grown, preferably Yes, the epitaxial layer 4 is formed by a relatively simple homoepitaxial process, that is, the material of the epitaxial layer 4 is the same as that of the substrate 3, and when the material of the substrate 3 is silicon, the epitaxial layer 4 The material is also silicon. In other implementation manners, the epitaxial layer 4 can also be formed by hetero-epitaxy, and the material of the epitaxial layer 4 can also be semiconductor materials such as germanium and selenium. More specifically, the epitaxial growth method can be a vapor phase epitaxial growth method, a liquid phase epitaxial growth method, a vacuum evaporation growth method, a high frequency sputtering growth method, a molecular beam epitaxy growth method, etc., preferably a chemical vapor deposition method ( Or called vapor phase epitaxial growth method), the chemical vapor deposition method is a process in which gaseous reaction materials are reacted on the surface of a solid substrate and deposited into a solid thin layer or film. It is a relatively mature epitaxial growth method for transistors. In this method, silicon and dopant elements are sprayed on the substrate 3, and the uniformity and repeatability are good, and the step coverage is excellent. The epitaxial layer 4 is used as a collector area, and the entire bipolar integrated circuit is fabricated on this epitaxial layer. Epitaxial growth mainly considers the resistivity and thickness, usually the resistivity is 5-50ohm.cm, and the thickness is between 5-10um. In order to reduce the junction capacitance, increase the breakdown voltage, and reduce the diffusion effect in the subsequent process, the resistivity should be as high as possible; but in order to reduce the series resistance of the collector area, it is hoped that the resistivity should be smaller.

Both the substrate 3 and the epitaxial layer 4 include a main chip area 1 and a scribe lane area 2. On a wafer, there are usually hundreds or thousands of chips connected together. The main chip area 1 is used to make and form chips. There is a gap of 80um to 150um between them, which is the dicing lane area 2, which is used for dicing and packaging in the later stage of chip production.

S105: forming a base region in the main chip region of the epitaxial layer.

Specifically, please refer to FIG. 2 , the base region 11 is formed on the epitaxial layer 4, the epitaxial layer 4 is subjected to photolithography to etch the base region, and then boron is implanted and annealed to diffuse to form the base region 11. Region 11 is the lightly doped second conductivity type. Since the doping elements and their distribution in the base region directly affect the period current gain, cut-off frequency and other characteristics, the dose and energy of boron implantation should be specially controlled.

S107: forming a base contact of the second conductivity type, the base contact penetrating through the base region and connected to the epitaxial layer.

Specifically, please refer to FIG. 2 , the second conductivity type dopant is implanted in the base region 11 to form a base contact region 12 , and the base contact region 12 penetrates the base region 11 and the epitaxial layer 4 connect. The doping concentration of the base contact region 12 is higher than that of the base region 11, and the base region 11 is lightly doped. Since the contact between the subsequent electrodes and the lightly doped base region 11 is not good enough, heavy doping is used here instead. The impurity base contact region 12 is to improve the contact performance. After forming the base contact 12 , a silicon dioxide protective layer 6 is deposited over the base region 11 .

S109: Forming a main chip emission region connected to the base region above the base region, and forming a scribing path emission region connected to the epitaxial layer above the scribing path region of the epitaxial layer.

Specifically, referring to FIGS. 3-4 , the main chip emitter polysilicon 13 and the scribing street emitter polysilicon 23 are respectively formed on the base region 11 and the epitaxial layer scribing street region 2 according to the same process. A layer of polysilicon is formed by vapor deposition. Before polysilicon deposition, the contact hole area is cleaned with HF acid solution at a ratio of 100:1 for 120 seconds, and then immediately enters the furnace tube for polysilicon deposition. The thickness of polysilicon deposition is 1900A, use implantation to carry out heavy doping of N-type impurities on polycrystalline. In order to ensure that the leakage of the device is small, we generally use AS instead of P. After the doping is completed, photolithography and etching are used. The low temperature of 1000C pushes the AS impurities implanted in the polycrystalline into the epitaxial layer scribe area 2 and the base area 11, forming the main chip emission area 14 and the scribe line emission area 24, and retaining Polycrystalline above the emitter. The emitter polycrystalline structure can improve the magnification and frequency response characteristics of the bipolar transistor, reduce the area of the emitter region, reduce the area of the transistor, and reduce the junction depth of the emitter region and the base region, all of which reduce the transistor The vertical and horizontal dimensions improve the integration.

S111: Form a metal layer on the base area, the emission area of the main chip, and the emission area of the scribe lane, wherein the metal layer on the base area is electrically connected to the base area as a base pad, so The metal layer on the emission area of the main chip is electrically connected to the emission area of the main chip as an emitter pad, and the metal layer on the emission area of the scribe line is electrically connected to the emission area of the scribing line as a collector for testing pad.

Specifically, please refer to Fig. 5-6, the base contact hole is formed on the upper surface of the base contact region 12, and the upper surface of the emitter polycrystal 13 of the main chip and the emitter polycrystal 23 in the scribing lane region are formed by photolithography. The emitter contact hole is used to lead out the electrode line, the base contact hole and the sputtered metal aluminum in the emitter contact hole form a metal layer, and the base metal layer is electrically connected to the base contact region 12 through the base contact hole to form a base Electrode pad 15, the emitter metal layer of the main chip is electrically connected to the emitter region 14 of the main chip through the emitter contact hole to form an emitter pad 16, and the emitter metal layer of the scribing road is emitted through the emitter contact hole and the scribing road. The area 24 is electrically connected as a collector pad 26 for testing, and finally interconnection metal wiring is formed by photolithography.

In the technical solution of the embodiment of the present invention, by optimizing the device design, the emitter metal contact is introduced in the scribe lane area without affecting any performance of the customer's main chip area. The test block is introduced into the chip track area, so that the initial test of the chip can be directly carried out after the foundry completes the front process. The test block is formed by the same process as the emitter, and the test block can form a good ohmic contact with the substrate, which solves the problem of inaccurate test data caused by not doing the back process. At the same time, because the width of the test electrode in the scribing lane is much smaller than that of the scribing lane, after the customer completes the backside process, it will not have any impact on the subsequent dicing and packaging.

Some embodiments of the present invention provide a semiconductor device for testing. Please refer to FIG. 5. The structure of the semiconductor device includes a main chip area 1 and a scribe lane area 2. The semiconductor device includes: a substrate 3 of the first conductivity type and The epitaxial layer 4 of the first conductivity type, the epitaxial layer 4 is formed on the upper surface of the substrate 3, and the substrate 3 and the epitaxial layer 4 both include the main chip area 1 and the scribe lane area 2; A base region 11 of the second conductivity type connected to the epitaxial house 4 on the upper surface of the main chip region 1 of the epitaxial layer; a base contact of the second conductivity type connected to the epitaxial layer 4 through the base region 11 Region 12; the main chip emission region 14 formed above the base region 11 and connected to the base region 11; the scribing path emission region 24 formed above the epitaxial layer scribing path region 2 and connected to the epitaxial layer 4; A base pad 15 formed above the base region 11 and connected to the base contact region 12; an emitter pad 16 formed above the main chip emission region 14 and connected to the main chip emission region 14; A collector pad for testing is formed above the scribe street emitter region 24 and connected to the scribe row emitter region 24 .

Specifically, on a wafer, there are usually hundreds of chips connected together, the main chip area 1 is the part where the chips are formed, and there is a gap of 80um to 150um between each chip, which is the scribing lane area 2. It is used for dicing and packaging in the later stage of chip production.

Specifically, the substrate 3, as the carrier of the transistor, mainly plays a supporting role. The substrate in the embodiment of the present invention is made of lightly doped N-type material, and the material includes silicon, germanium, silicon germanium, gallium arsenide Those skilled in the art can select the type of the semiconductor substrate 3 according to the semiconductor device formed on the semiconductor substrate 3, so the type of the semiconductor substrate 3 should not limit the protection scope of the present invention. In this embodiment, the semiconductor substrate 3 is a single crystal silicon substrate. In other embodiments of the present invention, a buried layer formed in the substrate 3 is also included.

Specifically, the epitaxial layer 4 is formed on the upper surface of the substrate 3, and the material of the epitaxial layer 4 is the same as that of the substrate 3. When the material of the substrate 3 is silicon, the epitaxial layer 4 The material is also silicon. In other implementation manners, the material of the epitaxial layer 4 may also be different from that of the substrate 3 , and the material of the epitaxial layer 4 may also be semiconductor materials such as germanium and selenium.

Specifically, the base region 11 is formed on the epitaxial layer 4 , and the base region 11 is lightly doped with the second conductivity type. A base contact region 12 is formed in the base region 11 , and the base contact region 12 passes through the base region 11 and is connected to the epitaxial layer 4 . The doping concentration of the base contact region 12 is higher than that of the base region 11, and the base region 11 is lightly doped. Since the contact between the subsequent electrodes and the lightly doped base region 11 is not good enough, heavy doping is used here instead. The impurity base contact region 12 is to improve the contact performance. A silicon dioxide protection layer 6 is deposited and formed on the base region 11 .

Specifically, above the base region 11 and above the epitaxial layer scribing lane area 2 are respectively formed a main chip emitter polycrystalline 13 and a scribing lane emitter polycrystalline 23, and the main chip emitter polycrystalline 13 and the scribing lane The emitter polycrystalline 23 is annealed to form the main chip emission region 14 and the scribing street emission region 24 , and the formation process of the main chip emission region 14 and the scribing street emission region 24 is the same.

Specifically, a base contact hole is formed on the upper surface of the base contact region 12, and an emitter contact hole is formed on the upper surface of the emitter polycrystal 13 of the main chip and the emitter polycrystal 23 of the scribing lane by photolithography etching for leading out Electrode lines, the metal layer is formed in the contact hole, the base metal layer is electrically connected to the base contact region 12 to form a base pad 15, and the emitter metal layer of the main chip is electrically connected to the emitter region 14 of the main chip to form an emitter The electrode pad 16, the scribe line emitter metal layer and the scribe line emitter region 24 are electrically connected as the collector pad 26 for testing, and finally the interconnection metal wiring is formed by photolithography.

In the technical solution of the embodiment of the present invention, the emitter metal used as the collector pad is formed in the scribe lane area, and thus a test block is introduced in the scribe lane area, so that the chip can be directly tested for the initial test after the front-side process is completed in the foundry. The test block is formed by the same process as the emitter, and the test block can form a good ohmic contact with the substrate, which solves the problem of inaccurate test data caused by not doing the back process. At the same time, because the width of the test electrode in the scribing lane is much smaller than that of the scribing lane, after the customer completes the backside process, it will not have any impact on the subsequent dicing and packaging.

In addition, those skilled in the art can also make other changes within the spirit of the present invention. Of course, these changes made according to the spirit of the present invention should be included within the scope of protection claimed by the present invention.

Claims (10)

1. a kind of preparation method of bipolar junction transistor, which is characterized in that the described method includes:

The substrate of first conduction type is provided；

The epitaxial layer of the first conduction type is formed on the surface of the substrate, and the substrate and the epitaxial layer include master Chip region and dicing lane area；

Base area is formed in epitaxial layer main core section；

The base contact regions of the second conduction type are formed, the base contact regions are connect through the base area with the epitaxial layer；

The master chip emitter region connecting with the base area is formed above the base area, and in epitaxial layer dicing lane area It is rectangular at the dicing lane emitter region being connect with the epitaxial layer；

It is respectively formed metal layer in the base area, the master chip emitter region and the dicing lane emitter region, wherein the base Metal layer in area is electrically connected with the base area is used as base pad, metal layer and the main core in the master chip emitter region The electrical connection of piece emitter region is used as emitter pad, and the metal layer in the dicing lane emitter region is electrically connected with the dicing lane emitter region It connects as the collector pad for test.

2. the preparation method of bipolar junction transistor according to claim 1, which is characterized in that main core section emitter region It is formed with dicing lane area emitter region using identical technique.

3. the preparation method of bipolar junction transistor according to claim 1, which is characterized in that formed above the base area The master chip emitter region being connect with the base area, and formed above epitaxial layer dicing lane area and connect with the epitaxial layer Dicing lane emitter region specifically include:

Emitter polycrystalline is made respectively above the base area and above epitaxial layer dicing lane area；

Polycrystalline is carried out to the emitter polycrystalline to anneal to form the master chip emitter region and the dicing lane emitter region.

4. the preparation method of bipolar junction transistor according to claim 1, which is characterized in that in the base area, the master Metal layer is respectively formed in chip emission area and the dicing lane emitter region to specifically include:

Base contact hole is formed above the base area；

Metal is carried out above the base area, the master chip emitter region and above the dicing lane emitter region to contact to form metal Layer；

The metal layer is performed etching.

5. the preparation method of bipolar junction transistor according to claim 4, which is characterized in that the metal above the base area Layer is extended to out of described base contact hole above the base contact hole.

6. a kind of semiconductor devices for test, including main core section and dicing lane area, which is characterized in that the semiconductor device Part includes:

The epitaxial layer of the substrate of first conduction type and the first conduction type, the epitaxial layer are formed in the upper table of the substrate Face, and the substrate and the epitaxial layer include main core section and dicing lane area；

It is formed in the base area for the second conduction type that epitaxial layer main core section upper surface is connect with the extension room；

The base contact regions for the second conduction type being connect through the base area with the epitaxial layer；

It is formed in the master chip emitter region connecting above the base area with the base area；

It is formed in the dicing lane emitter region connecting above epitaxial layer dicing lane area with the epitaxial layer；

Base pad is formed in above the base area and connect with the base contact regions；

Emitter pad is formed in above the master chip emitter region and connect with the master chip emitter region；

For the collector pad of test, it is formed in above the dicing lane emitter region and is connect with the dicing lane emitter region.

7. semiconductor devices according to claim 6, which is characterized in that main core section emitter region and the dicing lane Area's emitter region is formed using identical technique.

8. semiconductor devices according to claim 6, which is characterized in that the base area top and the epitaxial layer dicing lane It is respectively formed with emitter polycrystalline above area, the emitter polycrystalline anneals to form main core section emitter region and the scribing Road area emitter region.

9. semiconductor devices according to claim 6, which is characterized in that in the base area, the master chip emitter region It contacts and etches by metal above the square and described dicing lane emitter region and be formed with metal layer.

10. semiconductor devices according to claim 9, which is characterized in that metal layer above the base area is from the base It is extended in area's contact hole above the base contact hole.