CN109003982A - 3D memory device and manufacturing method thereof - Google Patents
3D memory device and manufacturing method thereof Download PDFInfo
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- CN109003982A CN109003982A CN201810796632.1A CN201810796632A CN109003982A CN 109003982 A CN109003982 A CN 109003982A CN 201810796632 A CN201810796632 A CN 201810796632A CN 109003982 A CN109003982 A CN 109003982A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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Abstract
本申请公开了一种3D存储器件及其制造方法。所述3D存储器件包括：衬底；堆叠于所述衬底上方的第一叠层结构和第二叠层结构，所述第一叠层结构和第二叠层结构分别包括交替堆叠的多个栅极导体和多个层间绝缘层；以及贯穿所述第一叠层结构和第二叠层结构的多个沟道柱，所述沟道柱包括沟道层以及夹在多个栅极导体和所述沟道层之间的隧穿介质层、电荷存储层和栅介质层，所述沟道柱中至少沟道层连续延伸穿过所述第一叠层结构和第二叠层结构的边界。该3D存储器件中将两层叠层结构连接处的层叠结构部分断开，并用沟道层覆盖，可以避免连接处层叠结构受损形成泄漏源，也保证了沟道层的连续性，从而提高3D存储器件的良率和可靠性。
The application discloses a 3D storage device and a manufacturing method thereof. The 3D memory device includes: a substrate; a first stacked structure and a second stacked structure stacked above the substrate, and the first stacked structure and the second stacked structure respectively include a plurality of alternately stacked a gate conductor and a plurality of interlayer insulating layers; and a plurality of channel pillars penetrating through the first stacked structure and the second stacked structure, the channel pillars including a channel layer and sandwiched by the plurality of gate conductors and the tunnel dielectric layer, the charge storage layer and the gate dielectric layer between the channel layer, at least the channel layer in the channel column continuously extends through the first stacked structure and the second stacked structure boundary. In the 3D memory device, the stacked structure at the junction of the two-layer stacked structure is partially disconnected and covered with a channel layer, which can prevent the stacked structure at the junction from being damaged and form a leakage source, and also ensure the continuity of the channel layer, thereby improving the 3D memory. Yield and reliability of memory devices.
Description
Technical field
The present invention relates to memory technologies, more particularly, to 3D memory device and its manufacturing method.
Background technique
The raising of the storage density of memory device and the progress of semiconductor fabrication process are closely related.With semiconductors manufacture
The characteristic size of technique is smaller and smaller, and the storage density of memory device is higher and higher.In order to further increase storage density,
Develop the memory device (that is, 3D memory device) of three-dimensional structure.3D memory device includes along the multiple of vertical direction stacking
Storage unit can double up integrated level on the chip of unit area, and can reduce cost.
Existing 3D memory device is mainly used as non-volatile flash memory.Two kinds of main non-volatile flash technology difference
Using NAND and NOR structure.Compared with NOR memory device, the reading speed in nand memory part is slightly slow, but writing speed
Fastly, erasing operation is simple, and smaller storage unit may be implemented, to reach higher storage density.Therefore, it uses
The 3D memory device of NAND structure has been widely used.
In the 3D memory device of NAND structure, the grid of selection transistor and memory transistor is provided using laminated construction
Conductor realizes the storage of memory cell string using the channel column through laminated construction.Stacked structure higher for the number of plies, channel
The formation of column is more difficult, then is stacked and realized using two to more laminated construction, but can also make the channel column of upper and lower level in this way
Dislocation, when carrying out SNON punching, the channel column that will cause the corner of layer and layer junction is impaired, lets out if do not handled will form
Drain-source, so that 3D memory device fails.
It is expected that be further improved 3D memory device structure and its manufacturing method, with improve 3D memory device yield and can
By property.
Summary of the invention
The object of the present invention is to provide a kind of improved 3D memory device and its manufacturing methods, wherein by two layer laminate knots
The laminated unit of structure junction disconnects, and is covered with channel layer, can form leakage to avoid junction stepped construction is impaired
Source, also ensures the continuity of channel layer, to improve the yield and reliability of 3D memory device.
According to a first aspect of the present invention, a kind of 3D memory device is provided, comprising: substrate；It is stacked in above the substrate
First laminated construction and the second laminated construction, first laminated construction and the second laminated construction respectively include being alternately stacked more
A grid conductor and multiple interlayer insulating films；And multiple channels through first laminated construction and the second laminated construction
Column, the channel column include channel layer and the tunneling medium layer being clipped between multiple grid conductors and the channel layer, charge
Accumulation layer and gate dielectric layer, wherein what at least one layer in the tunneling medium layer, charge storage layer and gate dielectric layer disconnected
Position, at least channel layer is extended continuously in the channel column.
Preferably, the position of the disconnection is the boundary of first laminated construction and second laminated construction.
Preferably, the 3D memory device further include: separation layer is located at first laminated construction and the second laminated construction
Between, the channel layer extends continuously across the separation layer.
Preferably, epitaxial layer is formed between the channel column and the substrate, the channel layer part covering is described outer
Prolong layer.
Preferably, the channel column of first laminated construction and the channel column of second laminated construction are in institute
The junction for stating the first laminated construction and second laminated construction mutually staggers a certain distance, thus in the junction shape
At channel window.
Preferably, the part that the epitaxial layer is directly covered by the channel layer and the channel window are vertical corresponding.
Preferably, the interlayer insulating film of first laminated construction and second laminated construction is in contact, and is formed
Separation layer.
Preferably, the structure of the tunneling medium layer, charge storage layer and the gate dielectric layer that are in contact with the separation layer
In, the tunneling medium layer and the charge storage layer part disconnect.
Preferably, the tunneling medium layer, charge storage layer and gate dielectric layer part cover the epitaxial layer, and with part
The channel layer for covering the epitaxial layer is in contact.
Preferably, the bottom end of the multiple channel column forms common source connection via the epitaxial layer.
Preferably, the multiple channel column forms multiple deposit with multiple first grid conductors in the multiple grid conductor
Second grid conductor and third grid conductor in storage transistor, with the multiple grid conductor are respectively formed first choice crystal
Pipe and the second selection transistor.
Preferably, the third grid conductor includes nearest positioned at epitaxial layer described in distance in first laminated construction
One layer of grid conductor；The second grid conductor includes farthest positioned at epitaxial layer described in distance in second laminated construction
One layer of grid conductor；The first grid conductor be located at the second grid conductor and the third grid conductor it
Between.
According to a second aspect of the present invention, a kind of manufacturing method of 3D memory device is provided, comprising: be formed on the substrate first
Laminated construction；Form the first cylinder for running through first laminated construction；The second lamination is formed on first laminated construction
Structure；Form the second cylinder for running through second laminated construction；Remove one of first cylinder and second cylinder
Point, form channel hole；And form channel layer in the channel hole, wherein the tunneling medium layer, charge storage layer and
At least one layer of position disconnected in gate dielectric layer, at least channel layer is extended continuously in the channel hole.
Preferably, before the step of forming first laminated construction, further includes: deposition forms outer over the substrate
Prolong layer, the epitaxial layer is in contact with first cylinder.
Preferably, first laminated construction and first cylinder and second laminated construction and described the are formed
The step of two cylinders includes: alternately to deposit multiple grid conductors and multiple interlayer insulating films over the substrate to form first folded
Layer structure, performs etching first laminated construction, forms multiple first cylinders for running through first laminated construction；And
Multiple grid conductors are alternately deposited on first laminated construction and multiple interlayer insulating films form the second laminated construction, it is right
Second laminated construction performs etching, and forms multiple second cylinders for running through second laminated construction.
It preferably, further include forming channel column before the step of forming channel hole: first cylinder and second column
Body is connected；It is sequentially depositing along the inner wall of first cylinder and second cylinder and to form continuous gate dielectric layer, charge is deposited
Reservoir and tunneling medium layer；And it deposits to form sacrificial layer along the Tunnel dielectric layer surface.
Preferably, first cylinder and second cylinder are in first laminated construction and second laminated construction
Junction mutually stagger a certain distance, thus the junction formed channel window.
Preferably, the forming step in the channel hole include: by the channel window along the top of the channel column to
Bottom is punched out, and forms the through-hole for running through the channel column bottom, so that epitaxial layer portion exposure；Described the will be located at
The damaged charge storage layer and tunneling medium layer carry out portion of the junction of one laminated construction and second laminated construction
Divide etching；The damaged charge storage layer and tunneling medium layer of the junction of the epitaxial layer and the channel column will be located at
It is partially etched；And the sacrificial layer is all etched.
Preferably, the step of channel layer is formed in the channel hole includes: to be situated between along the channel column wall in the grid
The surface of matter layer, charge storage layer and tunneling medium layer carries out deposition and forms continuous channel layer, wherein the channel layer is complete
The gate dielectric layer, charge storage layer and tunneling medium layer, and the exposed surface of the covering epitaxial layer are covered, outside described
Prolong layer to be in contact.
Preferably, the bottom end of the multiple channel column forms common source connection via the epitaxial layer.
Preferably, the multiple grid conductor using the metal layer of atomic layer deposition by being formed.
Preferably, the metal layer is by being selected from least one of tungsten, platinum, titanium or its composition of alloy.
3D memory device provided in an embodiment of the present invention and its manufacturing method, it is rectangular at including being alternately stacked on substrate
The laminated construction of grid conductor and interlayer insulating film, and the channel column for running through the laminated construction is formed, channel column includes being close to ditch
The laminated construction of road column wall and channel layer positioned at laminated construction surface.The 3D memory device uses at least two layer laminate knots
The stacked structure of structure carries out SONO punching to channel column, by the impaired laminated construction portion of at least two layers laminated construction junction
Divide and etch away, the formation of source of leaks is avoided, to improve the yield and reliability of 3D memory device；And since word is not done in junction
Line function, so etching does not influence the normal storage function of memory device.
Further, it is formed with epitaxial layer between channel column and substrate, when carrying out SONO punching, is located at epi-layer surface
Laminated construction on form a perforative aperture, and the corner to connect in epitaxial layer with the inner wall of channel column, laminated construction
Also it can be damaged, impaired laminated construction is also subjected to partial etching, discontinuous laminated construction is formed, in laminated construction surface shape
At one layer of continuous channel layer, channel layer covers the exposed surface of laminated construction and epitaxial layer, guarantees the continuity of channel layer, from
And guarantee the normal storage performance of memory device.
Further, before punching, the surface of laminated construction is also covered with one layer of sacrificial layer, and after punching, sacrificial layer also breaks
It splits, does channel layer after sacrificial layer is etched away again, sacrificial layer can play a protective role to laminated construction, when can prevent punching
The important features such as the gate structure of memory device are damaged, to improve the yield and reliability of 3D memory device.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from.
The circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.
Fig. 2 shows the perspective views of 3D memory device.
The section in each stage of 3D memory device manufacturing method according to an embodiment of the present invention is shown respectively in Fig. 3 a to 3e
Figure.
The structural schematic diagram of the channel column of 3D memory device corresponding with Fig. 3 b and Fig. 3 e is shown respectively in Fig. 4 a and 4b.
Specific embodiment
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use " directly exist ... herein to describe located immediately at another layer, another region above scenario
Above " or " ... abut above and therewith " form of presentation.
In this application, term " semiconductor structure " refers to that is formed in each step of manufacture memory device entirely partly leads
The general designation of body structure, including all layers formed or region.Many specific details of the invention are described hereinafter,
Such as structure, material, size, treatment process and the technology of device, to be more clearly understood that the present invention.But as this field
Technical staff it will be appreciated that as, can not realize the present invention according to these specific details.
The present invention can be presented in a variety of manners, some of them example explained below.
The circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.In the embodiment
Shown in memory cell string include 4 storage units situation.It is appreciated that the invention is not limited thereto, in memory cell string
Number of memory cells can be to be any number of, for example, 32 or 64.
As shown in Figure 1a, the first end of memory cell string 100 is connected to bit line BL, and second end is connected to source electrode line SL.It deposits
Storage unit string 100 includes the multiple transistors being connected in series between the first end and a second end, comprising: first choice transistor
Q1, memory transistor M1 to M4 and the second selection transistor Q2.The grid of first choice transistor Q1 is connected to string selection line
The grid of SSL, the second selection transistor Q2 are connected to the ground selection line GSL.The grid of memory transistor M1 to M4 is respectively connected to
The respective word of wordline WL1 to WL4.
As shown in Figure 1 b, the selection transistor Q1 and Q2 of memory cell string 100 respectively include gate conductor layer 122 and 123,
Memory transistor M1 to M4 respectively includes gate conductor layer 121.In gate conductor layer 121,122 and 123 and memory cell string 100
Transistor stacking order it is consistent, separated each other using interlayer insulating film between adjacent gate conductor layer, to form grid
Laminated construction.Further, memory cell string 100 includes channel column 110.Channel column 110 is adjacent with rhythmic structure of the fence or passes through
Wear rhythmic structure of the fence.In the middle section of channel column 110, tunneling medium layer is accompanied between gate conductor layer 121 and channel layer 111
112, charge storage layer 113 and gate dielectric layer 114, to form memory transistor M1 to M4.At the both ends of channel column 110, grid
Gate dielectric layer 114 is accompanied between pole conductor layer 122 and 123 and channel layer 111, to form selection transistor Q1 and Q2.
In this embodiment, channel layer 111 is for example made of DOPOS doped polycrystalline silicon, tunneling medium layer 112 and gate dielectric layer 114
It is made of respectively oxide, such as silica, charge storage layer 113 is by the insulating layer group comprising quantum dot or nanocrystal
At, such as the silicon nitride of the particle comprising metal or semiconductor, gate conductor layer 121,122 and 123 be made of metal, such as
Tungsten.Channel layer 111 is used to provide control selection transistor and control the channel region of transistor, the doping type of channel layer 111 and choosing
It is identical with the control type of transistor to select transistor.For example, selection transistor and control transistor for N-type, channel layer 111
It can be the polysilicon of n-type doping.
In this embodiment, the core of channel column 110 is channel layer 111, tunneling medium layer 112,113 and of charge storage layer
Gate dielectric layer 114 forms the laminated construction for surrounding core wall.In alternate embodiments, the core of channel column 110 is additional
Insulating layer, channel layer 111, tunneling medium layer 112, charge storage layer 113 and gate dielectric layer 114 are formed around semiconductor layer
Laminated construction.In alternate embodiments, the core of channel column 110 be hollow structure, channel layer 111, tunneling medium layer 112,
Charge storage layer 113 and gate dielectric layer 114 form the laminated construction for surrounding semiconductor layer.
In this embodiment, selection transistor Q1 and Q2, memory transistor M1 to M4 use public channel layer 111 and grid
Dielectric layer 114.In channel column 110, channel layer 111 provides the source-drain area and channel layer of multiple transistors.In the implementation of substitution
Example in, can use step independent of one another, be respectively formed selection transistor Q1 and Q2 semiconductor layer and gate dielectric layer and
The semiconductor layer and gate dielectric layer of memory transistor M1 to M4.In channel column 110, the semiconductor layer of selection transistor Q1 and Q2
It is electrically connected to each other with the semiconductor layer of memory transistor M1 to M4.
In write operation, memory cell string 100 writes data into memory transistor M1 into M4 using FN tunneling efficiency
Selected memory transistor.By taking memory transistor M2 as an example, while source electrode line SL ground connection, ground selection line GSL is biased to greatly
About zero volts, so that the selection transistor Q2 for corresponding to ground selection line GSL is disconnected, string selection line SSL is biased to high voltage
VDD, so that corresponding to the selection transistor Q1 conducting of string selection line SSL.Further, bit line BIT2 is grounded, wordline WL2 biasing
In program voltage VPG, such as 20V or so, remaining wordline is offset to low-voltage VPS1.Due to only selected memory transistor M2's
Word line voltage is higher than tunneling voltage, and therefore, the electronics of the channel region of memory transistor M2 is reached via tunneling medium layer 112
Charge storage layer 113, so that data are transformed into charge storage in the charge storage layer 113 of memory transistor M2.
In read operation, selected memory transistor of the memory cell string 100 according to memory transistor M1 into M4 is led
Logical state judges the quantity of electric charge in charge storage layer, to obtain the data of quantity of electric charge characterization.By taking memory transistor M2 as an example,
Wordline WL2, which is offset to, reads voltage VRD, remaining wordline is offset to high voltage VPS2.The on state of memory transistor M2 and its
Threshold voltage is related, i.e., related to the quantity of electric charge in charge storage layer, thus can be with according to the on state of memory transistor M2
Judge data value.Memory transistor M1, M3 and M4 are in the conductive state always, and therefore, the on state of memory cell string 100 takes
Certainly in the on state of memory transistor M2.Control circuit is according to the electric signal judgement storage detected on bit line BL and source electrode line SL
The on state of transistor M2, to obtain the data stored in memory transistor M2.
Fig. 2 shows the perspective views of 3D memory device.For the sake of clarity, it is not shown in Fig. 2 each in 3D memory device
A insulating layer.
The 3D memory device 200 shown in this embodiment includes that 4*4 amounts to 16 memory cell strings 100, each storage
Unit string 100 includes 4 storage units, to form the memory array that 4*4*4 amounts to 64 storage units.It is appreciated that
The invention is not limited thereto, and 3D memory device may include any number of memory cell strings, for example, 1024, each storage unit
Number of memory cells in string can be it is any number of, for example, 32 or 64.
In 3D memory device 200, memory cell string respectively includes respective channel column 110 and public grid is led
Body layer 121,122 and 123.The stacking order one of transistor in gate conductor layer 121,122 and 123 and memory cell string 100
It causes, is separated each other using interlayer insulating film between adjacent gate conductor layer, to form the grid conductor of rhythmic structure of the fence
120.Interlayer insulating film is being not shown in the figure.
The internal structure of channel column 110 is as shown in Figure 1 b, is no longer described in detail herein.In the centre of channel column 110
Channel layer 111, tunneling medium layer 112, charge storage layer 113 and grid inside part, gate conductor layer 121 and channel column 110
Dielectric layer 114 together, forms memory transistor M1 to M4.At the both ends of channel column 110, gate conductor layer 122 and 123 and channel
Channel layer 111 and gate dielectric layer 114 inside column 110 together, form selection transistor Q1 and Q2.
Channel column 110 runs through grid conductor 120, and is arranged in array, the first end of multiple channel columns 110 of same row
It is commonly connected to same bit line (i.e. one of bit line BL1 to BL4), second end is commonly connected to substrate 101, and second end is via lining
Bottom 100 forms common source connection.
The grid conductor 122 of string select transistor Q1 is divided into different grid by grid line gap (gate line slit)
Line.With multiple channel columns 110 of a line grid line be commonly connected to same string selection line (i.e. string selection line SSL1 to SSL4 it
One).
The grid conductor 121 of memory transistor M1 and M4 are separately connected integrally according to different levels.If storage is brilliant
The grid conductor 121 of body pipe M1 and M4 are divided into different grid lines by grid line gap, then the grid line of same level is via respective
Conductive channel 131 reaches interconnection layer 132, thus it is interconnected amongst one another, then same wordline is connected to (i.e. via conductive channel 133
One of wordline WL1 to WL4).
The grid conductor of ground selection transistor Q2 links into an integrated entity.If the grid conductor 123 of ground selection transistor Q2 by
Grid line gap is divided into different grid lines, then grid line reaches interconnection layer 132 via respective conductive channel 131, thus mutually
Even, then via with the being connected to same selection line GSL of conductive channel 133.
The section in each stage of 3D memory device manufacturing method according to an embodiment of the present invention is shown respectively in Fig. 3 a to 3e
Figure.The sectional view is intercepted along the AA line in Fig. 2.
The 3D memory device 300 of the present embodiment includes at least the laminated construction 150 of two-layer laminate, and the present embodiment is with two stackings
It for layer structure, that is, include substrate 101 and the laminated construction 150 ' and laminated construction 150 for being stacked in 101 top of substrate.Lamination knot
Structure 150 ' and laminated construction 150 respectively include the multiple grid conductors being alternately stacked and multiple interlayer insulating films, and through folded
Multiple channel columns of layer structure 150 ' and laminated construction 150, channel column includes channel layer 111, at least channel layer 111 in channel column
Extend continuously across the boundary of laminated construction 150 ' He laminated construction 150.
As shown in Figure 3a, the foundation structure of the 3D memory device manufacturing method of the embodiment of the present invention is shown, the structure
Forming step includes: that multiple interlayer insulating films 140 ' and multiple grid conductors 120 ' formation heap are alternately deposited on substrate 101
Folded laminated construction 150 '；Laminated construction 150 ' is performed etching, the cylinder 10 ' for running through laminated construction 150 ' is formed.Above-mentioned
Multiple grid conductors 120 are alternately deposited on laminated construction 150 ' and multiple interlayer insulating films 140 form the second layer stacked structure
150, laminated construction 150 is performed etching, the multiple cylinders 10 for running through laminated construction 150 are formed.
In this embodiment, substrate 101 is, for example, monocrystalline substrate, and interlayer insulating film 140 ' is for example made of silica.
Further, growth has epitaxial layer 102 on substrate 101, carries out the epitaxial deposition of silicon in the contact position of substrate 101 and cylinder 10 '
Growth forms silicon epitaxy layer (SEG).
It as shown in Figure 3b, is the schematic diagram of channel column.The channel column of the present embodiment includes being close in channel column 110 and 110 '
The trench sidewalls structure ONO of wall and sacrificial layer 116 positioned at the surface trench sidewalls structure ONO, ONO include that the tunnelling stacked is situated between
Matter layer 112, charge storage layer 113 and gate dielectric layer 114.The forming process of channel column 110 and 110 ' includes: cylinder 10 ' and column
Body 10 is connected；It is sequentially depositing to form continuous gate dielectric layer 114, charge storage layer 113 along the inner wall of cylinder 10 ' and cylinder 10
With tunneling medium layer 112；And it deposits to form sacrificial layer 116 along 112 surface of tunneling medium layer.Wherein, tunneling medium layer 112,
Charge storage layer 113 and gate dielectric layer 114 and sacrificial layer 116 are the layer structure of uniformly continuous, and sacrificial layer 116 is, for example, more
Crystal silicon.
150 cylinder 10 of top laminate structure is connected with the cylinder 10 ' of lower layer stacked structure 150 ', due to the work of technique
With the cylinder 10 and 10 ' of upper layer and lower layer laminated construction 150 and 150 ' being connected is in laminated construction 150 and laminated construction 150 '
Junction mutually stagger a certain distance, to will form channel window 160 in junction；And since upper layer cylinder 10 is under
When being formed, the characteristic by silicon is influenced layer cylinder 10 ', and channel column 110 and 110 ' is in upper coarse and lower fine cylindricality, so even
The bore for connecing the channel window 160 at place is smaller.Tunneling medium layer 112, charge storage layer 113 and gate dielectric layer 114 and sacrifice
Layer 116 is the continuous layer structure for covering entire two layers of channel column 110 and 110 '.
At this point, the bottom of the channel column 110 ' of 3D memory device 300 namely the surface of epitaxial layer 102 are tunneled over medium
Layer 112, charge storage layer 113 and gate dielectric layer 114 are covered, and the company of subsequent channel layer 110 ' and epitaxial layer 102 is unfavorable for
Logical, so to carry out SONO punch operation to it, one group of solid line as shown in L in figure passes through channel window 160 along the direction of L
It is punched out along the top of channel column 110 to the bottom of channel column 110 '.
Shown in Fig. 3 c, vertical punching is carried out to channel column 110 and 110 ', because of the ONO of channel column 110 and 110 ' and inner wall and
Sacrificial layer 116 is incline structure, and 160 size of channel window is smaller, in punching, is located at two layer stacked structures 150 and 150 '
Junction and it is located in the laminated construction 150 and 150 ' of junction of 101 surface of substrate and cylinder 10 ', tunneling medium layer 112,
Charge storage layer 113 and gate dielectric layer 114 and sacrificial layer 116 will receive the strong shock of the high deviation of punching, cause to be damaged.
To the tunneling medium layer 112 on 101 surface of substrate, charge storage layer 113 and gate dielectric layer 114 and sacrificial layer 116
It is punched out, to form the through-hole for running through 110 ' bottom of channel column, to make the exposure of 102 part of epitaxial layer, is convenient for subsequent and ditch
The connection of channel layer 111.After punching, the part of the exposure of epitaxial layer 102, i.e. position where through-hole is vertical with channel window 160 right
It answers.
And it is located at the ONO of the corner of 150 ' junction of laminated construction 150 and laminated construction and sacrificial layer 116 and is located at
The ONO and sacrificial layer 116 of the corner on 101 surface of substrate and the junction of channel column 110 ', the breakage as caused by punching, such as
Fruit is handled not in time, will form source of leaks, influences storage performance.So by damaged tunneling medium layer 112, electricity in the present embodiment
Lotus accumulation layer 113 and gate dielectric layer 114 are partially etched.
Specifically, the interlayer insulating film 140 of laminated construction 150 connects with the interlayer insulating film 140 ' of laminated construction 150 '
Touching forms separation layer.In ONO (tunneling medium layer 112, charge storage layer 113 and the grid that the two junction is in contact with separation layer
Dielectric layer 114) it is not corresponding with grid conductor 120, wordline function is not done, at this point, nor affecting on storage even if ONO is discontinuous
The storage performance of device, so the ONO of breakage is carried out partial etching.For example, to the tunnelling at above-mentioned two connecting corner
Dielectric layer 112 and charge storage layer 113 perform etching, and gate dielectric layer 114 is not dealt with, and still play protection to outboard structure and make
With, be consequently formed along 110 and 110 ' inner surface of channel column deposition incomplete continuous trench sidewalls structure ONO.And sacrificial layer
116 since punching is also damaged, and becomes discontinuous layer structure.
When punching, at channel window 160, the position outstanding of underlying channel column 110 ' is impacted, and is damaged, so
The case where tunneling medium layer 112, charge storage layer 113 and the gate dielectric layer 114 of side is etched and disconnects is shown in sectional view,
In fact, at impaired place, etching is applicable in.Tunneling medium layer 112, charge storage layer 113 and the gate dielectric layer on 101 surface of substrate
114 etched portions can be connected to through-hole, form bigger through-hole.
Then the formation of channel layer 111 is carried out, as shown in Figure 3d, sacrificial layer 116 damaged after punching is all etched
Fall, by discontinuous tunneling medium layer 112, charge storage layer 113 and gate dielectric layer 114 and through-hole exposure, in their table
Face forms channel layer.
As shown in Figure 3 e, along 110 and 110 ' inner wall of channel column in gate dielectric layer 114, charge storage layer 113 and Tunnel dielectric
The surface of layer 112 carries out deposition and forms continuous channel layer 111, wherein gate dielectric layer 114, charge is completely covered in channel layer 111
The exposed surface of accumulation layer 113 and tunneling medium layer 112 and epitaxial layer 102, i.e. channel layer 111 are continuous and extend through separation layer
Corresponding etching part, and channel layer 111 is connected by through-hole and epitaxial layer 102, epitaxial layer 102 is connected to common source electrode
Area.It is connected finally, multiple channel columns 110 ' form common source via the epitaxial layer 102 on substrate 101.
Preferably, multiple grid conductors 120 using the metal layer of atomic layer deposition (ALD) by being formed.Metal layer for example by
Selected from least one of tungsten, platinum, titanium or its composition of alloy.
The manufacturing method of the 3D memory device is completed as a result,.
The structural schematic diagram of the channel column of 3D memory device corresponding with Fig. 3 b and Fig. 3 e is shown respectively in Fig. 4 a and 4b.Figure
4a and Fig. 4 b presents the stereochemical structure of channel column 110.
As shown in fig. 4 a, in conjunction with the description to Fig. 3 a- Fig. 3 e, in the junction A of laminated construction 150 and laminated construction 150 '
Punching damage is formed at the corner B that place and substrate 101 are connect with cylinder 110 ', is needed to the gate dielectric layer at A and at B
114, charge storage layer 113 and tunneling medium layer 112 carry out partial etching.
As shown in Figure 4 b, after sacrificial layer 116 being etched, new channel layer 111 is deposited.At the etching at A, charge storage layer
113 and tunneling medium layer 112 it is discontinuous, do not do wordline function；At the etching at B, charge storage layer 113 and tunneling medium layer
112 is discontinuous, and third grid conductor 123 and channel column 110 ' form selection transistor GSL；At 110 top of channel column, only ditch
Channel layer 111 and gate dielectric layer 114, second grid conductor 122 and channel column 110 form selection transistor SSL；Second grid conductor
First grid conductor 121 and channel column 110 and 110 ' between 122 and third grid conductor 123 form memory transistor, connection
To wordline WL1-WL4, WL1 '-WL4 '.
Here only there can actually be 32, the different number of wordline such as 64 by taking every layer of 4 wordline as an example.And
Above-described embodiment is only preferable section Example, and embodiments of the present invention are not limited thereto.
3D memory device provided in an embodiment of the present invention and its manufacturing method, it is rectangular at including being alternately stacked on substrate
The laminated construction of grid conductor and interlayer insulating film, and the channel column for running through the laminated construction is formed, channel column includes being close to ditch
The laminated construction of road column wall and channel layer positioned at laminated construction surface.The 3D memory device uses at least two layer laminate knots
The stacked structure of structure carries out SONO punching to channel column, by the impaired laminated construction portion of at least two layers laminated construction junction
Divide and etch away, the formation of source of leaks is avoided, to improve the yield and reliability of 3D memory device；And since word is not done in junction
Line function, so etching does not influence the normal storage function of memory device.
Further, it is formed with epitaxial layer between channel column and substrate, when carrying out SONO punching, is located at epi-layer surface
Laminated construction on form a perforative aperture, and the corner to connect in epitaxial layer with the inner wall of channel column, laminated construction
Also it can be damaged, impaired laminated construction is also subjected to partial etching, discontinuous laminated construction is formed, in laminated construction surface shape
At one layer of continuous channel layer, channel layer covers the exposed surface of laminated construction and epitaxial layer, guarantees the continuity of channel layer, from
And guarantee the normal storage performance of memory device.
In the above description, the technical details such as composition, the etching of each layer are not described in detail.But
It will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition, being
Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method.
In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous
Ground is used in combination.
The embodiment of the present invention is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the invention.The scope of the present invention is limited by appended claims and its equivalent.This hair is not departed from
Bright range, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in of the invention
Within the scope of.
Claims (22)
1. a kind of 3D memory device, comprising:
Substrate；
The first laminated construction and the second laminated construction being stacked in above the substrate, first laminated construction and the second lamination
Structure respectively includes the multiple grid conductors and multiple interlayer insulating films being alternately stacked；And
Through multiple channel columns of first laminated construction and the second laminated construction, the channel column includes channel layer and folder
Tunneling medium layer, charge storage layer and gate dielectric layer between multiple grid conductors and the channel layer,
Wherein, at least one layer of position disconnected in the tunneling medium layer, charge storage layer and gate dielectric layer, the channel
At least channel layer is extended continuously in column.
2. 3D memory device according to claim 1, wherein the position of the disconnection is first laminated construction and institute
State the boundary of the second laminated construction.
3. 3D memory device according to claim 2, wherein further include: separation layer, be located at first laminated construction and
Between second laminated construction, the channel layer extends continuously across the separation layer.
4. 3D memory device according to claim 3, wherein be formed with extension between the channel column and the substrate
Layer, the channel layer part cover the epitaxial layer.
5. 3D memory device according to claim 4, wherein the channel column of first laminated construction and described
The channel column of two laminated construction mutually staggers one in the junction of first laminated construction and second laminated construction
Fixed distance, to form channel window in the junction.
6. 3D memory device according to claim 5, wherein the part that the epitaxial layer is directly covered by the channel layer
It is vertical corresponding with the channel window.
7. 3D memory device according to claim 3, wherein first laminated construction and second laminated construction
The interlayer insulating film is in contact, and forms separation layer.
8. 3D memory device according to claim 7, wherein the tunneling medium layer that is in contact with the separation layer,
In the structure of charge storage layer and gate dielectric layer, the tunneling medium layer and the charge storage layer part are disconnected.
9. 3D memory device according to claim 4, wherein the tunneling medium layer, charge storage layer and gate dielectric layer
Part covers the epitaxial layer, and is in contact with the channel layer for partially covering the epitaxial layer.
10. 3D memory device according to claim 4, wherein the bottom end of the multiple channel column is via the epitaxial layer
Form common source connection.
11. 3D memory device according to claim 4, wherein in the multiple channel column and the multiple grid conductor
Multiple first grid conductors form multiple memory transistors, with the second grid conductor and third in the multiple grid conductor
Grid conductor is respectively formed first choice transistor and the second selection transistor.
12. 3D memory device according to claim 11, wherein the third grid conductor includes being located at described first to fold
One layer of nearest grid conductor of epitaxial layer described in distance in layer structure；The second grid conductor includes being located at described second
One layer of farthest grid conductor of epitaxial layer described in distance in laminated construction；The first grid conductor is located at the second gate
Between pole conductor and the third grid conductor.
13. a kind of manufacturing method of 3D memory device, comprising:
The first laminated construction is formed on the substrate；
Form the first cylinder for running through first laminated construction；
The second laminated construction is formed on first laminated construction；
Form the second cylinder for running through second laminated construction；
A part of first cylinder and second cylinder is removed, channel hole is formed；And
Channel layer is formed in the channel hole,
Wherein, at least one layer of position disconnected in the tunneling medium layer, charge storage layer and gate dielectric layer, the channel
At least channel layer is extended continuously in hole.
14. manufacturing method according to claim 13, wherein before the step of forming first laminated construction, also
It include: to deposit to form epitaxial layer over the substrate, the epitaxial layer is in contact with first cylinder.
15. manufacturing method according to claim 14, wherein formed first laminated construction and first cylinder with
And the step of second laminated construction and second cylinder, includes:
Multiple grid conductors are alternately deposited over the substrate and multiple interlayer insulating films form the first laminated construction, to described
First laminated construction performs etching, and forms multiple first cylinders for running through first laminated construction；And
Multiple grid conductors are alternately deposited on first laminated construction and multiple interlayer insulating films form the second lamination knot
Structure performs etching second laminated construction, forms multiple second cylinders for running through second laminated construction.
16. the manufacturing method according to claim 15, wherein further include forming channel before the step of forming channel hole
Column:
First cylinder is connected with second cylinder；
Be sequentially depositing along the inner wall of first cylinder and second cylinder to be formed continuous gate dielectric layer, charge storage layer and
Tunneling medium layer；And
It deposits to form sacrificial layer along the Tunnel dielectric layer surface.
17. the manufacturing method according to claim 16, wherein first cylinder and second cylinder are described first
The junction of laminated construction and second laminated construction mutually staggers a certain distance, to form channel in the junction
Window.
18. manufacturing method according to claim 17, wherein the forming step in the channel hole includes:
It is punched out, is formed through the channel column bottom to bottom along the top of the channel column by the channel window
Through-hole, so that epitaxial layer portion exposure；
To be located at the junction of first laminated construction and second laminated construction the damaged charge storage layer and
Tunneling medium layer carries out partial etching；
To be located at the damaged charge storage layer and tunneling medium layer of the junction of the epitaxial layer and the channel column into
Row part etches；And
The sacrificial layer is all etched.
19. manufacturing method according to claim 18, wherein the step of formation channel layer includes: in the channel hole
Deposition, which is carried out, on the surface of the gate dielectric layer, charge storage layer and tunneling medium layer along the channel column wall forms company
Continuous channel layer,
Wherein, the gate dielectric layer, charge storage layer and tunneling medium layer is completely covered in the channel layer, and covers described outer
The exposed surface for prolonging layer is in contact with the epitaxial layer.
20. manufacturing method according to claim 19, wherein the bottom end of the multiple channel column is via the epitaxial layer shape
It is connected at common source.
21. manufacturing method according to claim 19, wherein the multiple grid conductor is by the gold using atomic layer deposition
Belong to layer to be formed.
22. manufacturing method according to claim 20, wherein the metal layer is by being selected from least one of tungsten, platinum, titanium
Or its composition of alloy.
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