CN108989260B - Improved all-digital timing synchronization method and device based on Gardner - Google Patents

Abstract

The invention discloses an improved all-digital timing synchronization method and device based on Gardner, wherein the method comprises: using a CIC filter to smooth and filter the timing error output by a Gardner timing error detector; The error enters the loop filter processing of the pre-designed loop filter parameters; if the number of sampling points in the symbol period is greater than the first threshold, the timing controller selects a single symbol to pull a timing control; if the number of sampling points in the symbol period is less than For the second threshold, the timing controller selects a plurality of symbols to pull the timing control once, so as to realize the timing synchronization of the baseband signal entering the receiving end after carrier stripping. This method can not only effectively reduce the jitter after signal synchronization, but also ensure that the time for the signal to reach synchronization lock will not be too long, and this algorithm can be used for timing synchronization regardless of high sampling rate or low sampling rate.

Description

Improved all-digital timing synchronization method and device based on Gardner

technical field

The present invention relates to the technical field of communication signal processing, in particular to a Gardner-based improved all-digital timing synchronization method and device.

Background technique

In the digital receiver of communication, since the sampling clock of the receiver and the clock of the sender are independent of each other, in order to output the demodulation symbols at the accurate sampling decision time, a timing synchronization algorithm must be used to synchronize the clock of the receiver with the clock of the sender. The traditional method is to continuously adjust the sampling clock of the receiving end through a closed-loop structure, so as to complete the clock synchronization. With the continuous development of FPGA and digital signal processing technology, all-digital receivers have been widely used, and the local processing clock of all-digital receivers is usually fixed at the FPGA main frequency, so the receiver cannot easily adjust the local clock to obtain the same The clock that is synchronized by the sender adopts the method based on timing control, error detection, and interpolation estimation to achieve clock synchronization.

Commonly used timing synchronization methods include: early-late gate, M&M, Gardner and other timing synchronization algorithms. The early-late gate algorithm requires at least three sampling points per symbol. If the baseband signal entering the early-late gate timing synchronization is in a long time When there is no edge hopping, the error signal obtained in these multiple symbol periods will always be 0, thus losing synchronization; the M&M algorithm only needs one sampling point per symbol, but it is sensitive to carrier frequency offset and phase offset. , it is necessary to complete the carrier synchronization first and then the timing synchronization; the Gardner algorithm requires two sampling points for each symbol, one of which is the best sampling point, and is insensitive to the carrier frequency offset and phase offset, and can be accurately implemented without carrier synchronization. Timing synchronization has been widely used in all-digital receivers due to its simple implementation structure, efficient and reliable synchronization performance.

In the related art, (1) the feedback-type symbol timing synchronization method based on interpolation filtering is also based on the Gardner algorithm for timing error detection, but the timing synchronization jitter is relatively large, and a high signal-to-noise ratio is required to achieve high-precision timing synchronization performance. (2) A high-speed parallel timing synchronization method based on interpolation method, which can realize timing synchronization at high-speed transmission rates of hundreds of megabits per second or even gigabits per second, but it has a large amount of processing operations, a large delay, and After synchronization, the jitter is large and the system complexity is high.

However, in an all-digital receiver, due to the randomness of signal transmission and the influence of noise and interference, when a typical timing synchronization method is used, the jitter after synchronization is large, so that the receiving end cannot correctly recover the demodulated symbols.

SUMMARY OF THE INVENTION

The present invention aims to solve one of the technical problems in the related art at least to a certain extent.

Therefore, an object of the present invention is to propose an improved all-digital timing synchronization method based on Gardner, which can effectively improve the reliability, applicability and versatility of timing synchronization, has high efficiency and little error, and is simple and easy to implement.

Another object of the present invention is to propose an improved all-digital timing synchronization device based on Gardner.

In order to achieve the above object, an embodiment of the present invention proposes an improved all-digital timing synchronization method based on Gardner, comprising the following steps: using a CIC filter to smooth and filter the timing error output by the Gardner timing error detector; The smoothed and filtered timing error enters the loop filter processing of the pre-designed loop filter parameters; if the number of sampling points in the symbol period is greater than the first threshold, the timing controller selects a single symbol to pull the timing control once; If the number of sampling points in the symbol period is less than the second threshold, the timing controller selects multiple symbols to pull one timing control, so as to realize the timing synchronization of the baseband signal entering the receiving end after carrier stripping, wherein the first A threshold is greater than the second threshold.

The Gardner-based improved all-digital timing synchronization method in the embodiment of the present invention can not only effectively reduce the jitter after signal synchronization, but also ensure that the time for the signal to reach synchronization lock will not be too long. This algorithm can be used for timing synchronization, thereby effectively improving the reliability, applicability and versatility of timing synchronization, high efficiency, small error, simple and easy to implement.

In addition, the Gardner-based improved all-digital timing synchronization method according to the above embodiments of the present invention may also have the following additional technical features:

Further, in an embodiment of the present invention, two sampling points of interpolation are output for each symbol period by an interpolation method, and the two sampling points are the transition point between the output of the optimal sampling point and the adjacent symbol. , extract the amplitude and polarity change information of the optimal sampling point of two adjacent symbols, and extract the timing error from the sampling signal according to the extracted information and whether the transition point of adjacent symbols is zero.

Further, in an embodiment of the present invention, according to the timing error, the two sampling points of the next symbol period are adjusted and output by the closed-loop feedback to the interpolation algorithm, and the optimal sampling point is output externally at the same time.

Further, in an embodiment of the present invention, the calculation formula of the timing error detector is as follows:

为第i个码元和第i-1个码元的中间采样点对应的值。Among them, y(i) is the value corresponding to the sampling point at the ith symbol,

is the value corresponding to the intermediate sampling point of the i-th symbol and the i-1-th symbol.

Further, in an embodiment of the present invention, the CIC filter includes a delay device and an adder-subtractor, and the loop filter adopts a second-order active proportional-integral structure.

In order to achieve the above object, another embodiment of the present invention proposes an improved Gardner-based all-digital timing synchronization device, including: a smoothing and filtering module for using a CIC filter to detect the timing error output by the Gardner timing error detector. Perform smoothing and filtering; the processing module is used to enter the smoothed and filtered timing error into the loop filter processing of the pre-designed loop filter parameters; the first control module is used for the number of sampling points in the symbol period greater than the first When the threshold is set, a single symbol is selected to pull a timing control through the timing controller; the second control module is configured to select multiple symbols to pull through the timing controller when the number of sampling points in the symbol period is less than the second threshold A timing control is performed to realize timing synchronization of the baseband signal entering the receiving end after carrier stripping, wherein the first threshold is greater than the second threshold.

The Gardner-based improved all-digital timing synchronization device in the embodiment of the present invention can not only effectively reduce the jitter after signal synchronization, but also ensure that the time for the signal to reach synchronization lock is not too long. This algorithm can be used for timing synchronization, thereby effectively improving the reliability, applicability and versatility of timing synchronization, high efficiency, small error, simple and easy to implement.

In addition, the Gardner-based improved all-digital timing synchronization device according to the above embodiments of the present invention may also have the following additional technical features:

Further, in an embodiment of the present invention, two sampling points of interpolation are output for each symbol period by an interpolation method, and the two sampling points are the transition point between the output of the optimal sampling point and the adjacent symbol. , extract the amplitude and polarity change information of the optimal sampling point of two adjacent symbols, and extract the timing error from the sampling signal according to the extracted information and whether the transition point of adjacent symbols is zero.

Further, in an embodiment of the present invention, according to the timing error, the two sampling points of the next symbol period are adjusted and output by the closed-loop feedback to the interpolation algorithm, and the optimal sampling point is output externally at the same time.

Further, in an embodiment of the present invention, the calculation formula of the timing error detector is as follows:

为第i个码元和第i-1个码元的中间采样点对应的值。Among them, y(i) is the value corresponding to the sampling point at the ith symbol,

is the value corresponding to the intermediate sampling point of the i-th symbol and the i-1-th symbol.

Further, in an embodiment of the present invention, the CIC filter includes a delay device and an adder-subtractor, and the loop filter adopts a second-order active proportional-integral structure.

Additional aspects and advantages of the present invention will be set forth, in part, from the following description, and in part will be apparent from the following description, or may be learned by practice of the invention.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of embodiments taken in conjunction with the accompanying drawings, wherein:

1 is a flowchart of an improved all-digital timing synchronization method based on Gardner according to an embodiment of the present invention;

2 is a waveform diagram of a baseband signal entering timing synchronization according to an embodiment of the present invention;

Fig. 3 is a device connection diagram according to an embodiment of the present invention;

4 is a structural block diagram of a loop filter according to an embodiment of the present invention;

5 is a flow chart of signal processing according to an embodiment of the present invention;

Fig. 6 is a simulation verification result diagram of the present invention based on the System Generator environment according to an embodiment of the present invention;

7 is a signal constellation diagram before timing synchronization according to an embodiment of the present invention and after timing synchronization according to the present invention;

FIG. 8 is a schematic structural diagram of an improved all-digital timing synchronization apparatus based on Gardner according to an embodiment of the present invention.

Detailed ways

The following describes in detail the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary, and are intended to explain the present invention and should not be construed as limiting the present invention.

The following describes the improved Gardner-based all-digital timing synchronization method and device according to the embodiments of the present invention with reference to the accompanying drawings.

FIG. 1 is a flowchart of an improved all-digital timing synchronization method based on Gardner according to an embodiment of the present invention.

As shown in Figure 1, the Gardner-based improved all-digital timing synchronization method includes the following steps:

In step S101, a CIC filter is used to smooth and filter the timing error output by the Gardner timing error detector.

It can be understood that, in this embodiment of the present invention, the timing error output by the Gardner timing error detector is first smoothed and filtered by a CIC filter. The implementation principle is briefly introduced below.

It can be seen from the principle of the communication system that the symbol signal sent by the transmitting end is transmitted through the channel, and the baseband signal obtained by the carrier stripping at the receiving end has a raised cosine characteristic. The baseband signal after carrier stripping is the baseband signal before entering timing synchronization. The waveform diagram is shown in Figure 2, and only two kinds of information, "0" or "1" are carried at any sampling moment.

Further, in an embodiment of the present invention, two sampling points of interpolation are output for each symbol period by an interpolation method, and the two sampling points are the output of the optimal sampling point and the transition point of adjacent symbols, and extract The amplitude and polarity change information of the optimal sampling point of two adjacent symbols is obtained, and the timing error is extracted from the sampling signal according to the extracted information and whether the transition point of adjacent symbols is zero.

Further, in an embodiment of the present invention, the two sampling points of the next symbol period are adjusted and output by the closed-loop feedback to the interpolation algorithm according to the timing error, and the optimal sampling point is output externally at the same time.

Specifically, the embodiment of the present invention realizes timing synchronization based on Gardner, which is completely independent of carrier synchronization. The basic idea of the algorithm is: output two interpolated sampling points for each symbol period through an interpolation method, one of which is the symbol The best sampling point is output, and the other is the transition point of the adjacent symbol. By extracting the amplitude and polarity change information of the best sampling point of the two adjacent symbols, plus whether the transition point of the adjacent symbol is With the information of zero, the timing error can be extracted from the sampled signal. At the same time, the timing error is fed back to the interpolation algorithm through the closed loop to adjust the interpolation to output the two sampling points of the next symbol period, and output the best sampling point to the outside world. .

And as shown in FIG. 3 , the device designed according to the method of the embodiment of the present invention consists of five parts: an interpolation filter, a timing error detector, a CIC filter, a loop filter, and a timing controller.

Further, in an embodiment of the present invention, the calculation formula of the timing error detector is as follows:

为第i个码元和第i-1个码元的中间采样点对应的值。Among them, y(i) is the value corresponding to the sampling point at the ith symbol,

is the value corresponding to the intermediate sampling point of the i-th symbol and the i-1-th symbol.

Specifically, the interpolation filter uses a polynomial interpolation function to implement interpolation, and is implemented by a simple and efficient Farrow structure, which is especially suitable for hardware circuit implementation and simplifies the computational complexity. The specific implementation method is: for each symbol, according to the control amount of the timing controller, take four sampling points adjacent to the corresponding point, and then use the Lagrangian interpolation formula based on the sample set of the four sampling points, based on the timing control Calculate the value of the two sampling points of the symbol, one of which is the best sampling point of the last output, and the other is the middle sampling point of the best sampling point of the two adjacent symbols. value.

Among them, the timing error detector calculation formula is as follows:

为第i个码元和第i-1个码元的中间采样点对应的值，当没有定时误差时，输出为零；当定时超前时，输出为负；当定时滞后时，输出为正。Among them, y(i) is the value corresponding to the sampling point at the ith symbol,

is the value corresponding to the middle sampling point of the i-th symbol and the i-1-th symbol. When there is no timing error, the output is zero; when the timing is advanced, the output is negative; when the timing lags, the output is positive.

Further, in one embodiment of the present invention, the CIC filter includes a delay device and an adder-subtractor.

Specifically, in the embodiment of the present invention, the error output of the timing error detector first passes through a CIC filter with a simple structure to smooth and average the error, so as to reduce the influence of error jitter on synchronization. The CIC filter used in the algorithm device is only realized by a delay device and an adder-subtractor, which has low complexity, occupies very low hardware resources, and is easy to implement.

In step S102, the smoothed and filtered timing error is entered into a loop filter process in which loop filter parameters are pre-designed.

It can be understood that the smoothed and filtered timing error is processed by the loop filter, and at the same time, the parameters of the loop filter should be reasonably designed.

Further, in an embodiment of the present invention, the loop filter adopts a second-order active proportional-integral structure.

Specifically, the loop filter in the embodiment of the present invention adopts a simple second-order active proportional-integral structure, and its implementation structure is shown in FIG. 4 .

The performance of the loop filter is adjusted by adjusting the values of the proportional constant C1 and the integral constant C2. The calculation formulas of C1 and C2 are as follows:

Where ε is the damping coefficient, T is the update time period of the frequency control word of the loop NCO, K _d is the loop gain, is the product of the phase detector gain K _p and the numerically controlled oscillator (NCO) gain K ₀ , and ω _n is the loop gain The damping oscillation frequency of the circuit is calculated as:

where B represents the noise bandwidth of the loop filter.

In the actual communication system, the reasonable design of the loop filter parameters can not only make the error jitter of the synchronization tracking loop smaller, but also ensure that the time for synchronization to lock is shorter, and it can be applied to any system sampling clock and code in a large range. Meta-rate signal timing synchronization process, which is universal.

The parameters of the loop filter designed in the embodiment of the present invention are as follows:

其中f_s为系统采样时钟，N为NCO相位累加器位数，如此所有参数取值后代入公式2和公式3，计算出合适的环路参数C1和C2，当然也可以根据工程实际需求进行微调整。The damping coefficient ε is generally 0.707, the loop bandwidth B is 0.001 of the symbol rate, the integration time T is the reciprocal of the system sampling clock, the phase detector gain _Kp is 1, and the NCO gain

Where f _s is the system sampling clock, N is the number of bits of the NCO phase accumulator, so all parameters are entered into formula 2 and formula 3, and the appropriate loop parameters C1 and C2 are calculated. Adjustment.

In step S103, if the number of sampling points in the symbol period is greater than the first threshold, select a single symbol to pull one timing control through the timing controller.

It can be understood that when there are enough sampling points in the symbol period, the timing controller selects a single symbol to pull the timing control once.

Specifically, the timing controller is mainly composed of a numerical control oscillator and a fractional interval counter. The numerical control oscillator acts as an accumulator and continuously subtracts the timing error output by the current symbol. When the overflow occurs, it is the position of the interpolation base point m _k ; The fractional interval counter calculates the fractional interval u _k , and outputs it together with m _k to the interpolation filter for interpolation, thereby adjusting the sampling position of the next symbol.

The improvement of the timing controller in the embodiment of the present invention: the number of sampling points n in the symbol period is determined according to the system sampling clock and the symbol rate, and if the number of sampling points in the symbol period is too small, M (M is greater than 1) codes are selected The element cycle pulls a timing control, that is, when the register of the numerical control oscillator overflows, the modulo M is taken as the value of the current accumulator, and the current interpolation base point is output, and the interval between the interpolation base points of the next M-1 symbols is fixed. is n, and the fractional interval _uk is calculated once in M symbol periods and output to the interpolation filter for interpolation. The timing controller of the embodiment of the present invention can reduce the phase jitter caused by the synchronization error and improve the synchronization performance; at the same time, when the device is implemented in hardware, the timing controller returns the value to itself after judging whether the numerical control oscillator overflows, so that the The delay required for the next accumulation is limited to low-rate sampling, and M symbols can also be pulled once. Therefore, the timing controller of the embodiment of the present invention expands the applicable range to the case of low sampling rate.

In step S104, if the number of sampling points in the symbol period is less than the second threshold, the timing controller selects multiple symbols to pull a timing control to realize the timing synchronization of the baseband signal entering the receiving end after carrier stripping, wherein, The first threshold is greater than the second threshold.

It can be understood that when the number of sampling points in the symbol period is small, the timing controller selects multiple symbols to pull one timing control.

The improved all-digital timing synchronization method based on Gardner will be further described below with reference to the accompanying drawings.

As shown in FIG. 5 , the processing flow of the embodiment of the present invention specifically includes:

(1) When the sampling rate of the system is greater than 3 times the signal bandwidth, it is considered to be an oversampling processing system. Then, the number of sampling points n in the symbol period can be calculated according to known information such as the system sampling rate, signal bandwidth, and signal style.

(2) Set the initial value to the loop filter register, the numerical control oscillator register in the timing controller, and the register in the fractional interval counter.

(3) According to the set initial value, the timing controller outputs the initial control quantity: interpolation base point and decimal interval value, starts the interpolation filter to perform interpolation estimation on the next symbol, and outputs two interpolation sampling points.

(4) The timing error detector receives the interpolation sampling point output by the interpolation filter, calculates the timing error at this moment, outputs the timing error to the CIC filter, smoothes the timing error within a length of a symbol, and obtains the average timing error.

(5) Reasonable design of the loop filter parameters for timing synchronization. According to the design rules of the loop filter parameters proposed by this algorithm, the loop filter required for the signal timing synchronization of sampling clock and symbol rate of any system in a large range can be designed. road parameters.

(6) The timing controller receives the output error value of the loop filter. By improving the timing controller, M symbols can be pulled once for timing control, and M can be set according to the multiplication relationship between the system sampling clock and the symbol rate. When the magnification is high, M can be set to 1, and when the magnification is low, M can be set to an integer greater than 1.

(7) After a period of synchronization process, the timing error reaches a convergence state and tends to be stable, achieves stable tracking of the received signal, and outputs the best decision signal for the signal.

In a specific embodiment of the present invention, assuming that the symbol rate of a QPSK signal is 28.6MHz and the system sampling clock is 300MHz, the number of sampling points in each symbol period of the baseband signal is not an integer, and the rounding is about 10. CIC filtering The length of the generator is set to 3*n sampling points, the loop filter is calculated as C1=0.01035, C2=1.32e-6 according to the design rule, and the timing controller is set to 3 symbols to pull a timing control. In the System Generator environment The Xilinx model is built for the algorithm device to simulate, and the simulation results are shown in Figure 6, where din_i and din_q are the inputs of the timing synchronization module, which are the QPSK baseband signals, and dout_i and dout_q are the optimal sampling point values output after timing synchronization , dout_i_1b and dout_q_1b are the sampling decisions for the best sampling point after timing synchronization, which are binary demodulation symbols, ted is the timing error curve, and samp_en is the synchronous extraction sequence. It can be seen from Figure 7 that the system processing delay is small, After synchronization achieves stable tracking, the error jitter is small.

The optimal sampling point value after timing synchronization in System Generator is output to Matlab, and the baseband signal constellation diagram before and after timing synchronization is drawn as shown in Figure 7. It can be seen from the constellation diagram that the device works stably and has good synchronization performance. , the recovered demodulation symbols are accurate and reliable, very close to the ideal QPSK constellation diagram, and the judgment result is correct.

The embodiments of the present invention have the following advantages, including:

(1) For the oversampling processing system, the number of sampling points in each symbol period is determined according to the known information such as the system processing sampling rate, signal bandwidth, received signal pattern, etc. When the theoretically calculated number of sampling points in the symbol period is not When it is an integer, the timing synchronization processing of this algorithm is not affected, and the number of sampling points in the symbol period can be taken as the nearest integer, that is, the algorithm of the present invention can handle the timing synchronization process of any symbol rate within a certain range.

(2) The error result of the timing error detector in the device of the present invention first enters the CIC filter for smooth filtering and averaging, and then is input to the loop filter, which can effectively reduce the error caused by timing error jitter to synchronization, and enhance the anti-corrosion effect. Interference ability.

(3) Propose a design rule of loop filter parameters that is generally used in the signal timing synchronization process of sampling clock and symbol rate of any system in a large range, so as to avoid the need to re-design the sampling clock or code rate in actual engineering. The problem of designing the loop parameters; at the same time, the reasonable design of the loop filter parameters can ensure that the synchronization convergence time is small, and the synchronization error jitter will not be too large.

(4) Improve the timing controller: according to the number of sampling points in the symbol period, set M symbols to pull one timing control, which can not only solve the problem of timing control accumulation when the ratio of the system sampling clock to the symbol rate is low It can effectively reduce the jitter of the timing error after synchronization lock, and further improve the synchronization accuracy.

According to the improved all-digital timing synchronization method based on Gardner proposed by the embodiment of the present invention, the phase error jitter after timing synchronization is small, the synchronization error curve is stable, and it has strong anti-interference ability and anti-noise performance; the realized structure is simple, Using the most basic logic devices, such as registers, multipliers, comparators, adders, multiplexers, etc., can be fully realized with low resource consumption; the algorithm processing platform is not limited, such as FPGA, DSP and other platforms are easy to implement ;The timing synchronization algorithm has strong versatility and is suitable for both high sampling rate and low sampling rate. Once the loop filter parameters are configured according to the design rules, when the system sampling clock or symbol rate is arbitrarily changed, it will automatically restart. Calculate loop parameters to improve efficiency.

Next, an improved all-digital timing synchronization device based on Gardner proposed according to an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 8 is a schematic structural diagram of an improved all-digital timing synchronization device based on Gardner according to an embodiment of the present invention.

As shown in FIG. 8 , the Gardner-based improved all-digital timing synchronization device 10 includes: a smoothing and filtering module 100 , a processing module 200 , a first control module 300 and a second control module 400 .

The smoothing and filtering module 100 is used for smoothing and filtering the timing error output by the Gardner timing error detector by using a CIC filter. The processing module 200 is used to enter the smoothed and filtered timing error into the loop filter processing of pre-designed loop filter parameters. The first control module 300 is configured to select a single symbol to pull a timing control through the timing controller when the number of sampling points in the symbol period is greater than the first threshold. The second control module 400 is configured to select a plurality of symbols to pull a timing control through the timing controller when the number of sampling points in the symbol period is less than the second threshold, so as to realize the timing synchronization of the baseband signal entering the receiving end after carrier stripping, Wherein, the first threshold is greater than the second threshold. The device 10 in the embodiment of the present invention can not only effectively reduce the jitter that occurs after the signal is synchronized, but also ensure that the time for the signal to reach the synchronization lock will not be too long, and this algorithm can be used for timing regardless of the high sampling rate or the low sampling rate. Synchronization, thereby effectively improving the reliability, applicability and versatility of timing synchronization, high efficiency, small error, simple and easy to implement.

Further, in an embodiment of the present invention, two sampling points of interpolation are output for each symbol period by an interpolation method, and the two sampling points are the output of the optimal sampling point and the transition point of adjacent symbols, and extract The amplitude and polarity change information of the optimal sampling point of two adjacent symbols is obtained, and the timing error is extracted from the sampling signal according to the extracted information and whether the transition point of adjacent symbols is zero.

Further, in an embodiment of the present invention, the two sampling points of the next symbol period are adjusted and output by the closed-loop feedback to the interpolation algorithm according to the timing error, and the optimal sampling point is output externally at the same time.

Further, in an embodiment of the present invention, the calculation formula of the timing error detector is as follows:

为第i个码元和第i-1个码元的中间采样点对应的值。Among them, y(i) is the value corresponding to the sampling point at the ith symbol,

is the value corresponding to the intermediate sampling point of the i-th symbol and the i-1-th symbol.

Further, in an embodiment of the present invention, the CIC filter includes a delay device and an adder-subtractor, and the loop filter adopts a second-order active proportional-integral structure.

It should be noted that the foregoing explanations of the embodiment of the Gardner-based improved all-digital timing synchronization method are also applicable to the Gardner-based improved all-digital timing synchronization apparatus of this embodiment, and details are not repeated here.

According to the improved Gardner-based all-digital timing synchronization device proposed in the embodiment of the present invention, the phase error jitter after timing synchronization is small, the synchronization error curve is stable, and it has strong anti-interference ability and anti-noise performance; the realized structure is simple, Using the most basic logic devices, such as registers, multipliers, comparators, adders, multiplexers, etc., can be fully realized with low resource consumption; the algorithm processing platform is not limited, such as FPGA, DSP and other platforms are easy to implement ;The timing synchronization algorithm has strong versatility and is suitable for both high sampling rate and low sampling rate. Once the loop filter parameters are configured according to the design rules, when the system sampling clock or symbol rate is arbitrarily changed, it will automatically restart. Calculate loop parameters to improve efficiency.

In addition, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature delimited with "first", "second" may expressly or implicitly include at least one of that feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise expressly and specifically defined.

In the description of this specification, description with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples", etc., mean specific features described in connection with the embodiment or example , structure, material or feature is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine the different embodiments or examples described in this specification, as well as the features of the different embodiments or examples, without conflicting each other.

Although the embodiments of the present invention have been shown and described above, it should be understood that the above-mentioned embodiments are exemplary and should not be construed as limiting the present invention. Embodiments are subject to variations, modifications, substitutions and variations.

Claims (10)

1. An improved all-digital timing synchronization method based on Gardner, which is characterized by comprising the following steps:

smoothing and filtering the timing error output by the Gardner timing error detector by using a CIC filter;

the smoothed and filtered timing error enters a loop filter with the parameters of the loop filter designed in advance for processing;

if the number of sampling points in the code element period is larger than a first threshold value, selecting a single code element by a timing controller to pull timing control for one time; and

and if the number of sampling points in the code element period is less than a second threshold value, selecting a plurality of code elements through the timing controller to pull timing control once so as to realize timing synchronization of the baseband signals entering a receiving end after carrier stripping, wherein the first threshold value is greater than the second threshold value.

2. The improved all-digital timing synchronization method based on Gardner as claimed in claim 1, wherein two sampling points of interpolation are outputted for each symbol period by interpolation method, the two sampling points are the transition points of the optimal sampling point output and the adjacent symbol, the amplitude and polarity change information of the optimal sampling point of the two adjacent symbols is extracted, and the timing error is extracted from the sampling signal according to the extracted information and the information whether the transition point of the adjacent symbol is zero.

3. The improved all-digital Gardner-based timing synchronization method according to claim 2, wherein two sampling points of the next symbol period are interpolated and outputted according to the timing error by adjusting the closed-loop feedback to the interpolation algorithm, and the optimal sampling point is outputted externally.

4. The improved all-digital Gardner-based timing synchronization method according to claim 1, wherein said timing error detector is calculated as follows:

wherein y (i) is a value corresponding to the sampling point at the ith symbol,

is the corresponding value of the ith symbol and the middle sampling point of the (i-1) th symbol.

5. The improved all-digital Gardner-based timing synchronization method according to any of claims 1-4, wherein said CIC filter comprises a delay and an adder-subtractor, and said loop filter employs a second-order active proportional-integral structure.

6. An improved all-digital timing synchronization device based on Gardner, comprising:

a smoothing and filtering module for smoothing and filtering the timing error output by the Gardner timing error detector with a CIC filter;

the processing module is used for enabling the smoothed and filtered timing error to enter a loop filter with the parameters of the loop filter designed in advance for processing;

the first control module is used for selecting a single code element to pull one-time timing control through the timing controller when the number of sampling points in the code element period is greater than a first threshold value; and

and the second control module is used for selecting a plurality of code elements to pull one-time timing control through the timing controller when the number of sampling points in the code element period is less than a second threshold value so as to realize timing synchronization of the baseband signals entering a receiving end after carrier stripping, wherein the first threshold value is greater than the second threshold value.

7. The improved all-digital timing synchronization device based on Gardner according to claim 6, wherein two sampling points of interpolation are outputted for each symbol period by interpolation method, the two sampling points are the transition points of the optimal sampling point output and the adjacent symbol, the amplitude and polarity change information of the optimal sampling point of the two adjacent symbols is extracted, and the timing error is extracted from the sampling signal according to the extracted information and the information whether the transition point of the adjacent symbol is zero.

8. The improved all-digital Gardner-based timing synchronization device according to claim 7, wherein two sampling points of the next symbol period are interpolated and outputted according to said timing error by adjusting the feedback to the interpolation algorithm in a closed loop, and the optimal sampling point is outputted externally.

9. The improved all-digital Gardner-based timing synchronization apparatus according to claim 6, wherein said timing error detector is calculated as follows:

wherein y (i) is a value corresponding to the sampling point at the ith symbol,

is the corresponding value of the ith symbol and the middle sampling point of the (i-1) th symbol.

10. The improved Gardner-based all-digital timing synchronization device according to any of claims 6-9, wherein said CIC filter comprises a delay and an adder-subtractor, and said loop filter employs a second order active proportional-integral structure.

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