CN108988854A - Phase-locked loop circuit - Google Patents

Abstract

The present invention relates to the field of radio frequency integrated circuit design, and provides a phase-locked loop circuit, including: a delay phase detector, a current compensation circuit, a charge pump circuit, a load capacitor, a low-pass filter, a voltage-controlled oscillator and a frequency division circuit , the phase delay detector is provided with a reference signal input terminal and a feedback signal input terminal connected to the frequency division circuit; the current compensation circuit and the charge pump circuit are connected to the phase delay detector in parallel Between the load capacitor and the load capacitor, the load capacitor, the low-pass filter, the voltage-controlled oscillator, and the frequency dividing circuit are serially connected in series. The phase-locked loop circuit can realize accurate circuit compensation, eliminate signal mismatch, and improve circuit stability and phase noise performance.

Description

PLL circuit

technical field

The invention belongs to the field of radio frequency integrated circuit design, and in particular relates to a phase-locked loop circuit.

Background technique

With the development of wireless communication technology and integrated circuit technology, more and more wireless communication systems are integrated on the chip. Phase-locked loops can generate precise clock signals or frequency signals, so they are widely used in clock generators. In electronic systems such as wireless communication systems and clock/data recovery circuits, frequency synthesizers based on phase-locked loops are widely used. In the radio frequency transceiver system. These requirements have promoted the research and development of phase-locked loop circuits.

The output current of the existing phase-locked loop charge pump is output by the pull-up and pull-down current sources controlled by the frequency detector and phase detector. Since the pull-up and pull-down current sources are respectively manufactured by P-type transistors and N-type transistors, when the environment When the conditions change, due to the different sensitivity of the P-type transistor and the N-type transistor to the temperature, there will be a current mismatch between the two. This affects the linearity of the output current of the charge pump, further affects the jitter of the output frequency of the voltage-controlled oscillator, and deteriorates the phase noise of the entire phase-locked loop.

Therefore, it is necessary to provide an accurate and stable phase-locked loop circuit.

Contents of the invention

In order to solve the above-mentioned problems in the prior art, the present invention provides a phase-locked loop circuit. The technical problem to be solved in the present invention is realized through the following technical solutions:

The application provides a phase-locked loop circuit, including: a phase-delay detector, a current compensation circuit, a charge pump circuit, a load capacitor, a low-pass filter, a voltage-controlled oscillator and a frequency division circuit, and the phase-delay detector is set There is a reference signal input terminal and a feedback signal input terminal connected to the frequency division circuit;

The current compensation circuit and the charge pump circuit are connected in parallel between the delay phase detector and the load capacitor, and the load capacitor, the low-pass filter, the voltage-controlled oscillator, and the frequency division circuit are connected in sequence.

In one embodiment, the delay phase detector is provided with a controllable delay unit, the controllable delay unit includes a plurality of delay units connected in series, and a plurality of control switches for controlling the number of delay units connected .

In one embodiment, the phase delay detector includes:

A first D flip-flop, the input terminal of which receives the reference signal, and the output terminal of which is connected to the first switch; and

A second D flip-flop, the input terminal of which receives the feedback signal, and the output terminal of which is connected to the second switch; and

An AND gate circuit, its input terminal is respectively connected to the output terminal of the first D flip-flop and the output terminal of the second D flip-flop, and the output terminal of the AND gate circuit is respectively connected to the reset terminal of the first D flip-flop and the second D flip-flop via a controllable delay unit. The reset terminal of the 2D flip-flop.

In one embodiment, the delay unit consists of two inverters.

Compared with prior art, the beneficial effect of the present invention:

The present application provides a phase-locked loop circuit, in which a delay circuit module is added to the front-stage circuit, and a corresponding charge pump compensation circuit is added to the corresponding rear-stage circuit, and the output error is artificially added in advance, so as to realize accurate compensation, The purpose of eliminating signal mismatch.

Furthermore, compared with the traditional charge pump phase-locked loop structure, the circuit structure adds a delay unit controlled by a digital code and an adjustable current compensation unit. The circuit can control the response time of the feedback loop signal by controlling the programmable digital delay unit, so as to control the reset time of the charge pump switch. At the same time, the digital delay unit controls the conduction time of the adjustable current compensation unit to achieve the function of current compensation. The circuit makes the output current of the charge pump stable, so that when the environmental conditions change and the process deviation exists, the voltage-controlled oscillator of the subsequent stage can work normally, so as to improve the stability of the circuit and the performance of phase noise.

It can be understood that within the scope of the present invention, the above-mentioned technical features of the present invention and the technical features specifically described in the following (such as embodiments and examples) can be combined with each other to form new or preferred technical solutions . Due to space limitations, we will not repeat them here.

Description of drawings

Fig. 1 is the circuit diagram of a kind of phase-locked loop circuit in the embodiment of the present invention;

Fig. 2 is the circuit diagram of a kind of delay controller in the embodiment of the present invention;

3 is a circuit diagram of a controllable delay unit in an embodiment of the present invention;

4 is a circuit diagram of a charge pump and a current compensation circuit in an embodiment of the present invention;

FIG. 5 is a circuit diagram of a delay unit in an embodiment of the present invention.

Detailed ways

In the following description, many technical details are proposed in order to enable readers to better understand the application. However, those skilled in the art can understand that the technical solutions claimed in this application can be realized even without these technical details and various changes and modifications based on the following implementation modes.

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific examples, but the implementation of the present invention is not limited thereto.

The first embodiment of the present application relates to a phase-locked loop circuit. As shown in Figure 1, the circuit includes: a delay phase detector, a current compensation circuit, a charge pump circuit, a load capacitor, a low-pass filter, a voltage-controlled oscillator and a frequency division circuit, and the delay phase detector is provided with a reference signal The input terminal and the feedback signal input terminal connected to the frequency dividing circuit;

The current compensation circuit and the charge pump circuit are connected in parallel between the time-delay phase detector and the load capacitor, and the load capacitor, the low-pass filter, the voltage-controlled oscillator and the frequency division circuit are connected in series in sequence.

A controllable delay unit is provided in the delay phase detector, and the controllable delay unit includes a plurality of delay units connected in series in sequence, and a plurality of control switches for controlling the number of times the delay units are turned on.

When the circuit is working, the delay phase detector adds a delay in the circuit path through the controllable delay unit to amplify the current error generated by the P-type transistor and the N-type transistor, and the charge pump current compensation circuit and the charge pump circuit generate two directions Opposite error currents, these two error currents cancel out current errors when injected into the load capacitor.

In one embodiment, a phase delay detector as shown in Figure 2, the phase delay detector includes:

A first D flip-flop, the input terminal A of which receives the reference signal, and the output terminal Q1 is connected to the first switch to control the switching state of the first switch; and

The second D flip-flop, its input terminal B receives the feedback signal, and the output terminal Q2 is connected to the second switch to control the switching state of the second switch; and

The AND gate circuit, its input terminal is respectively connected to the output terminal Q1 of the first D flip-flop and the output terminal Q2 of the second D flip-flop, and the output terminal is respectively connected to the reset terminal of the first D flip-flop and the second D flip-flop through the controllable delay unit. The reset terminal of the flip-flop.

When the circuit is working, high or low signals are generated at the two output terminals of Q1 and Q2. If the feedback signal is ahead of the reference signal, the pull-down switch is turned on, and the pull-up switch is turned off, so that the load capacitor _CL flows out current and V _CTRL The voltage drops. Otherwise, turn on the pull-up switch, turn off the pull-down switch, inject current into the load capacitor _CL , and increase the voltage of V _CTRL . When both Q1 and Q2 outputs are high, they are considered to be phase-aligned, so that both the pull-up switch and the pull-down switch are turned off, and the V _CTRL voltage is maintained. The reset signal passes through the controllable delay unit to reset the two D flip-flops. After the reset signal occurs, the pull-up and pull-down switches of the charge pump are turned on at the same time. At this time, the current source does not inject current into the load capacitor _CL , so that the voltage of V _CTRL is maintained. At this point the PLL is locked.

In addition, due to the delay control circuit added to the phase detector module, when the input reference signal A in the phase detector and the frequency divider feedback signal B are aligned, Q ₁ and Q ₂ are high at the same time, and the phase detector should be A reset signal is generated to make the pull-up and pull-down switches of the charge pump open at the same time, so as to keep the charge in the load capacitor _CL stable. However, the controllable delay unit will delay the delayed signal to play a role. At this time, the phase detector will not be reset immediately, but will make the pull-up and pull-down switches closed at the same time during the delay time. At this time, due to the P-type transistor and The sensitivity of N-type transistors to temperature is different, and the charge pump will generate a mismatch current. At the same time, the delay signal will control the charge pump current compensation circuit to generate the same current as the charge pump mismatch current and combine it to reach the charge pump. The purpose of the output current is very good linearity, thereby reducing the phase noise of the whole phase-locked loop system.

In one embodiment, a controllable delay unit is shown in Figure 3. The controllable delay unit includes a plurality of delay units D ₁ -D _n connected in series in sequence, and is used to control the The delay unit connects a plurality of control switches. Preferably, the delay unit is as shown in Figure 5. The delay unit is composed of two inverters. After the signal passes through the delay unit, it will be inverted twice. The shape of the inverted signal is the same as before, but it is delayed by a delay time .

When switch S1 is closed and other switches are open, all delay units are short _- circuited, and the circuit has no delay;

When the switch _S2 is closed and the other switches are open, only one delay unit _Dn works, and the loop has a delay;

When the switch S _n is closed and other switches are open, n-1 delay units work, and the loop has n-1 delays.

In one embodiment, the charge pump and the current compensation circuit are shown in FIG. 4 , the positive phase error current and the reverse error current are offset when flowing through the load capacitor, so as to obtain an accurate output current.

The charge pump circuit includes a switch controlled by the output voltage signal of the pre-stage frequency and phase detection circuit and two sets of current sources, which can realize the function of converting the output voltage signal of the pre-stage frequency and phase detection circuit into a current signal. The post-stage current compensation circuit includes a number of pull-up and pull-down current sources symmetrical to the charge pump current source controlled by digital signals. Through the delay time selected in the pre-stage controllable delay circuit, the compensation current of the corresponding time is added to achieve control High linearity of charge pump output stage current.

The charge pump output current stabilization circuit proposed by the present invention can be applied to any charge pump phase-locked loop circuit, and simple changes are made to the structure proposed in this patent, such as replacing the delay unit, replacing the pull-up and pull-down current source module, and variable delay control The encoding method is considered to be within the protection scope of this patent right.

It should be noted that, in this application document, relative terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations There is no such actual relationship or order between the operations. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or apparatus. Without further limitations, an element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element. In the application documents of this patent, if it is mentioned that an action is performed according to a certain element, it means that the action is performed based on at least the element, which includes two situations: the action is only performed based on the element, and the action is performed based on the element and Other elements perform the behavior.

The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deduction or replacement can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (4)

1. a kind of phase-locked loop circuit characterized by comprising delay phase discriminator, current compensation circuit, charge pump circuit, load Capacitor, low-pass filter, voltage controlled oscillator and frequency dividing circuit, the delay phase discriminator are provided with reference signal input terminal and connection To the feedback signal input terminal of the frequency dividing circuit；

The current compensation circuit and the charge pump circuit are connected between the delay phase discriminator and the load capacitance, institute Load capacitance, the low-pass filter, the voltage controlled oscillator, the frequency dividing circuit is stated to be sequentially connected.

2. phase-locked loop circuit according to claim 1, which is characterized in that be provided with controllable time delay in the delay phase discriminator Unit, the controllable time delay unit include multiple delay units being sequentially connected in series, and are connected for controlling the delay unit Multiple control switches of quantity.

3. phase-locked loop circuit according to claim 1, which is characterized in that the delay phase discriminator includes:

First d type flip flop, input terminal receive reference signal, and output end connects first switch；And

Second d type flip flop, input terminal receive feedback signal, and output end connects second switch；And

AND gate circuit, input terminal are separately connected the output end and the second d type flip flop output end of first d type flip flop, The output end of the AND gate circuit is separately connected the reset terminal and described of first d type flip flop through the controllable time delay unit The reset terminal of 2-D trigger.

4. phase-locked loop circuit according to claim 2, which is characterized in that the delay unit is made of two phase inverters.