CN108984115A - Data parallel write-in, read method, apparatus and system - Google Patents

Abstract

The present invention provides a data parallel writing and reading method, device and system. The method includes: converting the written data index of the data vector to be written into a one-dimensional writing address; according to the one-dimensional writing address and the predetermined Set the number of write data, obtain the write data enable vector, the first storage index vector and the first storage address vector of the data vector to be written; according to the first storage index vector, write data to reordering the enable vector, the first storage address vector, and the to-be-written data vector, and reordering all the reordered write data enable vectors and the first storage address vector according to the reordered write data enable vector and the first storage address vector The data vector to be written is stored in the parallel memory. The invention supports parallel writing of data from one or more dimensions, and improves the flexibility and writing efficiency of data writing.

Description

Data parallel writing and reading method, device and system

technical field

The invention belongs to the technical field of data access, and more specifically relates to a data parallel writing and reading method, device and system.

Background technique

In recent years, artificial intelligence has been widely used in various fields. Artificial intelligence algorithms are usually algorithms with a large amount of data. Therefore, in order to speed up the execution of artificial intelligence algorithms, not only the computing system but also the storage system need to be optimized.

GPU is a hardware platform for artificial intelligence algorithms that are widely used. GPU storage has a specific multi-level cache structure for matrix calculations to optimize the storage system. In the field of embedded applications, due to constraints such as power consumption, custom programmable chips are usually used instead of GPUs to implement artificial intelligence algorithms. One of these embedded chips is a vector computer chip, which is also very suitable for artificial intelligence algorithm acceleration. This type of computer chip usually uses vector memory as a storage system.

However, for the GPU, the size and power consumption are very large. Therefore, the use in the field of embedded applications is greatly limited. Artificial intelligence algorithms require a large number of matrix operations, so the processed data is often multi-dimensional data blocks, including one-dimensional and multi-dimensional. Different algorithms require parallel sequential reading and writing of data from one or more dimensions. However, the vector memory can only fixedly access a specific length of vector data at a time, and the flexibility of data access is insufficient to meet the data access requirements of complex and changeable artificial intelligence algorithms.

Contents of the invention

In order to overcome the problems of large size, large power consumption and inflexible data access of the existing data access system or at least partially solve the above problems, the present invention provides a data parallel writing and reading method, device and system.

According to a first aspect of the present invention, a data parallel writing method is provided, comprising:

Transform the write data index of the data vector to be written into a one-dimensional write address; wherein, the data vector to be written is a one-dimensional or multi-dimensional vector in the multidimensional data matrix to be written, and the write data The index is the index in the multidimensional data matrix to be written of the index of the first element to be written in the multidimensional data matrix to be written among all elements of the data vector to be written;

Acquire the write data enable vector, the first storage index vector, and the first storage address vector of the data vector to be written according to the one-dimensional write address and the preset number of write data; wherein, the write Each element in the input data enable vector is used to indicate whether the element at the corresponding position in the data vector to be written is written; the first storage index vector is the parallel index corresponding to each element in the data vector to be written A vector composed of indexes of each storage subunit in the memory; the first storage address vector is a vector composed of addresses in each storage subunit corresponding to each element in the data vector to be written;

According to the first storage index vector, reorder the write data enable vector, the first storage address vector and the to-be-written data vector, and according to the reordered write data enable The vector and the first storage address vector store the reordered data vector to be written into the parallel memory.

According to the second aspect of the present invention, a data parallel reading method is provided, including:

Transform the read data index of the data vector to be read into a one-dimensional read address; wherein, the data vector to be read is a one-dimensional or multi-dimensional vector in the multidimensional data matrix to be read; the read data The index is the index of the first element to be read among all the elements of the data vector to be read in the multidimensional data matrix to be read;

Acquire the read data enable vector, the second storage index vector, and the second storage address vector of the data vector to be read according to the one-dimensional read address and the preset number of read data; wherein, the read Each element in the data enable vector is used to indicate whether the element at the corresponding position in the data vector to be read is read; the second storage index vector is the data vector to be read for each element in the parallel memory The vector formed by the index of each storage subunit; the second storage address vector is a vector formed by the address of each element in the data vector to be read in each storage subunit;

According to the second storage index vector, reorder the read data enable vector and the second storage address vector, and according to the reordered read data enable vector and the second storage address The vector reads the stored data vectors from the parallel memory, reorders the stored data vectors according to the second stored index vector, and acquires the to-be-read data vectors.

According to a third aspect of the present invention, a data parallel writing device is provided, including:

The first conversion module is used to convert the write data index of the data vector to be written into a one-dimensional write address; wherein, the data vector to be written is a one-dimensional or multi-dimensional data matrix to be written Vector, the write data index is the index of the first element to be written in the multidimensional data matrix to be written in the multidimensional data matrix to be written among all the elements of the data vector to be written ;

A first acquisition module, configured to acquire a write data enable vector, a first storage index vector, and a first storage address of the data vector to be written according to the one-dimensional write address and the preset number of write data Vector; wherein, each element in the write data enable vector is used to indicate whether the element at the corresponding position in the data vector to be written is written; the first storage index vector is the data to be written A vector composed of indexes of each storage subunit in the parallel memory corresponding to each element in the vector; the first storage address vector is composed of addresses in each storage subunit corresponding to each element in the data vector to be written vector;

A storage module, configured to reorder the write data enable vector, the first storage address vector, and the data vector to be written according to the first storage index vector, and according to the reordered The write data enable vector and the first storage address vector store the reordered data vector to be written into the parallel memory.

According to a fourth aspect of the present invention, a data parallel reading device is provided, including:

The second conversion module is used to convert the read data index of the data vector to be read into a one-dimensional read address; wherein, the data vector to be read is a one-dimensional or multi-dimensional data matrix to be read Vector, the read data index is the index of the first element to be read among all the elements of the data vector to be read in the multidimensional data matrix to be read;

A second acquisition module, configured to acquire the read data enable vector, the second storage index vector, and the second storage address of the data vector to be read according to the one-dimensional read address and the preset number of read data Vector; wherein, each element in the read data enable vector is used to indicate whether the element at the corresponding position in the data vector to be read is read; the second storage index vector is the data to be read A vector formed by indexes of each storage subunit in the parallel memory corresponding to each element in the vector; the second storage address vector is formed by addresses in each storage subunit corresponding to each element in the data vector to be read vector;

A reading module, configured to reorder the read data enable vector and the second storage address vector according to the second storage index vector, and reorder the read data enable vector and the second storage address vector according to the reordered read data enable vector and The second storage address vector reads the storage data vector from the parallel memory, reorders the storage data vector according to the second storage index vector, and acquires the to-be-read data vector.

According to the fifth aspect of the present invention, a data parallel reading and writing system is provided, including:

A parallel memory, and the above-mentioned data parallel writing device and the above-mentioned data parallel reading device.

The present invention provides a data parallel writing and reading method, device and system. The method transforms the written data index of the data vector to be written into a one-dimensional writing address, and according to the one-dimensional writing address and the preset writing Enter the number of data, obtain the write data enable vector, the first storage index vector and the first storage address vector of the data vector to be written, and according to the first storage index vector, write the data enable vector, The first storage address vector and the data vector to be written are reordered, and the reordered data to be written is reordered according to the reordered write data enable vector and the first storage address vector. The data vectors are stored in the parallel memory, thereby supporting parallel writing of data from one or more dimensions, and improving the flexibility and writing efficiency of data writing.

Description of drawings

FIG. 1 is a schematic diagram of the overall flow of a data parallel writing method provided by an embodiment of the present invention;

2 is a schematic diagram of parallel writing of four-dimensional data vectors to be written in two dimensions in the data parallel writing method provided by the embodiment of the present invention;

3 is a schematic diagram of parallel writing of four-dimensional data vectors to be written in one dimension in the data parallel writing method provided by the embodiment of the present invention;

FIG. 4 is a schematic diagram of converting a written data index into a one-dimensional written address in a data parallel writing method provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram of the write reordering network structure in the data parallel writing method provided by the embodiment of the present invention;

FIG. 6 is a schematic diagram of the overall flow of a data parallel reading method provided by an embodiment of the present invention;

7 is a schematic diagram of the overall structure of a data parallel writing device provided by an embodiment of the present invention;

FIG. 8 is a schematic diagram of an overall structure of a data parallel reading device provided by an embodiment of the present invention.

Detailed ways

The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

In one embodiment of the present invention, a data parallel writing method is provided. FIG. 1 is a schematic diagram of the overall flow of the data parallel writing method provided by the embodiment of the present invention. The method includes: S101, writing the data vector to be written The data index is converted into a one-dimensional write address; wherein, the data vector to be written is a one-dimensional or multi-dimensional vector in the multidimensional data matrix to be written, and the write data index is all elements of the data vector to be written The index of the first element to be written in the multidimensional data matrix to be written The index in the multidimensional data matrix to be written;

Wherein, the data vector to be written is a data vector that needs to be written in parallel. The write data index is the index of the first element to be written in the data vector to be written in the multidimensional data matrix to be written. The element to be written is an element that needs to be written. Under the control of the control signal w_ctrl0 and w_ctrl1, the write data index is converted to generate a one-dimensional write address. For example, the data vector to be written is a four-dimensional vector [dim3, dim2, dim1, dim0], where dim3, dim2, dim1 and dim0 represent different dimensions. The sizes of the data vectors to be written in each dimension are DIM3, DIM2, DIM1 and DIM0 respectively. The maximum number of data to be written in parallel is S, and the data vector W_DATA to be written is a vector with a length of N. Continuous writing is performed from two dimensions of dim1 and dim0, as shown in Figure 2. When performing parallel continuous writing from two dimensions, two parameters need to be defined, namely, the maximum number of parallel reads and writes K in the dimension dim1 and the maximum number L of parallel reads and writes in the dimension dim0, where K*L=S. The form of parallel continuous writing from one dimension of dim0 is shown in FIG. 3 , in this case L=S, K=0.

S102. According to the one-dimensional write address and the preset number of write data, obtain the write data enable vector, the first storage index vector and the first storage address vector of the data vector to be written; wherein, the write data enable Each element in the vector is used to indicate whether the element at the corresponding position in the data vector to be written is written; the first storage index vector is formed by the index of each storage subunit in the parallel memory corresponding to each element in the data vector to be written The vector; the first storage address vector is a vector composed of addresses in each storage subunit corresponding to each element in the data vector to be written;

Wherein, the preset number of written data W_M is the number of elements to be written in the data vector to be written. Calculate according to the one-dimensional write address w_base and the preset number of write data W_M, and obtain the write data enable vector, the first storage index vector and the first storage address vector of the data vector to be written. Wherein, the write data enable vector, the first storage index vector and the first storage address vector are respectively vectors with a length equal to N. Each element in the write data enable vector W_BE is 0 or 1, which is used to indicate whether the element at the corresponding position in the data vector W_DATA to be written is written, wherein 1 means write, and 0 means not write. The first storage index vector W_BI is a vector composed of indexes of storage subunits in the parallel memory corresponding to each element in the data vector W_DATA to be written. The first storage address vector W_BA is a vector composed of addresses in each storage subunit where the data vector W_DATA to be written will be stored.

S103. Reorder the write data enable vector, the first storage address vector, and the data vector to be written according to the first storage index vector, and reorder the write data enable vector and the first storage address vector according to the reordered write data enable vector and the first storage address vector. The reordered data vectors to be written are stored in the parallel memory.

Specifically, the write data enable vector, the first storage address vector and the data vector to be written are input into the write reordering network, and according to the first storage index vector, the write data enable vector W_BE, the first storage address vector W_BA and the data vector W_DATA to be written are reordered to obtain the reordered write data enable vector W_BE_R, the first storage address vector W_BA_R and the data vector W_DATA_R to be written. Among them, W_BA_R is the address of each element corresponding to each storage subunit to be stored in the data vector to be written, W_BE_R is the enable vector of whether each storage subunit is enabled, and W_DATA_R is the corresponding to be stored in each storage subunit. Write to the elements in the data vector.

In this embodiment, the write data index of the data vector to be written is converted into a one-dimensional write address, and the write data enable of the data vector to be written is obtained according to the one-dimensional write address and the preset number of write data Vector, the first storage index vector and the first storage address vector, according to the first storage index vector, the write data enable vector, the first storage address vector and the data vector to be written are reordered, and according to the reordered write The input data enable vector and the first storage address vector store the reordered data vectors to be written into the parallel memory, thereby supporting data to be written in parallel from one or more dimensions, improving the flexibility of data writing and writing input efficiency.

On the basis of the above embodiments, step S101 in this embodiment specifically includes: reordering the written data indexes, and decomposing the index values corresponding to the preset dimensions that are written in parallel in the reordered written data indexes respectively. Divided into multiple index values;

For example, as shown in Fig. 4, under the control of w_ctrl0, the written data indexes [dim0, dim1, dim2, dim3] are reordered to obtain the reordered written data indexes [dimnp1, dimnp0, dimp1, dimp0]. Among them, dimp1 and dimp0 are the two dimensions for parallel writing, dimnp1 and dimnp0 are the two dimensions that do not need to be written in parallel, and the sizes of the four dimensions of the data vectors to be written dimnp1, dimnp0, dimp1 and dimp0 are DIMNP1 respectively , DIMNP0, DIMP1, and DIMP0.

Define the maximum number of parallel writes for the two parallel write dimensions of dimp1 and dip0 to be K and L respectively. K and L can be set according to the performance of the parallel memory. Split dimp1 into two dimensions according to K, namely dim1_p and dim1_b. Among them, dim1_p=dimp1%K, dim1_b=dimp1//K. The size of the data vector to be written in the dimension dim1_p is DIM1_P=K, and the size in the dimension dim1_b is DIM1_B=DIMP1//K. Split dimp0 into two dimensions according to L, namely dim0_p and dim0_b. Among them, dim0_p=dimp0%L, dim0_b=dimp0//L. The dimension of the data vector to be written is DIM0_P=L on the dimension dim0_p, and the dimension on the dimension dim0_b is DIM0_B=DIMP1//L. At this time, the data vector to be written is split from four dimensions to six dimensions, and the index of the split write data is [dimnp1, dimnp0, dimp1_b, dimp1_p, dimp0_b, dimp0_p]. The sizes of the data vectors to be written in each dimension are DIMNP1, DIMNP0, DIMP1_B, DIMP1_P, DIMP0_B, and DIMP0_P.

Under the control of w_ctrl1, the split write data index is reordered again, and the one-dimensional write address is obtained by calculating according to the reordered write data index.

For example, reorder the split write data index [dimnp1,dimnp0,dimp1_b,dimp1_p,dimp0_b,dimp0_p] to get the reordered write data index [dnp3,dnp2,dnp1,dnp0,dp1,dp0 ]. Among them, dp1=dimp1_p, dp0=dimp0_p. dnp3, dnp2, dnp1, and dnp0 are reordered by dimnp1, dimnp0, dimp1_b, and dimp0_b. The sizes of the data vectors to be written in the corresponding dimensions after reordering are DNP3, DNP2, DNP1, DNP0, DP1, and DP0, which are obtained by performing the same reordering on DIMNP1, DIMNP0, DIMP1_B, DIMP1_P, DIMP0_B, and DIMP0_P. obtained by reordering. Calculated based on the reordered write data index, the formula for obtaining the one-dimensional write address w_base is:

w_base=dp0+dp1*DP0+dnp0*DP0*DP1+dnp1*DP0*DP1*DNP0+dnp2*DP0*DP1*DNP0*DNP1+dnp3*DP0*DP1*DNP0*DNP1*DNP1. This embodiment is not limited to the dimension of the data vector to be written, the dimension to which the data is split, and the dimension to which the data is split, nor is it limited to the dimension not to be reordered when reordering is performed.

On the basis of the above-mentioned embodiments, in this embodiment, according to the one-dimensional write address and the number of preset write data, the write data enable vector, the first storage index vector and the first storage index vector of the data vector to be written are obtained. The step of addressing the vector specifically includes: according to the preset number of written data, determining the number of elements with a value of 1 in the write data enable vector, and according to the length of the data vector to be written and the preset number of written data, Determine the number of elements with a value of 0 in the write data enable vector; according to the index of each element in the data vector to be written in the data vector to be written, the one-dimensional write address and the The length of the data vector, get the first storage index vector and the first storage address vector.

Specifically, according to W_M, a mathematical representation of the write data enable vector W_BE can be obtained: W_BE=[W_M{1}, (N−W_M){0}]. That is, the first W_M elements in the data vector W_DATA to be written are written, and other elements in W_DATA are not written. The calculation formula of the first storage index vector W_BI is: W_BI=(w_base+[0, 1, 2, . . . , N−1])%N. The formula for calculating the first storage address vector W_BA is: W_BA=(w_base+[0, 1, 2, . . . , N−1])//N.

On the basis of the above-mentioned embodiments, in this embodiment, according to the first storage index vector, the step of reordering the write data enable vector, the first storage address vector and the data vector to be written specifically includes: according to the first Store the index vector, and obtain the write data index vector formed by the index of the element corresponding to the index of each storage subunit in the data vector to be written; according to the write data index vector, the write data enable vector, the first storage The address vector and the data vector to be written are reordered.

Specifically, the write data index vector W_BI_R is a vector corresponding to W_BI, which represents an index vector formed by the index of the element to be written in each storage subunit in the parallel memory in the data vector W_DATA to be written, and the vector can be passed through W_BI Calculated, the formula is: W_BI_R=(N-W_BI[0]+[0,1,2,...,N-1])%N. The write data enable vector W_BE, the first storage address vector W_BA and the data to be written vector W_DATA are reordered according to the write data index vector W_BI_R. In the write reordering network, W_BE, W_BA, and W_DATA are independently reordered according to W_BI_R, and the structural diagram of the write reordering network is shown in Figure 5.

For example, the data vector [dim3, dim2, dim1, dim0] to be written needs to be written into a parallel memory composed of 4 storage sub-units, that is, N=4. The sizes of the data vectors to be written in each dimension correspond to DIM3=12, DIM2=10, DIM1=8, and DIM0=6. The index values of the written data index on the four dimensions are interleaved under the control of w_ctrl0, and the relationship between output and input is: dimnp1=dim1, dimnp0=dim0, dimp1=dim3, dimp0=dim2. The sizes of the data vectors to be written in each dimension are DIMNP1=DIM1=8, DIMNP0=DIM0=6, DIMP1=DIM3=12, DIMP0=DIM2=10. The maximum numbers of parallel reads and writes in the two dimensions of dip1 and dip0 are respectively K=2 and L=2. Dimp1 and dip0 are divided into two dimensions according to K and L respectively, and the following is obtained: dimp1_b=dimp1//K, dimp1_p=dimp1%K, dimp0_b=dimp0//L, dimp0_p=dimp0%L. The dimensions of the data vector to be written after splitting are DIMP1_B=DIMP1//K=6, DIMP1_P=K=2, DIMP0_B=DIMP0//L=5, DIMP0_P=L=2. Dimp1_p and dimp0_p in the six dimension data dimnp1, dimnp0, dimp1_b, dimp1_p, dimp0_b, and dimp0_p obtained after splitting are directly used as dp1 and dp0 in the final six dimensions; dimnp1, dimnp0, dimp1_b, and dimp0_b should be placed in the Interleaving is performed under control, and the relationship between output and input is: dnp3=dimp1_b, dnp2=dimnp0_b, dnp1=dimnp1, dnp0=dimnp0. The size of the data vector to be written in each dimension is DNP3=DIMP1_B=6, DNP2=DIMP0_B=5, DNP1=DIMNP1=8, DNP0=DIMNP0=6, DP1=DIMP1_P=2, DP0=DIMP0_P=2.

When the written data index w_index=[0,2,0,0], the number of preset data written W_M=4, and the data vector to be written W_DATA=[6,7,8,9], the data is written in parallel The process is as follows:

Calculate w_base according to the written data index w_index, namely:

w_base=dp0_p+dp1*DP0+dnp0*DP0*DP1+dnp1*DP0*DP1*DNP0+dnp2*DP0*DP1*DNP0*DNP1+dnp3*DP0*DP1*DNP0*DNP1*DNP1=2.

According to w_base and W_M, calculate W_BE, W_BA and W_BI_R, namely:

W_BE=[W_M{1},(N-W_M){0}]=[1,1,1,1];

W_BI=(w_base+[0,1,2,...,N-1])%N=[2,3,0,1];

W_BI_R=(N-W_BI[0]+[0,1,2,...,N-1])%N=[2,3,0,1];

W_BA=(w_base+[0,1,2,...,N-1])//N=[0,0,1,1];

The W_BE, W_BA and W_DATA inputs are written to the reordering network, and under the control of W_BI_R, the output is:

W_BE_R=[1,1,1,1];

W_BA_R=[1,1,0,0];

W_DATA_R=[8,9,6,7].

The data vectors to be written are written in parallel according to W_BE_R, W_BA_R and W_BA_R. Since each element in the W_BE_R vector is 1, all storage subunits are enabled, W_BA_R gives the address of each storage subunit, and W_DATA_R gives the data to be stored in each storage subunit.

In another embodiment of the present invention, a data parallel reading method is provided. FIG. 6 is a schematic diagram of the overall flow of the data parallel reading method provided by the embodiment of the present invention. The method includes: S601, read the data vector to be read Take the data index and transform it into a one-dimensional read address; wherein, the data vector to be read is a one-dimensional or multi-dimensional vector in the multidimensional data matrix to be read, and the read data index is all elements of the data vector to be read The index of the first element to be read in the multidimensional data matrix to be read;

Wherein, the data vector to be read is a data vector that needs to be read in parallel. The read data index is the index of the first to-be-read element in the to-be-read data vector in the multi-dimensional data matrix to be read. The element to be read is an element that needs to be read. Under the control of the control signals r_ctrl0 and r_ctrl1, the read data index is converted to generate a one-dimensional read address. The one-dimensional read address generation method is the same as the one-dimensional write address generation method.

S602. According to the one-dimensional read address and the preset number of read data, obtain the read data enable vector, the second storage index vector and the second storage address vector of the data vector to be read; wherein, the read data enable Each element in the vector is used to indicate whether the element at the corresponding position in the data vector to be read is read; the second storage index vector is formed by the index of each storage subunit of each element in the data vector to be read in the parallel memory Vector; the second storage address vector is a vector formed by the address of each element in each storage subunit in the data vector to be read;

Wherein, the preset number of read data is the number of elements to be read in the data vector to be read. Calculate according to the one-dimensional read address R_base and the preset number of read data R_M to obtain the read data enable vector, the second storage index vector and the second storage address vector of the data vector to be read. Wherein, the read data enable vector, the second storage index vector and the second storage address vector are respectively vectors with a length equal to N. Each element in the read data enable vector R_BE is 0 or 1, which is used to indicate whether to read the element at the corresponding position in the data vector R_DATA to be read, wherein 1 means read, and 0 means not read. The second storage index vector R_BI is a vector composed of indexes of storage subunits in the parallel memory for each element in the data vector R_DATA to be read. The second storage address vector R_BA is a vector formed by reading the address of each element in the data vector R_DATA to be read in each storage subunit.

S603, reorder the read data enable vector and the second storage address vector according to the second storage index vector, and read the stored data from the parallel memory according to the reordered read data enable vector and the second storage address vector A vector, reordering the stored data vectors according to the second stored index vector, to obtain the data vectors to be read.

Specifically, the read data enable vector, the second storage address vector and the data vector to be read are input into the read reordering network, and the read data enable vector R_BE and the second storage address vector are read according to the second storage index vector R_BI R_BA performs reordering, and acquires the reordered read data enable vector R_BE_R and the second storage address vector R_BA_R. Wherein R_BA_R is the address of each element in the pre-stored data vector to be read to be read in each storage subunit, and R_BE_R is the enablement of whether to read each element in the pre-stored data vector to be read in each storage subunit vector. The stored data vector R_DATA_R is read from the parallel memory according to R_BE_R and R_BA_R. The order of each element in R_DATA_R is arranged according to the order of the storage subunits, which is the same as the value of the elements in the data vector R_DATA to be read but the order is different. R_DATA_R is reordered according to the second storage index vector R_BI to obtain R_DATA.

In this embodiment, the read data index of the data vector to be read is converted into a one-dimensional read address, and the write data enable of the data vector to be read is obtained according to the one-dimensional read address and the preset number of read data Vector, the second storage index vector and the second storage address vector, according to the second storage index vector, the write data enable vector and the first storage address vector are reordered, according to the reordered read data enable vector and The second storage address vector reads the storage data vector from the parallel memory, reorders the storage data vector according to the second storage index vector, and obtains the data vector to be read, thereby supporting parallel reading of data from one or more dimensions, Improve the flexibility of data reading and writing efficiency.

On the basis of the above embodiments, step S601 in this embodiment specifically includes: the step of transforming the read data index of the data vector to be read into a one-dimensional read address specifically includes: reordering the read data index, and In the reordered read data index, the index values corresponding to the preset dimensions that are read in parallel are split into multiple index values; Take the data index for calculation and obtain the one-dimensional read address.

For example, reorder the read data indexes [dim0, dim1, dim2, dim3] under the control of r_ctrl0 to obtain the reordered read data indexes [dimnp1, dimnp0, dimp1, dimp0]. Among them, dimp1 and dimp0 are the two dimensions of parallel reading, dimnp1 and dimnp0 are the two dimensions that do not need to be read in parallel, and the sizes of the four dimensions of the data vector dimnp1, dimnp0, dimp1 and dimp0 to be read are respectively DIMNP1 , DIMNP0, DIMP1, and DIMP0.

Define the maximum number of parallel reads for the two parallel read dimensions of dimp1 and dip0 to be K and L respectively. K and L can be set according to the performance of the parallel memory. Split dimp1 into two dimensions according to K, namely dim1_p and dim1_b. Among them, dim1_p=dimp1%K, dim1_b=dimp1//K. The dimension of the data vector to be read is DIM1_P=K on the dimension dim1_p, and the dimension on the dimension dim1_b is DIM1_B=DIMP1//K. Split dimp0 into two dimensions according to L, namely dim0_p and dim0_b. Among them, dim0_p=dimp0%L, dim0_b=dimp0//L. The size of the data vector to be read on the dimension dim0_p is DIM0_P=L, and the size on the dimension dim0_b is DIM0_B=DIMP1//L. At this time, the data vector to be read is split from four dimensions into six dimensions, and the read data index after splitting is [dimnp1, dimnp0, dimp1_b, dimp1_p, dimp0_b, dimp0_p]. The sizes of the data vectors to be read in each dimension are DIMNP1, DIMNP0, DIMP1_B, DIMP1_P, DIMP0_B, and DIMP0_P.

The split read data indexes are reordered again, and calculation is performed based on the reordered read data indexes to obtain a one-dimensional read address.

For example, reorder the split read data indexes [dimnp1,dimnp0,dimp1_b,dimp1_p,dimp0_b,dimp0_p] under the control of r_ctrl1 to get the reordered read data indexes [dnp3,dnp2,dnp1, dnp0,dp1,dp0]. Among them, dp1=dimp1_p, dp0=dimp0_p. dnp3, dnp2, dnp1, and dnp0 are reordered by dimnp1, dimnp0, dimp1_b, and dimp0_b. The sizes of the data vectors to be read in the corresponding dimensions after reordering are DNP3, DNP2, DNP1, DNP0, DP1, and DP0, which are obtained by performing the same reordering on DIMNP1, DIMNP0, DIMP1_B, DIMP1_P, DIMP0_B, and DIMP0_P. obtained by reordering. Calculated based on the reordered read data index, the formula for obtaining the one-dimensional read address w_base is:

w_base=dp0+dp1*DP0+dnp0*DP0*DP1+dnp1*DP0*DP1*DNP0+dnp2*DP0*DP1*DNP0*DNP1+dnp3*DP0*DP1*DNP0*DNP1*DNP1. This embodiment is not limited to the dimension of the data vector to be read, the dimension into which the data is split, and the dimension into which the data is split, nor is it limited to the dimension in which reordering is not performed when reordering is performed.

On the basis of the above embodiments, in this embodiment, according to the one-dimensional read address and the preset number of read data, the read data enable vector, the second storage index vector and the second storage index vector of the data vector to be read are obtained. The steps of the address vector specifically include:

Determine the number of elements with a value of 1 in the read data enable vector according to the preset number of read data, and determine the read value according to the difference between the length of the data vector to be read and the preset number of read data. Get the number of elements whose value is 0 in the data enable vector; according to the index of each element in the data vector to be read, the one-dimensional read address and the length of the data vector to be read, obtain the first A second storage index vector and a second storage address vector.

Specifically, according to R_M, a mathematical representation of the read data enable vector R_BE can be obtained: R_BE=[R_M{1}, (N−R_M){0}]. That is, the first R_M elements in the data vector R_DATA to be read are written, and other elements in R_DATA are not read. The calculation formula of the second storage index vector R_BI is: R_BI=(r_base+[0, 1, 2, . . . , N−1])%N. The formula for calculating the second storage address vector R_BA is: R_BA=(r_base+[0, 1, 2, . . . , N−1])//N.

On the basis of the above embodiments, in this embodiment, according to the second storage index vector, the step of reordering the read data enable vector and the second storage address vector specifically includes: according to the second storage index vector, obtaining each storing the read data index vector formed by the index of the element corresponding to the index of the subunit in the data vector to be read; reordering the read data enable vector and the second storage address vector according to the read data index vector.

Specifically, the read data index vector R_BI_R is a vector corresponding to R_BI, which represents an index vector formed by the index of the element to be read by each storage subunit in the parallel memory in the data vector R_DATA to be read, and the vector can be passed through R_BI Calculated, the formula is: R_BI_R=(N-R_BI[0]+[0,1,2,...,N-1])%N. The write data enable vector R_BE and the second storage address vector R_BA are reordered according to the read data index vector R_BI_R. In the read reordering network, R_BE and R_BA are independently reordered according to R_BI_R, and the structure of the read reordering network is the same as that of the writing reordering network. The stored data vector R_DATA_R is read from the parallel memory according to R_BE_R and R_BA_R. The order of each element in R_DATA_R is arranged according to the order of the storage subunits, which is the same as the value of the elements in the data vector R_DATA to be read but the order is different. Reorder R_DATA_R according to R_BI to obtain R_DATA.

For example, read the data vector W_DATA=[6, 7, 8, 9] to be written into the parallel memory listed in the above embodiment. That is, when the data vector to be read is R_DATA=[6,7,8,9], the read data index r_dex=[0,2,0,0], the preset number of read data R_M=4, and the data is read in parallel The process is as follows:

Calculate r_base according to the read data index r_index, namely:

r_base=dp0_p+dp1*DP0+dnp0*DP0*DP1+dnp1*DP0*DP1*DNP0+dnp2*DP0*DP1*DNP0*DNP1+dnp3*DP0*DP1*DNP0*DNP1*DNP1=2.

According to r_base and R_M, calculate R_BE, R_BA and R_BI_R, namely:

R_BE=[R_M{1},(N-R_M){0}]=[1,1,1,1];

R_BI=(r_base+[0,1,2,...,N-1])%N=[2,3,0,1];

R_BI_R=(N-R_BI[0]+[0,1,2,...,N-1])%N=[2,3,0,1];

R_BA=(r_base+[0,1,2,...,N-1])//N=[0,0,1,1];

r_BE and r_BA input read reordering network, under the control of R_BI_R, the output is:

R_BE_R=[1,1,1,1];

R_BA_R=[1,1,0,0];

Read storage data vector R_DATA_R from parallel memory according to R_BE_R and R_BA_R and W_BA_R. Since each element in the R_BE_R vector is 1, all storage subunits are enabled, R_BA_R gives the address of each storage subunit, and the read data is R_DATA_R=[8,9,6,7]. R_DATA_R has the same values as the elements in R_DATA, but in a different order and needs to be reordered. Reorder R_DATA_R under the control of R_BI to get R_DATA.

In another embodiment of the present invention, a data parallel writing device is provided, refer to FIG. 7 . The device is used to implement the above embodiments of the data parallel writing method. Therefore, the descriptions and definitions in the data parallel writing methods in the foregoing embodiments can be used for the understanding of each execution module in the embodiments of the present invention.

The data parallel writing device includes: a first conversion module 701 for converting the write data index of the data vector to be written into a one-dimensional write address; wherein, the data vector to be written is a multidimensional data matrix to be written A one-dimensional or multidimensional vector in , the write data index is the index of the first element to be written in the multidimensional data matrix to be written among all elements of the data vector to be written; the first acquisition module 702 is used for according to The one-dimensional write address and the number of preset write data are used to obtain the write data enable vector, the first storage index vector and the first storage address vector of the data vector to be written; wherein, the write data in the enable vector Each element is used to indicate whether the element at the corresponding position in the data vector to be written is written; the first storage index vector is a vector composed of indexes of each storage subunit in the parallel memory corresponding to each element in the data vector to be written; The first storage address vector is a vector composed of addresses in each storage subunit corresponding to each element in the data vector to be written; the storage module 703 is used to enable the write data vector, the first storage index vector according to the first storage index vector A storage address vector and the data vector to be written are reordered, and the reordered data vector to be written is stored in the parallel memory according to the reordered write data enable vector and the first storage address vector.

On the basis of the above embodiments, the first transformation module in this embodiment is specifically used to: reorder the written data indexes, and reorder the indexes corresponding to the preset dimensions that are written in parallel in the reordered written data indexes The value is split into multiple index values respectively; the split write data index is reordered again, and calculation is performed based on the reordered write data index to obtain a one-dimensional write address.

On the basis of the above embodiments, the first acquisition module in this embodiment is specifically configured to: determine the number of elements with a value of 1 in the write data enable vector according to the preset number of write data, and determine the number of elements with a value of 1 in the write data enable vector according to The difference between the length of the data vector and the number of preset write data determines the number of elements whose value is 0 in the write data enable vector; The index in, the one-dimensional write address and the length of the data vector to be written are used to obtain the first storage index vector and the first storage address vector.

On the basis of the above-mentioned embodiments, the writing module in this embodiment is specifically configured to: obtain the index of the element corresponding to the index of each storage subunit in the data vector to be written according to the first storage index vector. Entering the data index vector; reordering the write data enable vector, the first storage address vector and the data vector to be written according to the write data index vector.

By transforming the write data index of the data vector to be written into a one-dimensional write address, according to the one-dimensional write address and the preset number of write data, the write data enable vector and the first data vector of the data vector to be written are obtained A storage index vector and a first storage address vector, according to the first storage index vector, the write data enable vector, the first storage address vector and the data vector to be written are reordered, and according to the reordered write data use The energy vector and the first storage address vector store the reordered data vectors to be written into the parallel memory, thereby supporting parallel writing of data from one or more dimensions, and improving the flexibility and writing efficiency of data writing.

In another embodiment of the present invention, a device for reading data in parallel is provided, refer to FIG. 8 . The device is used to implement the above embodiments of the data parallel reading method. Therefore, the descriptions and definitions in the data parallel reading methods in the foregoing embodiments can be used to understand each execution module in the embodiments of the present invention.

The data parallel writing device includes: a second transformation module 801 for transforming the read data index of the data vector to be read into a one-dimensional read address; wherein, the data vector to be read is a multidimensional data matrix to be read A one-dimensional or multidimensional vector in , the read data index is the index of the first element to be read in the multidimensional data matrix to be read among all elements of the data vector to be read; the second acquisition module 802 is used for according to The one-dimensional read address and the preset number of read data obtain the read data enable vector, the second storage index vector and the second storage address vector of the data vector to be read; wherein, the read data enable vector Each element is used to indicate whether the element at the corresponding position in the data vector to be read is read; the second storage index vector is a vector formed by indexes of each storage subunit in the parallel memory corresponding to each element in the data vector to be read; The second storage address vector is a vector composed of addresses in each storage subunit corresponding to each element in the data vector to be read; the reading module 803 is used to enable the read data vector and the second storage index vector according to the second storage index vector The two storage address vectors are reordered, and the storage data vectors are read from the parallel memory according to the reordered read data enable vector and the second storage address vector, and the storage data vectors are reordered according to the second storage index vector to obtain the pending Read the data vector.

On the basis of the above embodiments, the second transformation module in this embodiment is specifically used to: reorder the read data indexes, and reorder the indexes corresponding to the preset dimensions that are read in parallel in the reordered read data indexes The values are split into multiple index values; the read data indexes after splitting are reordered again, and the one-dimensional read address is obtained by calculating according to the reordered read data indexes.

On the basis of the above embodiments, the second acquisition module in this embodiment is specifically configured to: determine the number of elements with a value of 1 in the read data enable vector according to the preset number of read data, and determine the number of elements with a value of 1 in the read data enable vector according to the The difference between the length of the data vector and the preset number of read data determines the number of elements whose value is 0 in the read data enable vector; The index, the one-dimensional read address and the length of the data vector to be read obtain the second storage index vector and the second storage address vector.

On the basis of the above-mentioned embodiments, the reading module in this embodiment is specifically configured to: obtain the index of the element corresponding to the index of each storage subunit in the data vector to be read according to the second storage index vector. The data index vector is fetched; according to the read data index vector, the read data enable vector and the second storage address vector are reordered.

In this embodiment, the read data index of the data vector to be read is converted into a one-dimensional read address, and the write data enable of the data vector to be read is obtained according to the one-dimensional read address and the preset number of read data Vector, the second storage index vector and the second storage address vector, according to the second storage index vector, the write data enable vector and the first storage address vector are reordered, according to the reordered read data enable vector and The second storage address vector reads the storage data vector from the parallel memory, reorders the storage data vector according to the second storage index vector, and obtains the data vector to be read, thereby supporting parallel reading of data from one or more dimensions, Improve the flexibility of data reading and writing efficiency.

In another embodiment of the present invention, a data parallel reading and writing system is provided, the data parallel reading and writing system includes a parallel memory, any data parallel writing device in the embodiments of the above-mentioned data parallel writing devices, and the above-mentioned data Any data parallel reading device in the parallel reading device embodiment.

Finally, the method of the present application is only a preferred embodiment, and is not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (11)

1. a kind of data parallel wiring method characterized by comprising

The write-in data directory for being written into data vector is transformed to one-dimensional writing address；Wherein, the data vector to be written For an one or more dimensions vector in multidimensional data matrix to be written, said write data directory is the data to be written Index of first element to be written in the multidimensional data matrix to be written in all elements of vector；

According to the one-dimensional writing address and default write-in data amount check, the write-in data for obtaining the data vector to be written make It can vector, the first storage index vector and the first storage address vector；Wherein, said write data enable each member in vector Element is for indicating whether the element of corresponding position in the data vector to be written is written；The first storage index vector is institute State the vector that the index of each storing sub-units in the corresponding parallel storage of each element in data vector to be written is constituted；It is described First storage address vector is made of the address in the data vector to be written in the corresponding each storing sub-units of each element Vector；

According to the first storage index vector, vector, the first storage address vector sum institute are enabled to said write data It states data vector to be written to reorder, enables the first storage ground described in vector sum according to the said write data after reordering The data vector to be written after location vector will reorder is stored in the parallel storage.

2. the method according to claim 1, wherein the write-in data directory for being written into data vector is transformed to The step of one-dimensional writing address, specifically includes:

It reorders to said write data directory, it is each by being written in parallel in the said write data directory to reorder The default corresponding index value of dimension is split as multiple index values respectively；

It reorders again to the said write data directory after fractionation, according to the said write data directory to reorder again It is calculated, obtains the one-dimensional writing address.

3. the method according to claim 1, wherein according to the one-dimensional writing address and default write-in data Number, obtain the data vector to be written write-in data enable vector, the first storage index vector and the first storage address to The step of amount, specifically includes:

According to the default write-in data amount check, determine that said write data enable the number for the element that vector intermediate value is 1, according to Difference between the length of the data vector to be written and the default write-in data amount check, determines that said write data are enabled The number for the element that vector intermediate value is 0；

According to index, the one-dimensional write-in ground of each element in the data vector to be written in the data vector to be written The length of location and the data vector to be written obtains the first storage index vector and the first storage address vector.

4. method according to claim 1 to 3, which is characterized in that according to the first storage index vector, to institute State the step of write-in data enable vector, data vector to be written described in the first storage address vector sum is reordered tool Body includes:

According to the first storage index vector, the corresponding element of index of each storing sub-units is obtained described to be written The write-in data directory vector that index in data vector is constituted；

According to said write data directory vector, vector, the first storage address vector sum institute are enabled to said write data Data vector to be written is stated to reorder.

5. a kind of data parallel read method characterized by comprising

The reading data directory of data vector to be read is transformed to one-dimensional reading address；Wherein, the data vector to be read For an one or more dimensions vector in multidimensional data matrix to be read, the reading data directory is the data to be read Index of first element to be read in the multidimensional data matrix to be read in all elements of vector；

According to the one-dimensional reading address and default reading data amount check, the reading data for obtaining the data vector to be read make It can vector, the second storage index vector and the second storage address vector；Wherein, each member read in the enabled vector of data Element is for indicating whether the element of corresponding position in the data vector to be read reads；The second storage index vector is institute State each element vector that the index of each storing sub-units is constituted in parallel storage in data vector to be read；Described second Storage address vector by address of each element in each storing sub-units in the data vector to be read constitute to Amount；

According to the second storage index vector, the second storage address vector described in vector sum is enabled to the reading data and is carried out It reorders, enables the second storage address vector described in vector sum from the parallel memorizing according to the reading data after reordering Storing data vector is read in device, is reordered, is obtained to the storing data vector according to the second storage index vector Take the data vector to be read.

6. according to the method described in claim 5, it is characterized in that, the reading data directory of data vector to be read is transformed to The step of one-dimensional reading address, specifically includes:

It reorders to the reading data directory, it is each by being read parallel in the reading data directory to reorder The default corresponding index value of dimension is split as multiple index values respectively；

It reorders again to the reading data directory after fractionation, according to the reading data directory to reorder again It is calculated, obtains the one-dimensional reading address.

7. according to the method described in claim 5, it is characterized in that, according to the one-dimensional reading address and default reading data Number, obtain the data vector to be read reading data enable vector, the second storage index vector and the second storage address to The step of amount, specifically includes:

According to the default reading data amount check, determine that the reading data enable the number for the element that vector intermediate value is 1, according to The length of the data vector to be read and the default difference read between data amount check, determine that the reading data are enabled The number for the element that vector intermediate value is 0；

According to index, the one-dimensional reading ground of each element in the data vector to be read in the data vector to be read The length of location and the data vector to be read obtains the second storage index vector and the second storage address vector.

8. according to any method of claim 5-7, which is characterized in that according to the second storage index vector, to institute The step of the second storage address vector described in the enabled vector sum of reading data is reordered is stated to specifically include:

According to the second storage index vector, the corresponding element of index of each storing sub-units is obtained described to be read The reading data directory vector that index in data vector is constituted；

According to the reading data directory vector, the second storage address vector described in vector sum is enabled to the reading data and is carried out It reorders.

9. a kind of data parallel writing station characterized by comprising

First conversion module, the write-in data directory for being written into data vector are transformed to one-dimensional writing address；Wherein, institute Stating data vector to be written is an one or more dimensions vector in multidimensional data matrix to be written, said write data directory It is first element to be written in all elements of the data vector to be written in the multidimensional data matrix to be written Index；

First obtains module, for obtaining the number to be written according to the one-dimensional writing address and default write-in data amount check Vector, the first storage index vector and the first storage address vector are enabled according to the write-in data of vector；Wherein, said write data Each element in enabled vector is for indicating whether the element of corresponding position in the data vector to be written is written；Described One storage index vector is the rope of each storing sub-units in the corresponding parallel storage of each element in the data vector to be written Draw constituted vector；The first storage address vector is corresponding each storage of each element in the data vector to be written The vector that address in unit is constituted；

It is stored in module, for enabling vector, first storage to said write data according to the first storage index vector Address vector and the data vector to be written reorder, and enable vector sum institute according to the said write data after reordering The data vector to be written after stating the first storage address vector and reordering is stored in the parallel storage.

10. a kind of data parallel reading device characterized by comprising

Second conversion module, for the reading data directory of data vector to be read to be transformed to one-dimensional reading address；Wherein, institute Stating data vector to be read is an one or more dimensions vector in multidimensional data matrix to be read, the reading data directory It is first element to be read in all elements of the data vector to be read in the multidimensional data matrix to be read Index；

Second obtains module, for reading data amount check with default according to the one-dimensional reading address, access of continuing described in acquisition Vector, the second storage index vector and the second storage address vector are enabled according to the reading data of vector；Wherein, the reading data Each element in enabled vector is for indicating whether the element of corresponding position in the data vector to be read reads；Described Two storage index vectors are the rope of each storing sub-units in the corresponding parallel storage of each element in the data vector to be read Draw constituted vector；The second storage address vector is corresponding each storage of each element in the data vector to be read The vector that address in unit is constituted；

Read module, for being deposited to described in the enabled vector sum of the reading data second according to the second storage index vector Storage address vector reorders, and enables the second storage address vector described in vector sum according to the reading data after reordering From the parallel storage read storing data vector, according to it is described second storage index vector to the storing data vector into Rearrangement sequence obtains the data vector to be read.

11. a kind of data parallel read-write system, which is characterized in that including parallel storage, and as described in claim 9 and 10 Device.