CN108983119A - A kind of single-chip integration two-dimensional magnetic vector sensor and its integrated manufacture craft - Google Patents

Abstract

The invention discloses a kind of single-chip integration two-dimensional magnetic vector sensor and its manufacture crafts, the sensor includes for detecting the eight of two-dimensional magnetic field silicon magnetic sensitive transistors, it is wherein two-by-two to be arranged in parallel between silicon magnetic sensitive transistor, and it is respectively formed the first magnetic susceptibility unit (MSE1), second magnetic susceptibility unit (MSE2), third magnetic susceptibility unit (MSE3) and the 4th magnetic susceptibility unit (MSE4), wherein, the first magnetic susceptibility unit (MSE1) and the second magnetic susceptibility unit (MSE2) are arranged along x-axis by phase diamagnetic sensitive direction, form the first differential testing circuit, for the direction x magnetic field (B_x) detection；The third magnetic susceptibility unit (MSE3) and the 4th magnetic susceptibility unit (MSE4) are arranged along y-axis by phase diamagnetic sensitive direction, form the second differential testing circuit, are used for the direction y magnetic field (B_y) detection.Single-chip integration two-dimensional magnetic vector sensor structure of the present invention is simple, realizes the detection of two-dimensional magnetic field, and chip realizes miniaturization and single-chip integrated.

Description

A monolithic integrated two-dimensional magnetic vector sensor and its integrated manufacturing process

technical field

The present invention relates to the technical field of sensors, in particular to a two-dimensional magnetic vector sensor, in particular to a monolithically integrated two-dimensional magnetic vector sensor and its integrated manufacturing process.

Background technique

With the rapid development of science and technology, sensor technology has attracted much attention, especially the magnetic field sensors widely used in modern industry and electronic products. With the wide application, the requirements for the integration of magnetic field sensors have also increased.

Sensors used to detect two-dimensional magnetic fields include magnetotransistors, fluxgates, giant magnetoresistance (GMR), tunneling magnetoresistors (TMR), anisotropic magnetoresistors (AMR), and Hall elements.

In the prior art, there have been reports on the use of magnetotransistors for two-dimensional magnetic field detection. However, in the reports, when using magnetotransistors for two-dimensional magnetic field detection, a wider susceptibility interval is required, that is, the magnetic field needs Covers the entire chip for measurement, and does not perform well for narrower magnetic field detection.

Contents of the invention

In order to solve the above problems, the present inventor has carried out intensive research, and adopted MEMS technology to design and manufacture eight integrated SOI (silicon-on-insulator) silicon magnetotransistors on a high-resistance single-crystal silicon substrate, wherein two by two are arranged in parallel, In addition, eight silicon magnetosensitive triodes are arranged to realize monolithic integration of two pairs of differential test circuits, which are respectively used to detect two-dimensional magnetic fields (B _x , B _y ) in a plane, thereby completing the present invention.

On the one hand, the present invention provides a monolithic integrated two-dimensional magnetic vector sensor, which is embodied in the following aspects:

(1) A monolithically integrated two-dimensional magnetic vector sensor, wherein the sensor includes a first silicon chip 1 as a device layer and a second silicon chip 2 as a substrate, wherein the first silicon chip 1 is provided with There are eight silicon magnetotransistors for detecting the two-dimensional magnetic field, and two silicon magnetotransistors are arranged in parallel.

(2) According to the monolithic integrated two-dimensional magnetic vector sensor described in the above (1), wherein, the eight silicon magnetotransistors are respectively a magnetotransistor one SMST1, a silicon magnetotransistor two SMST2, and a silicon magnetotransistor three SMST3 , silicon magnetic sensitive transistor four SMST4, silicon magnetic sensitive transistor five SMST5, silicon magnetic sensitive transistor six SMST6, silicon magnetic sensitive transistor seven SMST7 and silicon magnetic sensitive transistor eight SMST8, wherein,

The first SMST1 of the silicon magnetosensitive transistor and the second SMST2 of the silicon magnetosensitive transistor are arranged in parallel;

The silicon magnetic sensitive triode five SMST5 and the silicon magnetic sensitive triode six SMST6 are arranged in parallel;

The silicon magnetic sensitive triode SMST3 and the silicon magnetic sensitive triode SMST4 are arranged in parallel;

The silicon magnetic sensitive transistor seven SMST7 and the silicon magnetic sensitive transistor eight SMST8 are arranged in parallel.

(3) The monolithic integrated two-dimensional magnetic vector sensor according to the above (1) or (3), wherein,

The silicon magnetosensitive transistor one SMST1 and the silicon magnetosensitive transistor two SMST2 are connected in parallel with the collector load resistor one R _L1 to form the first magnetic sensitive unit MSE1;

The silicon magnetosensitive transistor five SMST5 and the silicon magnetosensitive transistor six SMST6 are connected in parallel with the collector load resistor two R _L2 to form a second magnetic sensitive unit MSE2;

The silicon magnetic sensitive triode SMST3 and the silicon magnetic sensitive triode SMST4 are connected in parallel with the collector load resistor 3 R _L3 to form the third magnetic sensitive unit MSE3;

The silicon magnetic sensitive transistor seven SMST7 and the silicon magnetic sensitive transistor eight SMST8 are connected in parallel to the collector load resistor four RL4 to form the fourth magnetic sensitive unit MSE4.

(4) The monolithic integrated two-dimensional magnetic vector sensor according to any one of the above (1) to (3), wherein,

The first magnetically sensitive unit MSE1 and the second magnetically sensitive unit MSE2 are arranged along the x-axis in opposite magnetically sensitive directions to form a first differential test circuit for detecting the magnetic field (B _x ) in the x direction; and/or

The third magnetically sensitive unit MSE3 and the fourth magnetically sensitive unit MSE4 are arranged along the y-axis in opposite magnetically sensitive directions, forming a second differential test circuit for detecting the magnetic field (B _y ) in the y-direction.

(5) The monolithic integrated two-dimensional magnetic vector sensor according to any one of the above (1) to (4), wherein, in the first magnetically sensitive unit MSE1 and the second magnetically sensitive unit MSE2,

The base area of silicon magnetic sensitive transistor one SMST1, the base area of silicon magnetic sensitive transistor two SMST2, the collector area of silicon magnetic sensitive transistor five SMST5 and the collector area of silicon magnetic sensitive transistor six SMST6 are collinear along the x-axis direction;

Preferably, the collector region of silicon magnetic sensitive transistor one SMST1, the collector region of silicon magnetic sensitive transistor two SMST2, the base region of silicon magnetic sensitive transistor five SMST5 and the base region of silicon magnetic sensitive transistor six SMST6 are collinear along the x-axis direction .

(6) The monolithic integrated two-dimensional magnetic vector sensor according to any one of the above (1) to (5), wherein, in the third magnetic sensitive unit MSE3 and the fourth magnetic sensitive unit MSE4,

The base area of the silicon magnetic sensitive transistor three SMST3, the base area of the silicon magnetic sensitive transistor four SMST4, the collector area of the silicon magnetic sensitive transistor seven SMST7 and the collector area of the silicon magnetic sensitive transistor eight SMST8 are collinear along the y-axis direction;

Preferably, the collector area of the silicon magnetic sensitive transistor three SMST3, the collector area of the silicon magnetic sensitive transistor four SMST4, the base area of the silicon magnetic sensitive transistor seven SMST7 and the base area of the silicon magnetic sensitive transistor eight SMST8 are collinear along the y-axis direction .

(7) The monolithic integrated two-dimensional magnetic vector sensor according to one of the above (1) to (6), wherein, on the first silicon chip 1, an isolation ring 11 is made around each silicon magnetosensitive triode, preferably Ground, the isolation ring 11 is n ⁺ type doped.

The second aspect of the present invention provides a manufacturing process of the sensor described in the first aspect of the present invention, specifically embodied in the following aspects:

(8) A manufacturing process of a monolithic integrated two-dimensional magnetic vector sensor described in one of the above (1) to (7), wherein the process includes the following steps:

Step 1, cleaning the first silicon wafer 1, performing an oxidation, and growing a silicon dioxide layer on its lower surface;

Step 2, performing photolithography on the lower surface of the first silicon wafer 1 to obtain eight emission region windows, and performing n ⁺ type heavy doping to form emission regions of eight silicon magnetotransistors respectively;

Step 3. Clean the second silicon wafer, grow silicon dioxide layers on both sides, and use a bonding process to bond the first silicon wafer to the second silicon wafer, preferably the lower surface of the first silicon wafer and the second silicon wafer. bonding between the top surfaces of the chips;

Step 4, after bonding, thinning, polishing and cleaning the first silicon wafer;

Step 5, cleaning, using a thermal oxidation process to grow a silicon dioxide layer on the upper surface of the device layer as an ion implantation buffer layer;

Step 6: Carry out two photolithography, three photolithography, four photolithography and five photolithography successively on the upper surface of the device layer, respectively perform n ⁺ type doping, n ^- type doping, and n ⁺ type heavy doping and p ⁺ type heavy doping, respectively forming an isolation ring, four collector load resistors, eight collector regions and eight base regions in sequence;

Step 7, high temperature annealing treatment;

Step 8, cleaning, growing a silicon dioxide layer on the chip, preferably with a thickness of As metal interconnect insulation layer;

Step 9, the sixth photolithography, etching the lead hole of the metal electrode, then vacuum-depositing the metal Al layer, and etching on the surface of the metal Al layer to form a metal Al interconnection line;

Step 10, cleaning, growing a silicon dioxide layer on the chip, preferably with a thickness of As a passivation layer, the seventh photolithography, etch the passivation layer window;

Step 11, cleaning, the eighth photolithography, etching eight emission area lead pit windows on the lower surface of the second silicon layer, etching by deep groove etching technology (ICP), forming eight emission area etching pits;

Step 12, cleaning, making metal Al in eight corrosion pits by vacuum evaporation to form metal Al leads;

Step 13, performing an alloying treatment to form an ohmic contact to obtain the monolithic integrated two-dimensional magnetic vector sensor.

(9) The manufacturing process according to the above (8), wherein, in step 1, the first silicon wafer 1 is a high-resistance p-type single crystal silicon wafer with a <100> crystal orientation, preferably, the first The resistivity of the silicon wafer is greater than 1000Ω·cm.

The third aspect of the present invention provides a monolithic integrated two-dimensional magnetic vector sensor manufactured by using the process described in the second aspect of the present invention.

Description of drawings

Fig. 1 shows the schematic top view of the monolithic integrated two-dimensional magnetic vector sensor of the present invention;

Fig. 2 shows the equivalent circuit diagram of the monolithic integrated two-dimensional magnetic field sensor of the present invention;

Fig. 3 shows a schematic cross-sectional view of a preferred embodiment at a-a in Fig. 1;

Fig. 4 shows a schematic cross-sectional view of a preferred embodiment at b-b in Fig. 1;

Fig. 5a～Fig. 5g show the technological process diagram one (along a-a section) of manufacturing process of the present invention;

Fig. 6a～Fig. 6g show the technological process Fig. 2 (along the b-b cross-section) of the manufacturing process of the present invention;

Fig. 7 shows a schematic top view of a comparative sensor different from the sensor of the present invention.

Explanation of reference signs

1-first silicon wafer; 11-isolating ring; 2-second silicon wafer; 3-silicon dioxide layer; SMST1-silicon magneto-sensitive transistor one; SMST2-silicon magneto-sensitive transistor two; SMST3-silicon magneto-sensitive transistor three; SMST4-Silicon Magnetic Transistor Four; SMST5-Silicon Magnetic Transistor Five; SMST6-Silicon Magnetic Transistor Six; SMST7-Silicon Magnetic Transistor Seven; SMST8-Silicon Magnetic Transistor Eight; R _B1 - Base Load Resistor One; R _B2 - base load resistor two; R _B3 - base load resistor three; R _B4 - base load resistor four; R _B5 - base load resistor five; R _B6 - base load resistor six; R _B7 - base load resistor Resistor seven; R _B8 - base load resistor eight; R _L1 - collector load resistor one; R _L2 - collector load resistor two; R _L3 - collector load resistor three; R _L4 - collector load resistor four; B ₃ - the base of the silicon magnetotransistor three; B ₄ - the base of the silicon magnetotransistor four; B ₅ - the base of the silicon magnetotransistor five; B ₆ - the base of the silicon magnetotransistor six _; The collector of magnetotransistor 1; C ₂ - the collector of silicon magnetotransistor 2; C ₇ - the collector of silicon magnetotransistor 7; C ₈ - the collector of silicon magnetotransistor 8; E ₁ - the silicon magnetotransistor Transistor 1 emitter; E ₂ -silicon magnetotransistor 2 emitter; E ₇ -silicon magnetotransistor 7 emitter; E ₈ -silicon magnetotransistor 8 emitter; V _DD -power supply; GND-ground ; V _x1 - output voltage one; V _x2 - output voltage two; V _y3 - output voltage three; V _y4 - output voltage four.

Detailed ways

The following describes the present invention in detail, and the features and advantages of the present invention will become more clear and definite along with these descriptions.

One aspect of the present invention provides a monolithic integrated two-dimensional magnetic vector sensor, as shown in Figure 1 and Figures 3-4, the sensor includes a first silicon chip 1 as a device layer and a second silicon chip as a substrate 2. Among them, eight silicon magnetotransistors for detecting two-dimensional magnetic fields are arranged on the first silicon chip 1, which are respectively silicon magnetosensitive transistor one SMST1, silicon magnetosensitive transistor two SMST2, silicon magnetosensitive transistor three SMST3, silicon magnetotransistor three Magnetic transistor four SMST4, silicon magnetic sensitive transistor five SMST5, silicon magnetic sensitive transistor six SMST6, silicon magnetic sensitive transistor seven SMST7 and silicon magnetic sensitive transistor eight SMST8, used for detection of xy plane two-dimensional magnetic field.

Wherein, the silicon magneto-sensitive transistor is an NPN type magneto-sensitive transistor.

According to a preferred embodiment of the present invention, the thickness of the first silicon wafer 1 is 20-30 μm, and the thickness of the second silicon wafer 2 is 350-450 μm.

In a further preferred embodiment, the thickness of the first silicon wafer 1 is 30 μm, and the thickness of the second silicon wafer 2 is 400˜425 μm.

Wherein, the present invention uses two silicon wafers for bonding, and the second silicon wafer located below is used for supporting, so that the first silicon wafer serving as the device layer can be thinned.

In a further preferred embodiment, the first silicon wafer 1 and the second silicon wafer 2 are both <100> oriented high-resistance p-type single crystal silicon wafers, preferably, the resistivity of the first silicon wafer is greater than 1000Ω cm.

According to a preferred embodiment of the present invention, as shown in FIGS. SMST6 parallel setup.

Among them, two silicon magnetosensitive transistors are used for parallel setting, which can improve the magnetic sensitivity, and at the same time, can optimize the resistance value of the collector load resistance, thus significantly reducing power consumption.

In the prior art, the sensitivity is mostly adjusted by adjusting the resistance of the collector load resistance, but now the resistance of the collector load resistance can be reduced to reduce power consumption, but at the same time it has high sensitivity and realizes low power consumption. Consumes an increase in sensitivity.

In a further preferred embodiment, as shown in Figures 1-2, the silicon magnetotransistor 1 SMST1 and the silicon magnetotransistor 2 _SMST2 are connected in parallel to the collector load resistor RL1 to form the first magnetic sensitive unit MSE1; the silicon magnetosensitive transistor five SMST5 and the silicon magnetosensitive transistor six SMST6 are connected in parallel to the collector load resistor two R _L2 to form a second magnetic sensitive unit MSE2.

In a further preferred embodiment, the first magnetically sensitive unit MSE1 and the second magnetically sensitive unit MSE2 are arranged along the x-axis in opposite magnetically sensitive directions to form a first differential test circuit for the x-direction magnetic field (B _x ) detection.

According to a preferred embodiment of the present invention, as shown in FIG. 1, in the first magnetic sensitive unit MSE1 and the second magnetic sensitive unit MSE2, the base area of the silicon magnetic sensitive triode SMST1, the silicon magnetic sensitive triode SMST2 The base region of the silicon magnetosensitive transistor five SMST5 and the collector region of the silicon magnetosensitive transistor six SMST6 are collinear along the x-axis direction.

In a further preferred embodiment, as shown in Figure 1, in the first magnetic sensitive unit MSE1 and the second magnetic sensitive unit MSE2, the collector area of the silicon magnetic sensitive transistor SMST1, the silicon magnetic sensitive transistor two SMST2 The collector region, the base region of the silicon magnetosensitive transistor five SMST5 and the base region of the silicon magnetosensitive transistor six SMST6 are collinear along the x-axis direction.

More preferably, as shown in Figure 1, silicon magnetosensitive transistor one SMST1, silicon magnetosensitive transistor two SMST2, silicon magnetosensitive transistor five SMST5 and silicon magnetosensitive transistor six SMST6 place line and y between base area and collector area axis parallel.

Like this, as shown in Figure 1, make silicon magnetosensitive transistor one SMST1, silicon magnetosensitive transistor two SMST2, silicon magnetosensitive transistor five SMST5 and silicon magnetosensitive transistor six SMST6 respective base areas and long base areas between the collector regions Parallel and aligned. In this way, by re-arranging the silicon magneto-sensitive transistors, the detection range of the magnetic field in the x-axis direction is greatly reduced, which is the distance between the base region and the collector region of the silicon magneto-sensitive transistors. Therefore, detection can be realized when the range of the magnetic field in the x-axis direction is only the size of the long base region between the base region and the collector region, and the magnetic field does not need to cover the entire x-axis.

According to a preferred embodiment of the present invention, as shown in Figures 1-2, the silicon magnetotransistor three SMST3 and the silicon magnetotransistor four SMST4 are arranged in parallel, the silicon magnetotransistor seven SMST7 and the silicon magnetotransistor eight SMST8 parallel setup.

Among them, two silicon magnetosensitive triodes are used for parallel arrangement, which can increase the magnetic sensitivity, and at the same time, reduce the resistance value of the collector load resistor, thus significantly reducing the power consumption.

In a further preferred embodiment, as shown in Figures 1-2, the silicon magnetotransistor 3 SMST3 and the silicon magnetotransistor 4 SMST4 are connected in parallel to the collector load resistor 3 R _L3 to form a third magnetic sensitive unit MSE3; the silicon magnetosensitive transistor seven SMST7 and the silicon magnetosensitive transistor eight SMST8 are connected in parallel to the collector load resistor four R _L4 to form a fourth magnetic sensitive unit MSE4.

In a further preferred embodiment, the third magnetically sensitive unit MSE3 and the fourth magnetically sensitive unit MSE4 are arranged along the y-axis in opposite magnetically sensitive directions to form a second differential test circuit for the y-direction magnetic field (B _y ) detection.

In the present invention, as shown in Figures 1 to 2, when the external magnetic field has magnetic field components along the x-axis and y-axis in the xy plane, due to the effect of the external magnetic field, the four output voltages (V _x1 , V _x2 , V _y3 , V _y4 ) changes, so as to realize the detection of the two-dimensional magnetic field (B _x , By _y ).

According to a preferred embodiment of the present invention, as shown in FIG. 1, in the third magnetic sensitive unit MSE3 and the fourth magnetic sensitive unit MSE4, the base area of the silicon magnetic sensitive transistor three SMST3, the silicon magnetic sensitive transistor four SMST4 The base region, the collector region of the silicon magnetosensitive transistor seven SMST7 and the collector region of the silicon magnetosensitive transistor eight SMST8 are collinear along the y-axis direction.

In a further preferred embodiment, as shown in Figure 1, in the third magnetic sensitive unit MSE3 and the fourth magnetic sensitive unit MSE4, the collector area of the silicon magnetic sensitive triode SMST3, the silicon magnetic sensitive triode SMST4 The collector region, the base region of the silicon magnetosensitive transistor seven SMST7 and the base region of the silicon magnetosensitive transistor eight SMST8 are collinear along the y-axis direction.

More preferably, as shown in Figure 1, silicon magnetosensitive transistor three SMST3, silicon magnetosensitive transistor four SMST4, silicon magnetosensitive transistor seven SMST7 and silicon magnetosensitive transistor eight SMST8 each base area and the line between the collector area and x axis parallel.

Like this, as shown in Figure 1, make silicon magnetosensitive transistor three SMST3, silicon magnetosensitive transistor four SMST4, silicon magnetosensitive transistor seven SMST7 and silicon magnetosensitive transistor eight SMST8 each base region and the long base region between the collector region mutually Parallel and aligned. In this way, by re-arranging the silicon magneto-sensitive transistors, the detection range of the magnetic field in the y-axis direction is greatly reduced, which is the distance between the base region and the collector region of the silicon magneto-sensitive transistors. Therefore, detection can be realized when the range of the magnetic field in the y-axis direction is only as large as the long base region between the base region and the collector region, and the magnetic field does not need to cover the entire y-axis.

To sum up, by rearranging the eight silicon magnetosensitive transistors, the detection range of the magnetic field of the sensor is greatly reduced. Whether it is the magnetic field of the x-axis or the y-axis, only a gap between the base area and the collector area is required. The long base area size can realize the detection. However, in the prior art, when two-dimensional magnetic field detection is performed, the magnetic field needs to cover the chip to realize simultaneous detection of the magnetic field in the x-axis and y-axis directions, and then the two-dimensional magnetic sensor described in the prior art requires the detected magnetic field to have relatively high large range.

According to a preferred embodiment of the present invention, as shown in Figures 1-2, the collector load resistor _RL1 , the collector load resistor _RL2 , the collector load resistor _RL3 and the collector load resistor RL The other ends of _L4 are both connected to the power supply V _DD .

In a further preferred embodiment, the collector load resistor _RL1 , the collector load resistor _RL2 , the collector load resistor _RL3 and the collector load resistor _RL4 are n ^- type doped.

According to a preferred embodiment of the present invention, as shown in Figures 1-2, the sensor further includes a base load resistor _RB1 , a base load resistor _RB2 , a base load resistor _RB3 , a base load Resistor 4 R _B4 , base load resistor 5 R _B5 , base load resistor 6 _RB6 , base load resistor 7 R _B7 and base load resistor 8 R _B8 , respectively connected with silicon magnetosensitive transistor SMST1 and silicon magnetosensitive transistor Two SMST2, three SMST3 of silicon magnetic sensitive transistor, four SMST4 of silicon magnetic sensitive transistor, five SMST5 of silicon magnetic sensitive transistor, six SMST6 of silicon magnetic sensitive transistor, seven SMST7 of silicon magnetic sensitive transistor and eight SMST8 of silicon magnetic sensitive transistor are connected to each other.

In a further preferred embodiment, base load resistor one R _B1 , base load resistor two R _B2 , base load resistor three R _B3 , base load resistor four R _B4 , base load resistor five R _B5 , base The other ends of the load resistor six R _B6 , the base load resistor seven R _B7 and the base load resistor eight R _B8 are all connected to the power supply V _DD .

In a further preferred embodiment, base load resistor one R _B1 , base load resistor two R _B2 , base load resistor three R _B3 , base load resistor four R _B4 , base load resistor five R B5 , base load resistor five R _B5 , base load resistor two R B2 The pole load resistor six R _B6 , the base load resistor seven R _B7 and the base load resistor eight R _B8 are all n ^- type doped.

Among them, the base is connected with the load resistor, so that the base can provide a constant current without providing a current source for each base.

According to a preferred embodiment of the present invention, as shown in Figures 1 to 4, the silicon magnetotransistor-SMST1 emitter E ₁ , the silicon magnetotransistor-two SMST2 emitter _E2 , and the silicon magnetotransistor-three SMST3 emitter E ₃ , silicon magnetic sensitive transistor four SMST4 emitter E ₄ , silicon magnetic sensitive transistor five SMST5 emitter E ₅ , silicon magnetic sensitive transistor six SMST6 emitter E ₆ , silicon magnetic sensitive transistor seven SMST7 emitter E ₇ and silicon magnetic sensitive Transistor eight SMST8 emitter E ₈ is connected and grounded.

According to a preferred embodiment of the present invention, an isolation ring 11 is fabricated on the first silicon chip 1 and around each silicon magnetotransistor.

In a further preferred embodiment, the isolation ring 11 penetrates through the first silicon wafer 1 .

In a further preferred embodiment, the isolation ring 11 is doped with n ⁺ type.

Wherein, on the p-type silicon chip, etch the n ⁺ type doped spacer ring 11, so that the inside and outside of the spacer ring 11 are all P-type, and the spacer ring forms a PN junction with the inner and outer contact surfaces of the first silicon chip, and because The PN junction has unidirectional conductivity, so there will always be a contact surface (inner contact surface or outer contact surface) that is not conducting. In this way, each silicon magnetosensitive triode is successfully isolated from other devices, preventing the contact between devices. conduction, avoiding mutual interference, and improving the consistency of magnetic sensitivity and the stability of the sensor.

The second aspect of the present invention provides a manufacturing process of the monolithic integrated two-dimensional magnetic vector sensor described in the first aspect of the present invention. As shown in FIG. 5, the process includes the following steps:

Step 1, cleaning the first silicon wafer 1, performing an oxidation, and growing a silicon dioxide layer on its lower surface [as shown in Figure 5a and Figure 6a];

Step 2. Perform a photolithography on the lower surface of the first silicon wafer 1 to obtain eight emission region windows, and carry out n ⁺ type heavy doping to form emission regions of eight silicon magnetotransistors [as shown in the figure 5b and Figure 6b];

Step 3, cleaning the second silicon wafer, growing silicon dioxide layers on both sides [as shown in Figure 5c and Figure 6c], and using a bonding process to bond the first silicon wafer to the second silicon wafer, preferably the second silicon wafer Bonding is performed between the lower surface of a silicon wafer and the upper surface of a second silicon wafer;

Step 4, after bonding, thinning, polishing and cleaning the first silicon wafer;

Step 5, cleaning, using a thermal oxidation process to grow a silicon dioxide layer on the upper surface of the device layer as an ion implantation buffer layer;

Step 6: Carry out two photolithography, three photolithography, four photolithography and five photolithography successively on the upper surface of the device layer, respectively perform n ⁺ type doping, n ^- type doping, and n ⁺ type heavy doping and p ⁺ type heavy doping, respectively forming isolation rings, four collector load resistors ( _RL1 , R _L2 , R _L3 , R _L4 ), eight collector regions and eight base regions in turn [as shown in Figure 5d~ 5e and Figure 6d ~ Figure 6e];

Step 7, high temperature annealing treatment;

Step 8, cleaning, growing a silicon dioxide layer on the chip, preferably with a thickness of As metal interconnect insulation layer;

Step 9, the sixth photolithography, etching the lead hole of the metal electrode, then vacuum-depositing the metal Al layer, and etching on the surface of the metal Al layer to form a metal Al interconnection line;

Step 10, cleaning, growing a silicon dioxide layer on the chip, preferably with a thickness of As a passivation layer, the seventh photolithography is used to etch the passivation layer window;

Step 11, cleaning, the eighth photolithography, etch eight emission area lead pit windows on the lower surface of the second silicon layer, and etch through deep groove etching technology (ICP) to form eight emission area etching pits [such as Figure 5f and Figure 6f];

Step 12, cleaning, making metal Al in eight corrosion pits by vacuum evaporation to form metal Al leads [as shown in Figure 5g and Figure 6g];

Step 13, performing an alloying treatment to form an ohmic contact to obtain the monolithic integrated two-dimensional magnetic vector sensor.

According to a preferred embodiment of the present invention, in step 1, the first silicon wafer 1 is a p-type single crystal silicon wafer with a <100> orientation and high resistance.

In a further preferred embodiment, the resistivity of the first silicon wafer is greater than 1000Ω·cm.

According to a preferred embodiment of the present invention, in step 1, a silicon dioxide layer with a thickness of 30-50 nm is grown by a thermal oxidation method as an ion implantation buffer layer.

In a further preferred embodiment, in step 1, a silicon dioxide layer with a thickness of 40 nm is grown by a thermal oxidation method.

According to a preferred embodiment of the present invention, in step 3, the thickness of the silicon dioxide layer grown on both sides is

In a further preferred embodiment, in step 3, the thickness of the silicon dioxide layer grown on both sides is

According to a preferred embodiment of the present invention, the thickness of the first silicon wafer 1 after thinning in step 4 is 20-40 μm.

In a further preferred embodiment, the thickness of the first silicon wafer 1 after step 4 is thinned is 30 μm.

Wherein, in the present invention, two silicon wafers are used for bonding, so that the first silicon wafer as a device layer can be very thin with the second silicon wafer as a substrate as a support.

According to a preferred embodiment of the present invention, in step 5, the thickness of the grown silicon dioxide layer is 30-50 nm.

In a further preferred embodiment, in step 5, the thickness of the grown silicon dioxide layer is 40 nm.

According to a preferred embodiment of the present invention, in step 7, the high-temperature annealing treatment is performed as follows: vacuum environment treatment at 800-900° C. for 30-40 minutes.

According to a preferred embodiment of the present invention, in step 13, the alloying treatment is performed as follows: vacuum environment treatment at 400-450° C. for 20-40 minutes.

In a further preferred embodiment, in step 13, the alloying treatment is carried out as follows: treatment in a vacuum environment at 420° C. for 30 minutes.

The third aspect of the present invention provides a monolithic integrated two-dimensional magnetic vector sensor obtained according to the manufacturing process described in the second aspect of the present invention.

The beneficial effects that the present invention has:

(1) The monolithic integrated two-dimensional magnetic vector sensor of the present invention connects eight silicon magnetosensitive triodes (SMST1, SMST2, SMST3, SMST4, SMST5, SMST6, SMST7, SMST8) in parallel with four collector load resistors (R _L1 , R _L2 , R _L3 , R _L4 ) are effectively combined and monolithically integrated to form two pairs of differential test circuits respectively, realizing two-dimensional magnetic field (B _x , By _y ) detection;

(2) At the same time, the parallel structure of two or two triodes not only improves the magnetic sensitivity in all directions, but also reduces the size of the collector load resistance, which significantly reduces power consumption. In this way, high magnetic sensitivity is achieved at low power consumption ;

(3) By rearranging and setting the silicon magnetosensitive transistors, the range of the detection magnetic field is greatly reduced, which is the distance between the base area and the collector area of the silicon magnetosensitive transistors;

(4) The single-chip integrated two-dimensional magnetic vector sensor of the present invention has a simple structure and realizes the miniaturization and integration of the chip;

(5) The manufacturing process of the present invention is simple, easy to realize, and suitable for large-scale industrial application.

Experimental example 1

Adopt the magnetic field generating system of Beijing Cuihai Jiacheng Magnetoelectric Technology Co., Ltd. to test the monolithic integrated two-dimensional magnetic vector sensor (shown in Fig. 1) and the two-dimensional magnetic field sensor shown in Fig. 7 of the present invention respectively, analyze the monolithic The magnetic field detection sensitivity of the integrated two-dimensional magnetic field sensor can be known after testing:

(1) When the power supply voltage is 5.0V:

The sensitivity of the magnetic sensor in the x-axis direction of the sensor of the present invention is 293mV/T, and the sensitivity of the magnetic sensor in the y-direction is 292mV/T;

The sensitivity of the magnetic sensor in the x-axis direction of the sensor shown in Figure 7 is 285mV/T, and the sensitivity of the magnetic sensor in the y-direction is 284mV/T;

It can be seen that the sensors of the present invention are arranged in parallel by two triodes, which improves the magnetic sensitivity.

Experimental example 2

Apply a magnetic field area of about 150 μm to the sensor of the present invention and the sensor shown in Figure 7 respectively, and find that:

(1) The sensor of the present invention can successfully detect an applied magnetic field of about 150 μm;

(2) The magnetically sensitive area of the sensor shown in Figure 7 is more than 800 μm along the magnetically sensitive direction.

The present invention has been described in detail above in conjunction with specific implementations and exemplary examples, but these descriptions should not be construed as limiting the present invention. Those skilled in the art understand that without departing from the spirit and scope of the present invention, various equivalent replacements, modifications or improvements can be made to the technical solutions and implementations of the present invention, all of which fall within the scope of the present invention. The protection scope of the present invention shall be determined by the appended claims.

Claims (10)

1. A monolithic integrated two-dimensional magnetic vector sensor is characterized in that the sensor comprises a first silicon chip (1) as a device layer and a second silicon chip (2) as a substrate, wherein, in the first The silicon chip (1) is provided with eight silicon magneto-sensitive triodes for detecting two-dimensional magnetic fields, and two silicon magneto-sensitive transistors are arranged in parallel. 2. monolithic integrated two-dimensional magnetic vector sensor according to claim 1, is characterized in that, described eight silicon magnetosensitive triodes are respectively silicon magnetosensitive transistor one (SMST1), silicon magnetosensitive transistor two (SMST2), Silicon magnetotransistor three (SMST3), silicon magnetotransistor four (SMST4), silicon magnetotransistor five (SMST5), silicon magnetotransistor six (SMST6), silicon magnetotransistor seven (SMST7) and silicon magnetotransistor eight ( SMST8), where Described silicon magnetosensitive triode one (SMST1) and silicon magnetosensitive transistor two (SMST2) are arranged in parallel; The silicon magnetic sensitive transistor five (SMST5) and the silicon magnetic sensitive transistor six (SMST6) are arranged in parallel; Described silicon magnetosensitive transistor three (SMST3) and silicon magnetosensitive transistor four (SMST4) are arranged in parallel; The silicon magneto-sensitive transistor seven (SMST7) and the silicon magneto-sensitive transistor eight (SMST8) are arranged in parallel. 3. The monolithic integrated two-dimensional magnetic vector sensor according to claim 1 or 2, characterized in that, The silicon magnetosensitive transistor one (SMST1) and the silicon magnetosensitive transistor two ( _SMST2 ) are connected in parallel with the collector load resistor one (RL1) to form a first magnetically sensitive unit (MSE1); The silicon magnetic sensitive transistor five (SMST5) and the silicon magnetic sensitive transistor six ( _SMST6 ) are connected in parallel with the collector load resistor two (RL2) to form a second magnetic sensitive unit (MSE2); The silicon magnetosensitive transistor three (SMST3) and the silicon magnetosensitive transistor four ( _SMST4 ) are connected in parallel with the collector load resistor three (RL3) to form the third magnetic sensitive unit (MSE3); The silicon magnetosensitive transistor seven (SMST7) and the silicon magnetosensitive transistor eight ( _SMST8 ) are connected in parallel to the collector load resistor four (RL4) to form a fourth magnetic sensitive unit (MSE4). 4. The monolithic integrated two-dimensional magnetic vector sensor according to one of claims 1 to 3, characterized in that, The first magnetically sensitive unit (MSE1) and the second magnetically sensitive unit (MSE2) are arranged along the x-axis in opposite magnetically sensitive directions to form a first differential test circuit for detecting the magnetic field (B _x ) in the x direction; and/ or The third magnetic sensitive unit (MSE3) and the fourth magnetic sensitive unit (MSE4) are arranged along the y-axis in opposite magnetic sensitive directions to form a second differential test circuit for detecting the magnetic field in the y direction (B _y ). 5. The monolithic integrated two-dimensional magnetic vector sensor according to one of claims 1 to 4, characterized in that, in the first magnetically sensitive unit (MSE1) and the second magnetically sensitive unit (MSE2), The base area of silicon magneto-sensitive transistor one (SMST1), the base area of silicon magneto-sensitive transistor two (SMST2), the collector area of silicon magneto-sensitive transistor five (SMST5) and the collector area of silicon magneto-sensitive transistor six (SMST6) The x-axis direction is collinear; Preferably, the collector region of silicon magnetosensitive transistor one (SMST1), the collector region of silicon magnetosensitive transistor two (SMST2), the base region of silicon magnetosensitive transistor five (SMST5) and the silicon magnetosensitive transistor six (SMST6) The base regions are collinear along the x-axis direction. 6. The monolithic integrated two-dimensional magnetic vector sensor according to one of claims 1 to 5, characterized in that, in the third magnetic sensitive unit (MSE3) and the fourth magnetic sensitive unit (MSE4), The base area of silicon magneto-sensitive transistor three (SMST3), the base area of silicon magneto-sensitive transistor four (SMST4), the collector area of silicon magneto-sensitive transistor seven (SMST7) and the collector area of silicon magneto-sensitive transistor eight (SMST8) The y-axis direction is collinear; Preferably, the collector region of silicon magnetosensitive transistor three (SMST3), the collector region of silicon magnetosensitive transistor four (SMST4), the base region of silicon magnetosensitive transistor seven (SMST7) and the silicon magnetosensitive transistor eight (SMST8) The base regions are collinear along the y-axis direction. 7. The monolithic integrated two-dimensional magnetic vector sensor according to one of claims 1 to 6, characterized in that, on the first silicon chip (1), an isolation ring (11) is made around each silicon magnetotransistor , preferably, the isolation ring (11) is doped with n ⁺ type. 8. A fabrication process for monolithically integrated two-dimensional magnetic vector sensor according to one of claims 1 to 7, characterized in that the process comprises the following steps: Step 1, cleaning the first silicon wafer (1), performing an oxidation, and growing a silicon dioxide layer on its lower surface; Step 2, performing photolithography on the lower surface of the first silicon wafer (1) to obtain eight emission region windows, and performing n ⁺ type heavy doping to form emission regions of eight silicon magnetotransistors respectively; Step 3. Clean the second silicon wafer, grow silicon dioxide layers on both sides, and use a bonding process to bond the first silicon wafer to the second silicon wafer, preferably the lower surface of the first silicon wafer and the second silicon wafer. bonding between the top surfaces of the chips; Step 4, after bonding, thinning, polishing and cleaning the first silicon wafer; Step 5, cleaning, using a thermal oxidation process to grow a silicon dioxide layer on the upper surface of the device layer as an ion implantation buffer layer; Step 6: Carry out two photolithography, three photolithography, four photolithography and five photolithography successively on the upper surface of the device layer, respectively perform n ⁺ type doping, n ^- type doping, and n ⁺ type heavy doping and p ⁺ type heavy doping, respectively forming an isolation ring, four collector load resistors, eight collector regions and eight base regions in sequence; Step 7, high temperature annealing treatment; Step 8, cleaning, growing a silicon dioxide layer on the chip, preferably with a thickness of As metal interconnect insulation layer; Step 9, the sixth photolithography, etching the lead hole of the metal electrode, then vacuum-depositing the metal Al layer, and etching the surface of the metal Al layer to form a metal Al interconnection line; Step 10, cleaning, growing a silicon dioxide layer on the chip, preferably with a thickness of As a passivation layer, the seventh photolithography, etch the passivation layer window; Step 11, cleaning, the eighth photolithography, etching eight emission area lead pit windows on the lower surface of the second silicon layer, etching by deep groove etching technology (ICP), forming eight emission area etching pits; Step 12, cleaning, making metal Al in eight corrosion pits by vacuum evaporation to form metal Al leads; Step 13, performing an alloying treatment to form an ohmic contact to obtain the monolithic integrated two-dimensional magnetic vector sensor. 9. The manufacturing process according to claim 8, characterized in that, in step 1, the first silicon wafer (1) is a <100> oriented high-resistance p-type single crystal silicon wafer, preferably, the The resistivity of the first silicon wafer is greater than 1000Ω·cm. 10. The monolithic integrated two-dimensional magnetic vector sensor obtained by the manufacturing process according to claim 8 or 9.