CN108975264B - Micro-electromechanical system chip wafer and system packaging method, and micro-electromechanical system - Google Patents
Micro-electromechanical system chip wafer and system packaging method, and micro-electromechanical system Download PDFInfo
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- CN108975264B CN108975264B CN201710404995.1A CN201710404995A CN108975264B CN 108975264 B CN108975264 B CN 108975264B CN 201710404995 A CN201710404995 A CN 201710404995A CN 108975264 B CN108975264 B CN 108975264B
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- 238000002161 passivation Methods 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 41
- 239000010703 silicon Substances 0.000 claims description 41
- 229910052710 silicon Inorganic materials 0.000 claims description 41
- 238000005530 etching Methods 0.000 claims description 11
- 238000005520 cutting process Methods 0.000 claims description 10
- 238000009713 electroplating Methods 0.000 claims description 7
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- 239000010410 layer Substances 0.000 description 92
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
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Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00309—Processes for packaging MEMS devices suitable for fluid transfer from the MEMS out of the package or vice versa, e.g. transfer of liquid, gas, sound
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2207/00—Microstructural systems or auxiliary parts thereof
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/01—Packaging MEMS
- B81C2203/0118—Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
- B81C2203/0785—Transfer and j oin technology, i.e. forming the electronic processing unit and the micromechanical structure on separate substrates and joining the substrates
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
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Abstract
The invention discloses a micro-electromechanical system chip wafer, a system packaging method and a micro-electromechanical system, wherein the wafer packaging method comprises the following steps: temporarily bonding the front surface of the micro-electromechanical system chip and the micro-electromechanical system bearing plate; embedding the micro-electromechanical system chip in an organic resin; the MEMS bearing plate is disassembled and bonded with the wafer, and MEMS pins on the MEMS chip are exposed; manufacturing a micro-electromechanical system insulating layer; removing the micro-electromechanical system insulating layer at the corresponding position of the micro-electromechanical system pin of the micro-electromechanical system chip to form a blind hole; manufacturing a micro-electromechanical system rewiring layer electrically connected with the micro-electromechanical system pins, manufacturing a passivation layer and manufacturing a micro-electromechanical system under-ball metal layer; and manufacturing a micro-electromechanical system bump electrically connected with the micro-electromechanical system pin to obtain the micro-electromechanical system chip wafer with the fan-out packaged. The MEMS chip is packaged in a fan-out type, so that the size of the MEMS chip can be integrated with an ASIC chip wafer to realize wafer-level packaging.
Description
Technical Field
The invention relates to the technical field of micro-electromechanical systems, in particular to a micro-electromechanical system chip wafer, a system packaging method and a micro-electromechanical system.
Background
Microelectromechanical systems (Micro-Electro-MECHANICAL SYSTEM, MEMS) chips are integrated Micro-chips integrating Micro sensors, micro actuators, micro mechanical structures, micro power sources, signal processing and control circuits, high performance electronic integrated chips, interfaces, communications, and the like, and are widely used in high and new technology industries.
Typically, application SPECIFIC INTEGRATED Circuit (ASIC) chips are designed to drive MEMS chips to form microelectromechanical systems.
However, the existing MEMS chip is manufactured based on a 6-inch or 8-inch wafer process, and most of the typical IC chips are manufactured by an 8-inch or 12-inch wafer process, so that the size of the MEMS chip is not adapted to the size of the ASIC chip, and therefore, the wafer-level package cannot be realized, the existing package forms are conventional WB or other packages, and the package is realized by WB after the MEMS chip and the ASIC chip are stacked.
Disclosure of Invention
Accordingly, it is necessary to provide a MEMS chip wafer and system packaging method, and a MEMS, for solving the technical problem that the prior art cannot realize wafer level packaging of MEMS chips and ASIC chips.
The invention provides a wafer packaging method of a micro-electromechanical system chip, which comprises the following steps:
Temporarily bonding the front surface of the micro-electromechanical system chip and the micro-electromechanical system bearing plate;
Embedding the micro-electromechanical system chip in the organic resin to obtain a wafer embedded with the chip;
Bonding a micro-electromechanical system bearing plate with the wafer in a unbonded manner, and exposing micro-electromechanical system pins on the micro-electromechanical system chip;
Manufacturing a micro-electromechanical system insulating layer on the front surface of the micro-electromechanical system chip;
removing the micro-electromechanical system insulating layer at the corresponding position of the micro-electromechanical system pin of the micro-electromechanical system chip to form a blind hole;
manufacturing a micro-electromechanical system rewiring layer electrically connected with the micro-electromechanical system pin through the blind hole, manufacturing a passivation layer covering the micro-electromechanical system rewiring layer, and manufacturing a micro-electromechanical system under-ball metal layer at a position corresponding to the micro-electromechanical system bump;
and manufacturing a micro-electromechanical system bump electrically connected with the micro-electromechanical system pin on the micro-electromechanical system under-ball metal layer to obtain the micro-electromechanical system chip wafer with the fan-out packaged.
Further, the embedding the mems chip in the organic resin to obtain a wafer embedded with the chip specifically includes:
and embedding the micro-electromechanical system chip into the organic resin, and exposing the functional area of the micro-electromechanical system chip to obtain the wafer embedded with the chip.
Further, the micro-electromechanical system bump is arranged in the projection range of the organic resin.
The invention provides a micro-electromechanical system packaging method, which comprises the following steps:
Fan-out packaging is carried out on the micro-electromechanical system chip by using the micro-electromechanical system chip wafer packaging method to obtain a micro-electromechanical system chip wafer, and fan-in packaging is carried out on the special-purpose integrated circuit chip to obtain the special-purpose integrated circuit chip wafer;
and packaging the MEMS chip wafer and the special integrated circuit chip wafer to obtain the MEMS-level packaging structure comprising the MEMS chip wafer and the special integrated circuit chip wafer.
Further, the micro-electro-mechanical system packaging is performed on the micro-electro-mechanical system chip wafer and the application specific integrated circuit chip wafer to obtain a micro-electro-mechanical system level packaging structure including the micro-electro-mechanical system chip wafer and the application specific integrated circuit chip wafer, which specifically includes:
assembling and interconnecting a micro-electromechanical system chip wafer with fan-out packaging and an application specific integrated circuit chip wafer with fan-in packaging through a wafer-level bonding process;
Releasing the required physical structure of the micro-electromechanical system on the back surface of the micro-electromechanical system chip wafer through an etching process;
performing cap bonding on a micro-electromechanical system chip wafer through a wafer-level bonding process;
Manufacturing a solder ball array ball on the back surface of the special integrated circuit chip wafer;
And scribing the MEMS chip wafer and the application specific integrated circuit chip wafer to obtain the MEMS level packaging structure comprising the MEMS chip wafer and the application specific integrated circuit chip wafer.
Furthermore, the method for performing fan-in packaging on the asic chip to obtain the asic chip wafer specifically includes:
temporarily bonding the front surface of the special integrated circuit chip with the special integrated circuit convex block with the special integrated circuit carrier plate;
Thinning the special integrated circuit chip from the back to a designed thickness;
setting an etched silicon groove area on the back of the special integrated circuit chip, and etching a silicon groove in the etched silicon groove area;
Manufacturing a first special integrated circuit insulating layer in the silicon groove and on the back of the special integrated circuit chip;
a bottom groove is cut at the bottom of the silicon groove in a cutting mode, and the cutting depth is controlled at the interface position of the special integrated circuit pin on the front surface of the special integrated circuit chip and the adhesive which is temporarily bonded;
manufacturing a metal layer in the silicon groove;
Electroplating and thickening the deposited metal layer, and then manufacturing an application specific integrated circuit rewiring circuit layer electrically connected with the pin of the application specific integrated circuit;
Manufacturing a second special integrated circuit insulating layer covering the special integrated circuit rewiring line layer, and manufacturing an under-ball metal layer of the special integrated circuit at a ball implantation position of the ball array;
and separating the special integrated circuit chip from the special integrated circuit carrier plate in a de-bonding mode to obtain the packaged special integrated circuit chip wafer.
Still further, a projection of the etched silicon trench region is between two adjacent integrated circuit bumps.
Still further, the dicing the mems die wafer and the asic die wafer specifically includes:
And scribing the MEMS chip wafer and the special integrated circuit chip wafer at the position of the silicon groove of the special integrated circuit chip wafer.
The invention provides a microelectromechanical system, comprising: the MEMS chip wafer adopting fan-out encapsulation and the special integrated circuit chip wafer adopting fan-in encapsulation are provided with MEMS bumps electrically connected with MEMS pins, and the MEMS bumps are electrically connected with the special integrated circuit bumps on the front surface of the special integrated circuit chip wafer.
Further, the mems die wafer includes: the MEMS chip is embedded in the organic resin, a layer of MEMS insulating layer is arranged on the front surface of the MEMS chip, a blind hole is arranged at a position of the MEMS insulating layer corresponding to the MEMS pin of the MEMS chip, a MEMS rewiring layer electrically connected with the MEMS pin through the blind hole is arranged on the insulating layer, a layer of MEMS passivation layer is arranged on the MEMS rewiring layer, and a MEMS bump electrically connected with the MEMS pin through an under-ball metal layer is arranged on the MEMS passivation layer.
Further, the asic die wafer includes: the special integrated circuit chip is characterized in that the front surface of the special integrated circuit chip is provided with a special integrated circuit bump, the back surface of the special integrated circuit chip is etched with a silicon groove, the bottom of the silicon groove is provided with a bottom groove, a first special integrated circuit insulating layer is arranged in the silicon groove and on the back surface of the special integrated circuit chip, a metal layer thickened through electroplating is deposited in the silicon groove, a special integrated circuit rewiring line layer electrically connected with the special integrated circuit pin is arranged on the first special integrated circuit insulating layer, a second special integrated circuit insulating layer is arranged above the special integrated circuit rewiring line layer, an under-ball metal layer of the special integrated circuit is arranged at the ball planting position of a solder ball array of the second special integrated circuit insulating layer, and a solder ball array ball is arranged on the under-ball metal layer of the special integrated circuit.
The MEMS chip is led out to the outside through the fan-out packaging mode in a manner of welding a bump (bump) and is connected to the outside through a fan-in mode of the ASIC chip, so that the integrated packaging of the MEMS chip and the ASIC chip can be realized through the wafer-level packaging. The wafer-level packaging is adopted, so that paths between chips and paths connected with the outside are effectively shortened, and the performance of the system is improved. The high-speed signal of the ASIC chip can be ensured to be transmitted by directly leading out the high-speed signal to the outside through the RDL from the back of the ASIC chip.
Drawings
FIG. 1 is a flow chart of a method for packaging a chip wafer of a MEMS according to the present invention;
FIG. 2 is a flow chart of a method of packaging a MEMS of the present invention;
FIG. 3 is a flow chart of MEMS packaging of MEMS chip wafers and application specific integrated circuit chip wafers according to the present invention;
FIG. 4 is a flow chart of an ASIC chip wafer packaging method according to the present invention;
FIG. 5 is a schematic diagram of a MEMS structure according to the present invention.
Detailed Description
The invention will now be described in further detail with reference to the drawings and to specific examples.
FIG. 1 is a flow chart of a method for packaging a chip wafer of a MEMS according to the present invention, which comprises:
Step S101, temporarily bonding the front surface of the micro-electromechanical system chip 11 and the micro-electromechanical system carrier plate 12;
step S102, embedding the micro-electromechanical system chip 11 in the organic resin 13 to obtain a wafer embedded with the chip;
Step S103, the MEMS bearing plate 12 is disassembled and bonded with the wafer, and the MEMS pins 14 on the MEMS chip are exposed;
Step S104, a layer of MEMS insulating layer 15 is manufactured on the front surface of the MEMS chip 11;
Step S105, removing the MEMS insulating layer at the position corresponding to the MEMS pin 14 of the MEMS chip to form a blind hole 16;
Step S106, manufacturing a micro-electromechanical system rewiring layer 17 electrically connected with the micro-electromechanical system pins 14 through the blind holes 16, manufacturing a passivation layer 18 covering the micro-electromechanical system rewiring layer 17, and manufacturing a micro-electromechanical system under-ball metal layer at a position corresponding to the micro-electromechanical system bumps;
Step S107, manufacturing a micro-electromechanical system bump 19 electrically connected with the micro-electromechanical system pin on the under-ball metal layer of the micro-electromechanical system to obtain the micro-electromechanical system chip wafer 1 with fan-out packaged.
Specifically:
step S101, temporary patch: the MEMS chip 11 is attached to the carrier plate 12 with the temporary bonding glue 121 facing downwards according to a certain position precision, the size of the carrier plate 12 is the same as the wafer size of the MEMS chip 11 to be bonded, and the material can be metal, silicon (Si), glass and the like;
step S102, plastic packaging: embedding the MEMS chip into organic resin by related equipment, wherein the resin can be mold top (molding) glue, and can also be other related resin materials such as epoxy, polyimide (PI), benzocyclobutene (BCB) and the like, and the materials can be in liquid state, solid state, film shape and the like, and the used equipment can be a plastic packaging machine, a film pressing machine, a high-temperature press and the like;
Step S103, detaching the temporary bonding bearing plate: the bearing plate is detached and bonded with the wafer embedded with the chip, so that I/O pins (pads) on the chip are exposed and are ready for the next RDL manufacture;
step S104, manufacturing an RDL insulating layer: an insulating layer is manufactured on the wafer on the front surface of the chip, and the insulating layer can be made of organic resin or inorganic material, and the manufacturing method comprises spraying, spin coating, film pressing, vapor deposition and the like;
Step S105, manufacturing blind holes for connecting RDL with the chip: removing the insulating layer at the position corresponding to the chip pad by a certain process method to form a blind hole, wherein the process method can be a drilling process, an exposure and development process, a dry etching process or a wet etching process and the like;
Step S106, RDL circuit layer manufacturing: manufacturing a redistribution circuit layer of the pad on the chip through the process steps of manufacturing a seed layer, electroplating, exposing, developing, etching and the like, manufacturing a passivation layer on the circuit layer for protecting the circuit of the RDL, and manufacturing a corresponding UBM layer at the position of the ball implantation;
Step S107, flip chip bonding process (Bumping): micro bumps (micro bumps) connected with the MEMS chip are manufactured at positions corresponding to the I/O bumps of the MEMS chip through a flip-chip bonding process, and the bump can be made of copper pillar bumps (Copper pillar bump) and the like.
The MEMS chip is led out to the outside through the fan-out packaging mode in a manner of welding a bump (bump) and is connected to the outside through a fan-in mode of the ASIC chip, so that the integrated packaging of the MEMS chip and the ASIC chip can be realized through the wafer-level packaging. The wafer-level packaging is adopted, so that paths between chips and paths connected with the outside are effectively shortened, and the performance of the system is improved. The high-speed signal of the ASIC chip can be ensured to be transmitted by directly leading out the high-speed signal to the outside through the RDL from the back of the ASIC chip.
In one embodiment, the step S102 specifically includes:
The mems chip is embedded in the organic resin and the functional area 111 of the mems chip is exposed, resulting in a wafer embedded with the chip.
The functional area of the micro-electromechanical system chip is exposed, so that the MEMS chip can communicate with the outside conveniently.
In one embodiment, the MEMS bumps are disposed within a projected area of the organic resin.
In the embodiment, the micro-electromechanical system bump is arranged in the projection range of the organic resin, so that the micro-electromechanical system bump can be cut in the range of the organic resin during cutting, and the MEMS chip is not influenced.
FIG. 2 is a flow chart showing a method of packaging a MEMS device according to the present invention, comprising:
step S201, fan-out packaging is carried out on the micro-electromechanical system chip by using the micro-electromechanical system chip wafer packaging method to obtain a micro-electromechanical system chip wafer, and fan-in packaging is carried out on the special-purpose integrated circuit chip to obtain the special-purpose integrated circuit chip wafer;
And S202, packaging the MEMS chip wafer and the special integrated circuit chip wafer to obtain a MEMS level packaging structure comprising the MEMS chip wafer and the special integrated circuit chip wafer.
The invention adopts wafer-level packaging to effectively shorten the paths between chips and connected with the outside, thereby improving the performance of the system. The high-speed signal of the ASIC chip can be ensured to be transmitted by directly leading out the high-speed signal to the outside through the RDL from the back of the ASIC chip.
As shown in fig. 3, in one embodiment, the step S202 specifically includes:
step S301, assembling and interconnecting a micro-electromechanical system chip wafer 1 with fan-out packaging and an application specific integrated circuit chip wafer 2 with fan-in packaging through a wafer-level bonding process;
specifically, the mems die wafer 1 with fan-out package and the asic die wafer 2 with fan-in package are assembled and interconnected by a wafer level bonding process to the mems bumps 19 of the mems die wafer and the asic bumps 22 of the asic die wafer.
Step S302, releasing the required physical structure of the micro-electromechanical system on the back surface of the micro-electromechanical system chip wafer 1 through an etching process;
Step S303, cap bonding is carried out on the micro-electromechanical system chip wafer 1 through a wafer level bonding process;
step S304, manufacturing a solder ball array ball 3 on the back surface of the special integrated circuit chip wafer 2;
And step S305, dicing the MEMS chip wafer 1 and the application specific integrated circuit chip wafer 2 to obtain the MEMS level packaging structure comprising the MEMS chip wafer and the application specific integrated circuit chip wafer.
Specifically:
Step S301, MEMS wafer level bonding: the packaging-completed MEMS chip wafer and ASIC chip wafer are assembled and interconnected through a wafer-level bonding process;
step S302, MEMS chip structure release: releasing the MEMS physical structure required by the MEMS chip wafer through an etching process on the back surface of the MEMS chip wafer, wherein the back surface of the MEMS chip wafer is consistent with the back surface direction of the MEMS chip;
Step S303, manufacturing a MEMS chip cap (cap): bonding CAP required by the MEMS chip wafer through a wafer-level bonding process, so as to protect movable structural components of the MEMS chip;
Step S304, implanting Ball array (Ball GRID ARRAY, BGA) balls: the BGA balls are planted at the bump positions on the back of the ASIC chip so as to complete the direct connection ports with the outside;
step S305, dicing: dicing is performed to form a MEMS system in package structure comprising a MEMS chip wafer and its ASIC driver chip wafer.
The embodiment particularly realizes the MEMS packaging of the MEMS chip wafer and the application specific integrated circuit chip wafer.
As shown in fig. 4, in one embodiment, the fan-in packaging the asic chip to obtain an asic chip wafer specifically includes:
step S401, temporarily bonding the front surface of the special integrated circuit chip 21 with the special integrated circuit bump 22 and the special integrated circuit carrier plate 23;
Step S402, thinning the special integrated circuit chip 21 from the back to the designed thickness;
step S403, setting an etched silicon groove area on the back of the special integrated circuit chip 21, and etching a silicon groove 24 in the etched silicon groove area;
step S404, manufacturing a first special integrated circuit insulating layer 25 in the silicon groove 24 and on the back surface of the special integrated circuit chip 21;
Step S405, a bottom groove 26 is cut at the bottom of the silicon groove 24 in a cutting mode, and the cutting depth is controlled at the interface position of the special integrated circuit pin on the front surface of the special integrated circuit chip and the temporarily-bonded adhesive 27;
Step S406, manufacturing a metal layer 28 in the silicon groove 24;
step S407, electroplating and thickening the deposited metal layer 28, and then manufacturing an application specific integrated circuit rewiring line layer 29 electrically connected with the pins of the application specific integrated circuit;
step S408, a second special integrated circuit insulating layer 210 covering the special integrated circuit rewiring line layer is manufactured, and an under-ball metal layer of the special integrated circuit is manufactured at the ball implantation position of the ball array;
in step S409, the asic chip 21 and the asic carrier 23 are separated by means of de-bonding, so as to obtain a packaged asic chip wafer.
Specifically:
Step S401, temporary bonding: temporarily bonding the front surface of the ASIC chip with an application specific integrated circuit bump (bump) with a temporarily bonded carrier plate, wherein the temporary bonding adhesive or a temporary bonding adhesive film can be used;
step S402, chip thinning: thinning the ASIC chip from the back to a required thickness;
Step S403, etching the back surface of the chip: protecting the area outside the etched silicon cavity by a photoresist process, and then etching a silicon groove shown in the figure by an etching process (dry or wet process), wherein the groove has a certain bevel edge, so that the subsequent RDL circuit layer can be conveniently manufactured;
Step S404, manufacturing a protective layer in a silicon groove: manufacturing an insulating layer in a silicon groove and on the surface of silicon in a spraying mode or manufacturing an insulating layer and a protective layer in a deposition mode;
step S405, groove scribing: cutting a trapezoid bottom groove shown at the bottom of the silicon groove in a cutting mode, wherein the cutting depth is controlled at the interface position of a metal pin (pad) on the front surface of the chip and the adhesive for temporary bonding;
step S406, in-groove metal layer deposition manufacturing: depositing a barrier layer, a seed layer and other metal layers in the metal groove;
Step S407, electroplating a circuit layer and manufacturing an RDL circuit layer: thickening the deposited metal layer in a pattern plating or full-plate plating mode, and then manufacturing a packaged RDL circuit layer through a photoresist mask layer;
Step S408, preparing an RDL insulating layer: manufacturing an insulating layer above the RDL circuit layer in a spraying or depositing mode, and manufacturing a Ball Grid Array (BGA) UBM layer at a BGA ball-implanting position;
step S409, bonding is performed: the encapsulated chip wafer is separated from the carrier plate by means of de-bonding.
In this embodiment, the ASIC chip is fan-in packaged, so as to reduce the packaging volume.
In one embodiment, the projection of the etched silicon trench region is between two adjacent integrated circuit bumps.
In this embodiment, the projection of the etched silicon groove area is between two adjacent integrated circuit bumps, so that the silicon groove is also between two adjacent integrated circuit bumps, which is convenient for later dicing.
In one embodiment, the dicing the mems die wafer and the asic die wafer specifically includes:
And scribing the MEMS chip wafer and the special integrated circuit chip wafer at the position of the silicon groove of the special integrated circuit chip wafer.
FIG. 5 is a system architecture diagram of a MEMS of the present invention, comprising: the MEMS chip wafer 1 adopting fan-out encapsulation and the ASIC chip wafer 2 adopting fan-in encapsulation are adopted, the MEMS chip wafer 1 is provided with a MEMS bump 19 electrically connected with a MEMS pin, and the MEMS bump 19 is electrically connected with an ASIC bump 22 on the front side of the ASIC chip wafer 2.
The MEMS chip is led out to the outside through the fan-out packaging mode in a manner of welding a bump (bump) and is connected to the outside through a fan-in mode of the ASIC chip, so that the integrated packaging of the MEMS chip and the ASIC chip can be realized through the wafer-level packaging. The wafer-level packaging is adopted, so that paths between chips and paths connected with the outside are effectively shortened, and the performance of the system is improved. The high-speed signal of the ASIC chip can be ensured to be transmitted by directly leading out the high-speed signal to the outside through the RDL from the back of the ASIC chip.
In one embodiment, the mems die wafer 1 comprises: the MEMS chip 11 is embedded in the organic resin 13, a layer of MEMS insulating layer 15 is arranged on the front surface of the MEMS chip 11, a blind hole 16 is arranged at a position of the MEMS insulating layer 15 corresponding to the MEMS pin 14 of the MEMS chip, a MEMS rewiring layer 17 electrically connected with the MEMS pin 14 through the blind hole 16 is arranged on the insulating layer 15, a MEMS passivation layer 18 is arranged on the MEMS rewiring layer 17, and a MEMS bump 19 electrically connected with the MEMS pin 14 through an under-ball metal layer is arranged on the MEMS passivation layer 18.
The MEMS chip of the present embodiment is a fan-out package structure, so that the size of the MEMS chip can be integrated with the ASIC chip wafer to realize wafer level package.
In one embodiment, the asic die wafer 2 comprises: the special integrated circuit chip 21, the front of the special integrated circuit chip 21 is provided with a special integrated circuit bump 22, the back of the special integrated circuit chip 21 is etched with a silicon groove 24, the bottom of the silicon groove 24 is provided with a bottom groove 26, a first special integrated circuit insulating layer 25 is arranged in the silicon groove 24 and on the back of the special integrated circuit chip 21, a metal layer 28 thickened by electroplating is deposited in the silicon groove 24, a special integrated circuit rewiring line layer 29 electrically connected with the special integrated circuit pins is arranged on the first special integrated circuit insulating layer 25, a second special integrated circuit insulating layer 210 is arranged above the special integrated circuit rewiring line layer 29, an under-ball metal layer of the special integrated circuit is arranged at the ball placement position of the solder ball array of the second special integrated circuit insulating layer 210, and a solder ball array ball 3 is arranged on the under-ball metal layer of the special integrated circuit.
The ASIC chip of this embodiment is a fan-in package structure, so that its size can achieve wafer level package with the wafer of the MEMS chip.
The foregoing examples illustrate only a few embodiments of the invention and are described in detail herein without thereby limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (8)
1. A method for packaging a chip wafer of a microelectromechanical system, comprising:
Temporarily bonding the front surface of the micro-electromechanical system chip and the micro-electromechanical system bearing plate;
Embedding the micro-electromechanical system chip in the organic resin to obtain a wafer embedded with the chip;
Bonding a micro-electromechanical system bearing plate with the wafer in a unbonded manner, and exposing micro-electromechanical system pins on the micro-electromechanical system chip;
Manufacturing a micro-electromechanical system insulating layer on the front surface of the micro-electromechanical system chip;
removing the micro-electromechanical system insulating layer at the corresponding position of the micro-electromechanical system pin of the micro-electromechanical system chip to form a blind hole;
manufacturing a micro-electromechanical system rewiring layer electrically connected with the micro-electromechanical system pin through the blind hole, manufacturing a passivation layer covering the micro-electromechanical system rewiring layer, and manufacturing a micro-electromechanical system under-ball metal layer at a position corresponding to the micro-electromechanical system bump;
and manufacturing a micro-electromechanical system bump electrically connected with the micro-electromechanical system pin on the micro-electromechanical system under-ball metal layer to obtain the micro-electromechanical system chip wafer with the fan-out packaged.
2. The method for encapsulating a mems chip wafer according to claim 1, wherein the embedding the mems chip in an organic resin, to obtain a chip embedded wafer, specifically comprises:
and embedding the micro-electromechanical system chip into the organic resin, and exposing the functional area of the micro-electromechanical system chip to obtain the wafer embedded with the chip.
3. The method of claim 1, wherein the mems bump is disposed within a projection range of the organic resin.
4. A method of packaging a microelectromechanical system, comprising:
Fan-out packaging of a mems chip to obtain a mems chip wafer, and fan-in packaging of an asic chip to obtain an asic chip wafer, using the mems chip wafer packaging method of any one of claims 1 to 3;
and packaging the MEMS chip wafer and the special integrated circuit chip wafer to obtain the MEMS-level packaging structure comprising the MEMS chip wafer and the special integrated circuit chip wafer.
5. The method of claim 4, wherein the step of performing mems packaging on the mems die wafer and the asic die wafer to obtain a mems-level package structure including an mems die wafer and an asic die wafer specifically comprises:
assembling and interconnecting a micro-electromechanical system chip wafer with fan-out packaging and an application specific integrated circuit chip wafer with fan-in packaging through a wafer-level bonding process;
Releasing the required physical structure of the micro-electromechanical system on the back surface of the micro-electromechanical system chip wafer through an etching process;
performing cap bonding on a micro-electromechanical system chip wafer through a wafer-level bonding process;
Manufacturing a solder ball array ball on the back surface of the special integrated circuit chip wafer;
And scribing the MEMS chip wafer and the application specific integrated circuit chip wafer to obtain the MEMS level packaging structure comprising the MEMS chip wafer and the application specific integrated circuit chip wafer.
6. The method of claim 5, wherein the fan-in packaging the asic chip to obtain the asic chip wafer, specifically comprises:
temporarily bonding the front surface of the special integrated circuit chip with the special integrated circuit convex block with the special integrated circuit bearing plate;
Thinning the special integrated circuit chip from the back to a designed thickness;
setting an etched silicon groove area on the back of the special integrated circuit chip, and etching a silicon groove in the etched silicon groove area;
Manufacturing a first special integrated circuit insulating layer in the silicon groove and on the back of the special integrated circuit chip;
a bottom groove is cut at the bottom of the silicon groove in a cutting mode, and the cutting depth is controlled at the interface position of the special integrated circuit pin on the front surface of the special integrated circuit chip and the adhesive which is temporarily bonded;
manufacturing a metal layer in the silicon groove;
Electroplating and thickening the deposited metal layer, and then manufacturing an application specific integrated circuit rewiring circuit layer electrically connected with the pin of the application specific integrated circuit;
Manufacturing a second special integrated circuit insulating layer covering the special integrated circuit rewiring line layer, and manufacturing an under-ball metal layer of the special integrated circuit at a ball implantation position of the ball array;
and separating the special integrated circuit chip from the special integrated circuit carrier plate in a de-bonding mode to obtain the packaged special integrated circuit chip wafer.
7. The method of claim 6, wherein the projection of the etched silicon trench region is between two adjacent integrated circuit bumps.
8. The method of claim 6, wherein dicing the mems die wafer and the asic die wafer, comprises:
And scribing the MEMS chip wafer and the special integrated circuit chip wafer at the position of the silicon groove of the special integrated circuit chip wafer.
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