CN108959106A - Memory pool access method and device - Google Patents

Abstract

The present application discloses a memory access method and device, which belong to the field of memory technology. The method includes: receiving a memory access request; the memory access request is used to request access to a target row in a dynamic random access memory DRAM; When the row is a weak row, determine the corresponding mapping address of the target row in the reserved domain in the DRAM according to the offset table and the preset start address; the offset table includes The address offset corresponding to the weak row in the reserved field, the preset start address is the start address of the reserved field; the address offset is set in the reserved field The pointed row is not a weak row; the reserved field is accessed according to the mapped address; and the access result is returned. It solves the problem in the related art that there are many refresh commands in the bus, which may cause bus congestion and reduce the performance of the system; the effect of avoiding bus congestion and improving performance is achieved.

Description

Memory access method and device

technical field

The present application relates to the technical field of memory, in particular to a memory access method and device.

Background technique

A dynamic random access memory (Dynamic Random Access Memory, DRAM) uses a transistor and a capacitor to form a unit, and then stores one bit of data.

However, over time, the capacitor will leak charge and cause the data stored in the cell to be lost. Therefore, in order to maintain the data stored in the cells, the operation of refreshing the data stored in each cell will be periodically performed, and in actual implementation, the row (Wordline (Wordline) connects multiple cells in the same row in series to form a row) as Unit to perform refresh operations. Most of the units in DRAM maintain data for more than 256ms, while a small number of units maintain data for less than 256ms or even less than 64ms. Therefore, in order to ensure that the data of each unit in a certain row will not be lost, it is necessary to use less than The refresh cycle of the target duration to refresh the data in the row. Wherein, the target duration is the maintenance time corresponding to the unit with the shortest maintenance time in the row. For example, if the holding time corresponding to the unit with the shortest holding time in a certain row is 40ms, then for this row, it needs to be refreshed with a duration less than 40ms, for example, a refresh period of 35ms is used for refreshing.

In the above solution, when there are many weak rows in the DRAM, since the refresh cycle for refreshing each weak row is short, there are many refresh commands in the bus, which may cause bus congestion and reduce system performance.

Contents of the invention

In order to solve the problem of low performance of a bus congestion system in the related art, an embodiment of the present application provides a memory access method and device.

In the first aspect, a memory access method is provided, and the memory access method includes:

Receive a memory access request; the memory access request is used to request access to a target row in the dynamic random access memory DRAM;

When the target line is a weak line, determine the corresponding mapping address of the target line in the reserved domain in the DRAM according to the offset table and the preset start address; the offset table includes the weak line in the DRAM in the reserved The address offset corresponding to the domain, the default starting address is the starting address of the reserved domain; the row pointed to by the address offset in the reserved domain is not a weak row;

Access the reserved domain according to the mapped address;

Return access result.

When the target row requested to be accessed is a weak row, the corresponding mapping address of the target row in the DRAM reserved area is calculated according to the pre-saved offset table and the preset start address, and then the DRAM is accessed according to the mapping address The reserved field in , returns the access result; among them, since the row pointed to by each address offset in the offset table in the reserved field is not a weak row, the above scheme passes conversion when requesting to access a weak row Its access address makes it possible to access normal rows in the DRAM, so that when the DRAM is refreshed subsequently, it can be refreshed according to the normal refresh cycle, which solves the problem that there are many refresh commands in the bus in the related art, which may cause bus congestion and reduce system performance. Performance issues; achieve the effect of avoiding bus congestion and improving performance.

In the first possible implementation manner, the access result is returned, including:

receiving a return result carrying a first address returned by the DRAM, where the first address is an accessed address in the DRAM;

calculating the difference between the first address and the preset starting address;

If the difference is greater than 0, calculate the second address corresponding to the first address according to the offset table and the preset start address;

Return the access result carrying the second address.

In a second possible implementation, the method further includes:

Detect whether the target row is a row in the weak row list, and the weak row list includes each weak row in the DRAM;

If so, determine that the target row is a weak row.

In combination with the second possible implementation, in the third possible implementation, the method further includes:

For each row in the DRAM, detecting whether the row includes cells whose duration is less than a preset duration;

If it includes units whose maintenance time is less than the preset duration, the row is determined as a weak row;

A list of weak rows is generated and saved based on the determination result.

In combination with the first aspect and the above-mentioned several possible implementations of the first aspect, in a fourth possible implementation, the location of the target row in the reserved area in the DRAM is determined according to the offset table and the preset start address. Before the corresponding mapped address, the method also includes:

Obtain the number of weak rows in the DRAM and the size of each weak row;

Calculate the total size corresponding to each weak row in the DRAM according to the obtained number of rows and the size of each weak row;

Reserve a storage space of a preset size in the DRAM as a reserved domain, and the preset size is greater than or equal to the calculated total size;

Save the start address of the reserved domain as the default start address.

In combination with the first aspect and the above-mentioned several possible implementations of the first aspect, in a fifth possible implementation, the location of the target row in the reserved area in the DRAM is determined according to the offset table and the preset start address. Before the corresponding mapped address, the method also includes:

According to the sorting of each weak row in the DRAM, determine the address offset corresponding to each weak row in the reserved field;

An offset table including offsets for individual addresses is maintained.

In a second aspect, there is provided a memory access device, which includes: a memory controller and a DRAM connected to the memory controller; the memory controller is configured to execute instructions, and the memory controller realizes the above-mentioned first aspect by executing the instructions memory access method.

Description of drawings

FIG. 1 is a schematic diagram of the implementation environment involved in various embodiments of the present application;

Fig. 2 is a method flowchart of a memory access method provided by an embodiment of the present application;

FIG. 3 is a schematic diagram of determining the address offset of a weak row by a memory controller provided by an embodiment of the present application;

FIG. 4 is a schematic diagram of an offset table stored by a memory controller provided by an embodiment of the present application;

FIG. 5 is a schematic block diagram of a memory access method provided by an embodiment of the present application;

Fig. 6 is a schematic diagram of a memory access device provided by an embodiment of the present application.

Detailed ways

"First", "second" and similar words mentioned herein do not indicate any order, quantity or importance, but are only used to distinguish different components. Likewise, words like "a" or "one" do not denote a limitation in quantity, but indicate that there is at least one. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

The "module" mentioned in this article usually refers to the program or instruction that can realize certain functions stored in the memory; the "unit" mentioned in this article usually refers to a functional structure divided according to logic, and the "unit" It can be implemented by pure hardware, or a combination of software and hardware.

The "plurality" mentioned herein means two or more. "And/or" describes the association relationship of associated objects, indicating that there may be three types of relationships, for example, A and/or B may indicate: A exists alone, A and B exist simultaneously, and B exists independently. The character "/" generally indicates that the contextual objects are an "or" relationship.

Please refer to FIG. 1, which shows a schematic diagram of an implementation environment involved in various embodiments of the present invention. As shown in FIG. 1, the implementation environment includes a central processing unit (Central Processing Unit, CPU) 110, a memory controller 120 and a DRAM 130 . in:

CPU 110 is used to access DRAM 130 through memory controller 120 . For example, the CPU 110 may send a read/write request for reading and writing memory to the memory controller 120 . In actual implementation, there may be one or more CPUs 110 , which is not limited.

The memory controller 120 refers to a device used to control the DRAM 130 in the terminal. For example, after receiving the read/write request sent by the CPU 110 , the memory controller 120 may perform read/write operations on the DRAM according to the address requested for read/write in the read/write request. In addition, the memory controller 120 may also receive the read and write results returned by the DRAM, and feed back the read and write results to the CPU 110 .

Please refer to FIG. 2 , which shows a method flowchart of a memory access method provided by an embodiment of the present application. This embodiment is described by using the method in the memory controller shown in FIG. 1 as an example. As shown in Figure 2, the memory access method includes the following steps:

Step 201 , for each row in the DRAM, check whether the row includes cells whose retention time is shorter than a preset duration.

After the DRAM memory is inserted into the terminal for the first time, for each row in the DRAM, the memory controller may detect whether the row includes cells whose maintenance time is shorter than a preset duration. Wherein, the preset duration is a preset duration in the memory controller, and the preset duration can be 256ms. Of course, in actual implementation, according to different actual design requirements, the preset duration can also be other values, such as 128ms or 64ms , which is not limited in this embodiment.

In actual implementation, for each unit in each row, the memory controller can detect whether the maintenance time of the unit is less than the preset duration, and if the detection result is less than, then determine that the row includes units whose maintenance time is shorter than the preset duration; And if the detection result is not less than, the memory controller may continue to detect other cells in the row until all the cells in the row are detected.

Step 202, if the unit with the maintenance time shorter than the preset duration is included, the row including the unit with the maintenance time shorter than the preset duration is determined as a weak row.

If a certain row includes a unit whose maintenance time is shorter than a preset duration, it means that the data stored in the unit will be lost in a short time, and at this time, the memory controller can determine that the behavior is weak.

On the other hand, if a row does not include cells whose maintenance time is shorter than a preset duration, the memory controller can determine that the behavior is normal.

Step 203, generate and save a list of weak rows according to the determination result.

The list of weak rows includes each weak row in the DRAM. In actual implementation, the weak row list includes the address of each weak row. For example, a certain row in the DRAM is a weak row, and the address of the row (here, the starting address of the row) is 0xff00, then the list of weak rows can include 0xff00.

Optionally, the memory controller may keep this list of weak rows in hardware itself.

It should be added that steps 201 to 203 are steps performed by the memory controller after the DRAM is inserted into the terminal for the first time.

Step 204, acquiring the number of weak rows in the DRAM and the size of each weak row.

After the terminal is restarted, the memory controller can obtain the number of weak rows in the DRAM and the size of each weak row. in:

The steps for the memory controller to obtain the number of weak rows include: reading the list of weak rows saved by itself, and counting the numbers of all weak rows according to the reading result.

The step for the memory controller to obtain the size of each weak row includes: reading the preset size of each row in the DRAM. DRAM is an array memory. The number of cells in each row is the same, that is, the size of each row is the same and is determined by the DRAM hardware. Therefore, the memory controller can directly read the size of the row in the DRAM. For example, if the size of a row in a certain DRAM is 8kB, the memory controller can read and obtain that the size of each weak row is 8kB.

Step 205: Calculate the total size corresponding to the weak rows in the DRAM according to the acquired number of rows and the size of each weak row.

Optionally, the memory controller may calculate the product of the obtained number of rows and the size of each weak row, and use the product as a total size corresponding to each weak row in the DRAM.

Step 206: Reserve a storage space of a preset size in the DRAM as a reserved area, and the preset size is greater than or equal to the calculated total size.

After calculating the total size, the memory controller can reserve a storage space of a preset size in the DRAM. The preset size may be the calculated total size, and in order to ensure the normal operation of the DRAM, the preset size may also be the total size + a fixed size, the fixed size is the size of the storage space reserved for subsequent use .

Optionally, the memory controller can reserve a storage space of a preset size at the end of the DRAM; or, reserve a storage space of a preset size at the start address of the DRAM; or, at a preset location of the DRAM A storage space of a preset size is reserved, which is not limited in this embodiment. And, unless otherwise specified, the storage space reserved at the end is used as an example below.

It should be noted that the storage areas in the DRAM other than the reserved domains are normal domains.

Step 207, saving the start address of the reserved domain as a preset start address.

After the memory controller reserves the reserved domain, the memory controller may save the start address of the reserved domain as a preset start address. In actual implementation, the memory controller may store the preset start address in its own base address register (Base Address Register).

Step 208, according to the sorting of each weak row in the DRAM, determine the address offset corresponding to each weak row in the reserved field.

The memory controller can obtain the order of each weak row according to the address of each weak row in the weak row list. For example, the memory controller acquires that the weak rows in a certain DRAM are the 3rd row, the 10th row, the 12th row, etc. The ranking in the weak row is the first, and the ranking of each weak row can be obtained by analogy. Optionally, the memory controller can obtain the ordering of individual weak rows in the normal domain.

Thereafter, the memory controller determines the address offset of each weak row according to the acquired ordering. Optionally, for the weak row ranked i, the memory controller may determine i as the address offset of the weak row. For example, for the weak line in the third line above, the memory controller can determine that the address offset of the weak line is 0, and for the weak line in the tenth line, the memory controller can determine that the address offset of the weak line is 1.

In actual implementation, since weak lines may also be included in the reserved field, in order to avoid corresponding weak lines in the reserved field after the offset, when determining the address offset, for the weak line ranked i row, the memory controller can detect whether the row after offset j in the reserved field is a weak row, if so, add j+1, and check again whether the row after offset j in the reserved field is a weak row, until offset If the row after shifting j is not a weak row, determine j as the address offset of the weak row; and if not, determine j as the address offset of the weak row. Wherein, j-1 refers to the address offset corresponding to the weak row ranked i-1.

In an illustrative example, for the weak line of the third line above, since the start address of the reserved field, that is, the first line of the reserved field is not a weak line, the memory controller can determine 0 as the line address offset; and for the weak line of the 10th line above, since the 2nd line in the reserved field is a weak line, the memory controller can detect whether the 3rd line in the reserved field is a weak line, and if it is not When a row is weak, 2 is determined as the address offset of the row, and so on, the memory controller can determine the address offset corresponding to each weak row in the normal domain. For example, it is determined that the obtained address offsets are 0, 2, 3, 6, 7 and so on.

For example, please refer to FIG. 3 , which shows a possible schematic diagram of the memory controller determining the address offset.

It should be noted that since the size of each row in the DRAM is the same and fixed, the above-mentioned row after the offset j refers to the corresponding space after the offset j*n in the reserved area. Wherein, n is the size of each row in the DRAM.

Another point that needs to be explained is that the above is only an example of the address offset represented by the number of offset lines. In actual implementation, the address offset can also be expressed by the offset address, that is, the address offset It is the difference between the address after offset and the address before offset.

Step 209, saving an offset table including each address offset.

Optionally, the memory controller can save the offset table itself through hardware. For example, please refer to FIG. 4, which shows a possible offset table kept by the memory controller.

Step 210, receiving a memory access request; the memory access request is used to request access to a target row in the DRAM.

When the CPU needs to access the DRAM, the CPU can send a memory access request to the memory controller, and the memory controller can correspondingly receive the memory access request. Wherein, the memory access request may be a read request or a write request, and in actual implementation, the memory access request carries the target address of the target row requested to be accessed.

For example, when the CPU needs to write content to 0xfff0 in the DRAM, the CPU can send a write request carrying 0xfff0 to the memory controller.

Optionally, after receiving the memory access request, the memory controller puts the memory access request into an input queue (Input Queue).

Step 211, detecting whether the target row is a row in the weak row list.

The memory controller can detect whether the target address in the memory access request is included in the weak line list, and if so, determine that the target line requested to be accessed is a weak line, otherwise, determine that the target line requested to access is not a weak line.

Step 212, if yes, determine that the target row is a weak row.

And if the detection result shows that the target row is not a weak row, then at this time, the memory controller can access the DRAM through the access method provided by the related technology, which will not be repeated here.

Step 213, when the target row is a weak row, determine the corresponding mapping address of the target row in the reserved area in the DRAM according to the offset table and the preset start address.

If the memory controller detects that the target row requested to be accessed is a weak row, it means that the data stored in the row may be lost. At this time, in order to ensure data security, the memory controller can query the offset table corresponding to the address offset, and determine the address in the reserved field after the address offset obtained by offsetting the query from the preset start address as the corresponding mapping address of the target row in the reserved field.

For example, if the default starting address is 0xfff0, then when the queried address offset is 0, the determined mapping address is 0xfff0; and when the queried address offset is 1, the determined mapping address is The address after offsetting one line from 0xfff0.

Optionally, after determining the mapping address, the memory controller may convert the memory access request into a series of DRAM commands, and put the DRAM commands into a queue pool (Queue Pool).

Step 214, access the reserved domain according to the mapped address.

The memory controller can directly access the location corresponding to the mapped address in the reserved domain. For example, when the memory access request is a write request, the content is written into the storage space corresponding to the mapping address; for another example, when the memory access request is a read request, the content in the storage space corresponding to the mapping address is read.

In actual implementation, the memory controller can select the command to be executed in the queue pool according to the preset scheduling strategy, and then use the signal interface to send the selected command to the DRAM. Perform the corresponding operation.

Step 215, receiving the access result carrying the first address returned by the DRAM. The first address is an address accessed in the DRAM.

After the memory controller accesses the reserved domain in the DRAM according to the mapped address, the DRAM can return the access result to the memory controller. Wherein, the address of the access result returned by the DRAM is an address actually accessed in the DRAM. That is, it is assumed that when the memory controller accesses the DRAM according to the mapped address, the mapped address is carried in the access result.

In actual implementation, the access result may also include other content, for example, when the memory access request is a read request, the access result may also include the read content; and when the memory access request is a write request, the access result may also include a writing result such as carrying successful writing information or carrying failed writing information.

Step 216, calculating the difference between the first address and the preset start address.

After receiving the access result, the memory controller may calculate the difference between the first address in the access result and the preset start address.

Step 217, if the difference is greater than 0, calculate the second address corresponding to the first address according to the offset table and the preset start address.

If the difference is greater than 0, it means that the access result accesses the content in the reserved field in the DRAM, that is, the behavior requested by the memory access request is a weak row in the DRAM. Therefore, in order to restore the corresponding The original address, so that the CPU can identify the access result, and the memory controller can calculate the second address corresponding to the first address according to the offset table and the preset start address.

Optionally, the memory controller may query the address of the weak row corresponding to the calculated difference in the offset table, and use the address of the weak row obtained through query as the second address. For example, if the difference between the first address and the preset start address is 2 lines, then it can be determined that the address offset is 2. At this time, the memory controller can query in the offset table described in FIG. 4 The address of the weak row at address offset 2.

It should be noted that if the difference is less than 0, it means that the memory access request accesses the normal domain in the DRAM, that is, the content of the normal row is accessed. At this time, the memory controller can directly return the access result to the CPU.

Step 218, return the access result carrying the second address.

Optionally, after the memory controller determines the second address, the access result after the updated address can be added to the return transaction queue (Return Transaction Queue), and then return the content in the return transaction queue to the CPU according to the preset scheduling rule .

Please refer to FIG. 5 , which shows a schematic diagram of a memory access method provided by this embodiment.

In an exemplary embodiment, the total capacity of the DRAM is 32GB, and includes 2 channels, each channel has 4 memory blocks (rank), each rank has 8 memory array banks, and each bank has 64000 rows. Each row is 8KB in size. Among them, there are 28 rows whose duration is less than 128ms, 978 rows whose duration is between 128ms and 256ms, and the duration of all remaining rows exceeds 256ms. The present invention regards the 1006 lines whose maintenance time is less than 256ms as weak lines, and divides the 32GB storage space into two parts, the normal domain and the reserved domain, wherein the size of the reserved domain is 8KB*(28+978)=7.86 MB, less than 0.024% of the total capacity, but in the above-mentioned scheme, when the memory controller refreshes the data stored in each unit in the DRAM, the memory controller can refresh with a refresh cycle of 256ms, which is what this embodiment provides The solution uses 0.024% of the total storage space in exchange for 4 times the refresh cycle.

It should be noted that steps 210 to 218 may be performed once or multiple times after step 209, which is not limited in this embodiment.

Another point that needs to be explained is that each of the above-mentioned embodiments uses a memory controller as an example to implement the above method. In actual implementation, it can also be implemented through a newly added controller, which can be located between the CPU and the memory controller. , or between the memory controller and the DRAM, which is not limited.

To sum up, the memory access method provided by this embodiment, when the target row requested to be accessed is a weak row, calculates the reserved area of the target row in the DRAM according to the pre-saved offset table and the preset start address The corresponding mapping address in the DRAM, and then access the reserved domain in the DRAM according to the mapping address, and return the access result; wherein, because each address offset in the offset table points to a row in the reserved domain is not weak Therefore, the above scheme can access the normal row in the DRAM by converting its access address when requesting to access the weak row, so that the follow-up DRAM can be refreshed according to the normal refresh cycle when refreshing the DRAM, which solves the problems in the bus in the related art. There are many refresh commands, which may cause bus congestion and reduce the performance of the system; the effect of avoiding bus congestion and improving performance is achieved.

Please refer to FIG. 6, which shows a schematic structural diagram of a memory access device provided by an embodiment of the present invention. As shown in FIG. 6, the memory access device may include: a receiving unit 610, a determining unit 620, an accessing unit 630 and a returning unit 640.

The receiving unit 610 is configured to receive a memory access request; the memory access request is used to request access to a target row in a dynamic random access memory DRAM;

A determining unit 620, configured to determine a corresponding mapping address of the target row in a reserved domain in the DRAM according to an offset table and a preset start address when the target row is a weak row; The offset table includes the address offset corresponding to the weak line in the DRAM in the reserved area, and the preset start address is the start address of the reserved area; the address offset the row pointed to by the offset in the reserved field is not a weak row;

An access unit 630, configured to access the reserved domain according to the mapped address;

A return unit 640, configured to return an access result.

To sum up, the memory access device provided by this embodiment, when the target row requested to be accessed is a weak row, calculates the reserved area of the target row in the DRAM according to the pre-saved offset table and the preset start address. The corresponding mapping address in the DRAM, and then access the reserved domain in the DRAM according to the mapping address, and return the access result; wherein, because each address offset in the offset table is not weak in the row pointed to in the reserved domain Therefore, the above scheme can access the normal row in the DRAM by converting its access address when requesting to access the weak row, so that the follow-up DRAM can be refreshed according to the normal refresh cycle when refreshing the DRAM, which solves the problems in the bus in the related art. There are many refresh commands, which may cause bus congestion and reduce the performance of the system; the effect of avoiding bus congestion and improving performance is achieved.

Based on the memory access device provided in the foregoing embodiments, optionally, the returning unit 640 is also configured to:

receiving a return result that carries a first address returned by the DRAM, where the first address is an address accessed in the DRAM;

calculating a difference between the first address and the preset start address;

If the difference is greater than 0, calculate a second address corresponding to the first address according to the offset table and the preset start address;

Returning the access result carrying the second address.

Optionally, the device also includes:

a first detection unit, configured to detect whether the target row is a row in a weak row list, and the weak row list includes each weak row in the DRAM;

The determining unit 620 is further configured to determine that the target row is a weak row when the detection result of the first detection unit is that the target row is a row in the weak row list.

Optionally, the device also includes:

The second detection unit is configured to, for each row in the DRAM, detect whether the row includes a unit whose maintenance time is shorter than a preset duration;

The determination unit 620 is further configured to determine the row as a weak row when the detection result of the second detection unit is that the row includes units whose maintenance time is less than the preset duration;

The first saving unit is configured to generate and save the weak row list according to the determination result.

Optionally, the device also includes:

An acquiring unit, configured to acquire the weak address in the DRAM before the determining unit determines the corresponding mapping address of the target row in the reserved domain in the DRAM according to the offset table and the preset start address the number of rows and the size of each weak row;

A calculation unit, configured to calculate the total size corresponding to each weak row in the DRAM according to the obtained number of rows and the size of each weak row;

A reservation unit, configured to reserve a storage space of a preset size in the DRAM as the reserved domain, where the preset size is greater than or equal to the calculated total size;

The second saving unit is configured to save the start address of the reserved domain as the preset start address.

Optionally, the device also includes:

The determining unit 620 is further configured to determine the corresponding mapping address of the target row in the reserved area in the DRAM according to the offset table and the preset start address, according to each of the DRAM Sorting the weak rows, determining the address offset corresponding to each weak row in the reserved field;

The third storage unit is configured to store the offset table including each address offset.

Those skilled in the art can appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution.

Those of ordinary skill in the art can clearly understand that for the convenience and brevity of description, the specific working process of the devices and units described above can refer to the corresponding process in the foregoing method embodiments, and details are not repeated here.

In the embodiments provided in this application, it should be understood that the disclosed devices and methods may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units may only be a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined Or it can be integrated into another system, or some features can be ignored, or not implemented.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

The above is only a specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the application. Should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims (12)

1. a kind of memory pool access method, which is characterized in that the described method includes:

Receive memory access request；The memory access request is used to request access to the mesh in dynamic RAM DRAM Mark row；

When the target line is weak row, determine the target line in the DRAM according to offset-lists and default initial address Reserved domain in corresponding mapping address；It include the institute in the reserved domain of the weak row in the DRAM in the offset-lists Corresponding address offset amount, the default initial address are the initial address in the reserved domain；The address offset amount is described In reserved domain it is pointed it is capable be not weak row；

The reserved domain is accessed according to the mapping address；

Backward reference result.

2. the method according to claim 1, wherein the backward reference result, comprising:

Receive the DRAM return carries returning the result for the first address, and first address is to be accessed in the DRAM Address；

Calculate the difference of first address Yu the default initial address；

If the difference is greater than 0, calculated corresponding to first address according to the offset-lists, the default initial address The second address；

Return carries the two address access result.

3. the method according to claim 1, wherein the method also includes:

Detect whether the target line is row in weak row-column list, includes each weak in the DRAM in the weak row-column list Row；

If so, determining that the target line is weak row.

4. according to the method described in claim 3, it is characterized in that, the method also includes:

Whether for every a line in the DRAM, detecting in the row includes the unit held time less than preset duration；

If the row is determined as weak row including the unit held time less than the preset duration；

It is generated according to definitive result and saves the weak row-column list.

5. method according to any one of claims 1 to 4, which is characterized in that described according to offset-lists and default starting point Before location determines target line mapping address corresponding in the reserved domain in the DRAM, the method also includes:

Obtain the line number of the weak row in the DRAM and the size of each weak row；

According to the size of the line number and each weak row that get, calculate total big corresponding to each weak row in the DRAM It is small；

The memory space of default size is reserved in the DRAM as the reserved domain, the default size, which is more than or equal to, to be calculated The obtained total size；

The initial address in the reserved domain is saved as into the default initial address.

6. method according to any one of claims 1 to 4, which is characterized in that described according to offset-lists and default starting point Before location determines target line mapping address corresponding in the reserved domain in the DRAM, the method also includes:

According to the sequence of each weak row in the DRAM, each weak row address offset corresponding in the reserved domain is determined Amount；

Save the offset-lists including each address offset amount.

7. a kind of internal storage access device, which is characterized in that described device includes:

Receiving unit, for receiving memory access request；The memory access request is deposited for requesting access to dynamic random-access Target line in reservoir DRAM；

Determination unit, for determining the target according to offset-lists and default initial address when the target line is weak row Row mapping address corresponding in the reserved domain in the DRAM；Exist in the offset-lists including the weak row in the DRAM Corresponding address offset amount in the reserved domain, the default initial address are the initial address in the reserved domain；Describedly Location offset in the reserved domain it is pointed it is capable be not weak row；

Access unit, for accessing the reserved domain according to the mapping address；

Return unit is used for backward reference result.

8. device according to claim 7, which is characterized in that the return unit is also used to:

Receive the DRAM return carries returning the result for the first address, and first address is to be accessed in the DRAM Address；

Calculate the difference of first address Yu the default initial address；

If the difference is greater than 0, calculated corresponding to first address according to the offset-lists, the default initial address The second address；

Return carries the two address access result.

9. device according to claim 7, which is characterized in that described device further include:

First detection unit includes institute in the weak row-column list for detecting whether the target line is row in weak row-column list State each weak row in DRAM；

The determination unit is also used to be target line in the testing result of the first detection unit to be row in weak row-column list When, determine that the target line is weak row.

10. device according to claim 9, which is characterized in that described device further include:

Whether second detection unit includes holding time to be less than for for every a line in the DRAM, detecting in the row The unit of preset duration；

The determination unit is also used to be in the row in the testing result of the second detection unit to include holding time to be less than When the unit of the preset duration, the row is determined as weak row；

First storage unit, for the weak row-column list to be generated and saved according to definitive result.

11. according to any device of claim 7 to 10, which is characterized in that described device further include:

Acquiring unit, for determining the target line described according to offset-lists and default initial address in the determination unit In reserved domain in DRAM before corresponding mapping address, obtain the weak row in the DRAM line number and each weak row Size；

Computing unit calculates each weak row in the DRAM for the size according to the line number and each weak row got Corresponding total size；

Prearranged elements, the memory space for default size reserved in the DRAM are described default big as the reserved domain It is small more than or equal to the total size being calculated；

Second storage unit, for the initial address in the reserved domain to be saved as the default initial address.

12. according to any device of claim 7 to 10, which is characterized in that described device further include:

The determination unit is also used to determining the target line in the DRAM according to offset-lists and default initial address Reserved domain in front of corresponding mapping address, according to the sequence of each weak row in the DRAM, determine that each weak row exists Corresponding address offset amount in the reserved domain；

Third storage unit, for saving the offset-lists including each address offset amount.