CN108933132B - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN108933132B CN108933132B CN201710372635.8A CN201710372635A CN108933132B CN 108933132 B CN108933132 B CN 108933132B CN 201710372635 A CN201710372635 A CN 201710372635A CN 108933132 B CN108933132 B CN 108933132B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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Abstract
一种半导体器件及其形成方法，方法包括：提供基底，基底上具有栅极结构、第一保护层和第一介质层，第一保护层位于栅极结构的顶部表面，第一介质层覆盖栅极结构侧壁和第一保护层侧壁且暴露出第一保护层的顶部表面；在部分第一介质层上形成电阻结构，所述电阻结构包括停止层和位于停止层顶部表面的电阻核心层；在电阻结构和第一介质层上和第一保护层表面形成第二介质层；采用第一刻蚀工艺刻蚀第一保护层上的第二介质层、电阻核心层以及电阻核心层上的第二介质层直至暴露出第一保护层和停止层，形成第一栅极通孔和第一开口，第一栅极通孔位于第一保护层上的第二介质层中，第一开口贯穿电阻核心层和第二介质层。所述方法使半导体器件的性能提高。
A semiconductor device and a method for forming the same, the method comprising: providing a substrate with a gate structure, a first protective layer and a first dielectric layer on the substrate, the first protective layer is located on the top surface of the gate structure, and the first dielectric layer covers the gate The sidewalls of the pole structure and the sidewalls of the first protective layer are exposed and the top surface of the first protective layer is exposed; a resistance structure is formed on part of the first dielectric layer, and the resistance structure includes a stop layer and a resistance core layer on the top surface of the stop layer ; Form a second dielectric layer on the resistance structure and the first dielectric layer and on the surface of the first protective layer; use the first etching process to etch the second dielectric layer, the resistance core layer and the resistance core layer on the first protective layer. The second dielectric layer is until the first protective layer and the stop layer are exposed, forming a first gate through hole and a first opening, the first gate through hole is located in the second dielectric layer on the first protective layer, and the first opening penetrates through Resistor core layer and second dielectric layer. The method improves the performance of the semiconductor device.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for forming the same.
Background
Active and passive devices are typically included in an integrated circuit. The active device includes a MOS transistor and the passive device includes a resistor.
The basic structure of the MOS transistor includes: a semiconductor substrate; the semiconductor device comprises a grid structure positioned on the surface of a semiconductor substrate, a source region positioned in the semiconductor substrate on one side of the grid structure and a drain region positioned in the semiconductor substrate on the other side of the grid structure.
To reduce process costs, resistors are typically formed during the formation of gate vias over the gate structures.
However, the performance of a semiconductor device including a MOS transistor and a resistor is still to be improved.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which are used for improving the performance of the semiconductor device.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, including: providing a substrate, wherein the substrate is provided with a grid structure, a first protective layer and a first dielectric layer, the first protective layer is positioned on the top surface of the grid structure, and the first dielectric layer covers the side wall of the grid structure and the side wall of the first protective layer and exposes the top surface of the first protective layer; forming a resistor structure on a part of the first dielectric layer, wherein the resistor structure comprises a stop layer and a resistor core layer positioned on the top surface of the stop layer; forming a second dielectric layer on the resistor structure, the first dielectric layer and the surface of the first protective layer; and etching the second dielectric layer on the first protective layer, the resistor core layer and the second dielectric layer on the resistor core layer by adopting a first etching process until the first protective layer and the stop layer are exposed to form a first grid through hole and a first opening, wherein the first grid through hole is positioned in the second dielectric layer on the first protective layer, and the first opening penetrates through the resistor core layer and the second dielectric layer.
Optionally, after the first etching process is performed, the first protection layer at the bottom of the first gate through hole and the stop layer at the bottom of the first opening are etched by using a second etching process until the top surface of the gate structure is exposed, a second gate through hole is formed in the first protection layer at the bottom of the first gate through hole, and a second opening is formed in the stop layer at the bottom of the first opening.
Optionally, the material of the stop layer is the same as the material of the first protective layer.
Optionally, the material of the stop layer and the material of the first protection layer are silicon nitride, silicon carbide, silicon oxynitride, or titanium oxide.
Optionally, the resistor structure further includes a second protective layer, the second protective layer is located on the top surface of the resistor core layer, and the second dielectric layer is also located on the second protective layer; the first etching process further etches a second protective layer, and the first opening further penetrates through the second protective layer.
Optionally, the etching rate of the first etching process to the second protection layer is greater than the etching rate to the stop layer.
Optionally, the material of the second protective layer includes silicon oxide.
Optionally, the thickness of the second protective layer is 10 angstroms to 200 angstroms.
Optionally, the resistor structure further includes a barrier layer located on a surface of a portion of the first dielectric layer, and the stop layer is located on a top surface of the barrier layer; the method for forming the resistance structure comprises the following steps: forming resistance structure material layers on the surface of the first dielectric layer and the surface of the first protective layer, wherein the resistance structure material layers comprise a blocking material layer positioned on the surface of the first dielectric layer and the surface of the first protective layer, a stopping material layer positioned on the surface of the blocking material layer and a resistance core material layer positioned on the surface of the stopping material layer; and etching and removing the resistance structure material layer on the surface of the first protective layer and part of the surface of the first medium layer to form the resistance structure.
Optionally, in the process of removing the resistive structure material layer on the surface of the first protection layer and part of the surface of the first dielectric layer by etching, the etching rate of the etching process to the barrier material layer is less than the etching rate to the stop material layer, and the etching rate of the etching process to the barrier material layer is less than the etching rate to the first protection layer.
Optionally, the material of the barrier layer includes silicon oxide.
Optionally, the method further includes: forming gate plugs in the first and second gate vias; forming a resistive plug in the first opening and the second opening.
Optionally, the method further includes: before the first etching process is carried out, forming source-drain through holes penetrating through the second dielectric layer and the first dielectric layer, wherein the source-drain through holes are respectively positioned at two sides of the grid structure; forming a flat layer filled with the source-drain through holes; after a flat layer is formed, the first etching process is carried out; removing the flat layer after the first etching process is carried out; and after the flat layer is removed, carrying out the second etching process.
Optionally, the substrate on both sides of the gate structure has a source-drain doped region therein; the first dielectric layer is also positioned on the source-drain doped region; the source drain through hole is positioned on the source drain doping region; the method for forming the semiconductor device further comprises the following steps: before the resistor structure is formed, a bottom protection layer is formed, the bottom protection layer is located on the surface of the source-drain doped region, and the first dielectric layer covers the bottom protection layer on the surface of the source-drain doped region; before the flat layer is formed, the source drain through hole exposes the bottom protective layer; the second etching process also etches the bottom protection layer until the surface of the source-drain doped region is exposed.
Optionally, the bottom protective layer is made of silicon nitride, silicon carbide, silicon oxynitride or titanium oxide.
Optionally, the material of the resistance core layer is titanium nitride, thallium nitride, or aluminum nitride.
The present invention also provides a semiconductor device comprising: a substrate; a gate structure on the substrate; the first protective layer is positioned on the top surface of the grid structure; the first dielectric layer covers the side wall of the grid structure and the side wall of the first protective layer; a resistive structure located on a portion of the first dielectric layer, the resistive structure including a stop layer and a resistive core layer located on a top surface of the stop layer; the second dielectric layer is positioned on the resistance structure, the first dielectric layer and the surface of the first protective layer; a first grid electrode through hole penetrating through the second dielectric layer on the first protective layer, wherein the first grid electrode through hole exposes out of the surface of the first protective layer; and a first opening penetrating through the resistive core layer and the second dielectric layer on the resistive core layer, wherein the first opening exposes the surface of the stop layer.
Optionally, the resistance core layer is made of titanium nitride, thallium nitride or aluminum nitride; the stop layer is made of silicon nitride, silicon carbide, silicon oxynitride or titanium oxide.
Optionally, the resistor structure further includes: the second protective layer is positioned on the top surface of the resistor core layer, and the second dielectric layer is also positioned on the second protective layer; the first opening also penetrates through the second protective layer.
Optionally, the material of the second protective layer includes silicon oxide.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the method for forming the semiconductor device, provided by the technical scheme of the invention, the resistance core layer and the second dielectric layer on the resistance core layer are etched in the process of etching the second dielectric layer on the first protective layer by adopting the first etching process, so that the first opening penetrating through the resistance core layer and the second dielectric layer is formed in the process of forming the first grid through hole in the second dielectric layer on the first protective layer, and the process is simplified. The first etching process can be stopped on the stop layer, so that the resistance core layer and the second dielectric layer on the resistance core layer are etched in different regions in a consistent manner, and the depths of the first openings in different regions are consistent. The first etching process can also be stopped on the surface of the first protection layer, so that the first protection layer can protect the top surface of the gate structure in the process of the first etching process, and the gate structure is prevented from being etched and lost by the first etching process. Thereby improving the performance of the semiconductor device.
Drawings
Fig. 1 to 3 are schematic structural views of a semiconductor device formation process;
fig. 4 to 11 are schematic structural diagrams illustrating a semiconductor device forming process according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of semiconductor devices formed by the prior art is poor.
Fig. 1 to 3 are schematic structural views of a semiconductor device formation process.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 has a gate structure 110, a first protection layer 120 located on a top surface of the gate structure 110, and a first dielectric layer 130, the first dielectric layer 130 covers sidewalls of the gate structure 110 and sidewalls of the first protection layer 120 and exposes a top surface of the first protection layer 120; forming a resistor structure 140 on a portion of the first dielectric layer 130, wherein the resistor structure 140 includes a resistor core layer 141 and a top barrier layer 142 on a top surface of the resistor core layer 141; a second dielectric layer 150 is formed on the first protective layer 120, the resistive structure 140, and the first dielectric layer 130.
Referring to fig. 2, a first etching process is used to etch the second dielectric layer 150 on the first protective layer 120 until the first protective layer 120 is exposed, a first gate through hole 161 is formed in the second dielectric layer 150 on the first protective layer 120, and in the process of etching the second dielectric layer 150 on the first protective layer 120, the second dielectric layer 150 on the resistor structure 140 is etched until the surface of the top barrier layer 142 is exposed, and a first opening 162 penetrating through the second dielectric layer 150 on the resistor structure 140 is formed.
Referring to fig. 3, the resistive structure 140 at the bottom of the first opening 162 is etched by a second etching process, a second opening 163 penetrating the resistive structure 140 is formed at the bottom of the first opening 162, the first protective layer 120 at the bottom of the first gate via 161 is etched during the etching of the resistive structure 140, and a second gate via 164 penetrating the first protective layer 120 is formed at the bottom of the first gate via 161.
A resistive plug is formed in first opening 162 and second opening 163 and a gate plug is formed in first gate via 161 and second gate via 164.
However, the performance of the semiconductor device formed by the method is poor, and researches show that the reason is that:
in the process of etching the second dielectric layer 150 on the first protective layer 120, the second dielectric layer 150 on the resistive structure 140 is etched, and in the process of etching the resistive structure 140, the first protective layer 120 is etched, so that the process is simplified. Etching the second dielectric layer 150 on the resistive structure 140 and stopping on the surface of the top barrier layer 142, the operations including: the depth of the first opening 162 is made more uniform in different regions. For convenience of description, the first opening 162 and the second opening 163 are collectively referred to as an opening structure. Since the thickness of the second dielectric layer 150 is much greater than that of the resistive structure 140, the depth difference of the first opening 162 in different regions has a large effect on the depth difference of the opening structure in different regions. Therefore, the depth of the opening structure in different regions is less different.
The opening structure penetrates the resistive structure 140, and thus the opening structure penetrates the resistive core layer 141. The function of the open structure through the resistive core layer 141 includes: the depth difference of the opening structure has small influence on the difference of the contact areas of the resistive plug and the resistive core layer 141; the contact area of the resistive plug and the resistive core layer 141 is related to the thickness of the resistive core layer 141; since the thickness of the resistive core layer 141 can be more uniform in different regions, the contact areas of the resistive plug and the resistive core layer 141 can be more uniform in different regions.
The first protective layer 120 and the top barrier layer 142 are similar in material. The second etching process has a larger etching selectivity for the first protection layer 120 relative to the top barrier layer 142, and thus the first protection layer 120 is easily lost during the etching of the resistive structure 140. And the thickness of the resistive core layer 141 is relatively thick, the resistive core layer 141 occupies a relatively large proportion of the total thickness of the resistive structure 140, so that the total thickness of the resistive structure 140 is greater than the thickness of the first protection layer 120. Which in turn results in: during the etching of the resistive core layer 141, the first gate via 161 exposes the top surface of the gate structure 110. Since the gate structure 110 is in an etching environment for etching the resistive core layer 141, after the resistive core layer 141 is etched through, a large loss is generated to the gate structure 110, resulting in poor performance of the semiconductor device.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, the resistive structure including a stop layer and a resistive core layer on a top surface of the stop layer; and etching the second dielectric layer on the first protective layer, the resistor core layer and the second dielectric layer on the resistor core layer by adopting a first etching process until the first protective layer and the stop layer are exposed to form a first grid through hole and a first opening, wherein the first grid through hole is positioned in the second dielectric layer on the first protective layer, and the first opening penetrates through the resistor core layer and the second dielectric layer. The method avoids the etching loss of the grid structure in the process of etching the resistance core layer, thereby improving the performance of the semiconductor device.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 11 are schematic structural diagrams illustrating a semiconductor device forming process according to an embodiment of the present invention.
Referring to fig. 4, a substrate 200 is provided, the substrate 200 has a gate structure 230, a first passivation layer 240 and a first dielectric layer 220, the first passivation layer 240 is located on the top surface of the gate structure 230, and the first dielectric layer 220 covers the sidewalls of the gate structure 230 and the sidewalls of the first passivation layer 240 and exposes the top surface of the first passivation layer 240.
In this embodiment, the semiconductor device is a finfet as an example, and accordingly, the substrate 200 includes a semiconductor substrate 201 and a fin 202 on the semiconductor substrate 201.
The semiconductor substrate 201 can be monocrystalline silicon, polycrystalline silicon or amorphous silicon; the semiconductor substrate 201 may be a semiconductor material such as silicon, germanium, silicon germanium, or gallium arsenide. In this embodiment, the material of the semiconductor substrate 201 is silicon.
In other embodiments, the semiconductor device is a planar MOS transistor and, correspondingly, the base is a planar semiconductor substrate.
In this embodiment, the semiconductor substrate 201 further has an isolation structure (not shown) thereon for isolating the adjacent fins 202. The material of the isolation structure comprises silicon oxide.
The first dielectric layer 220 is also located on the isolation structure.
The gate structure 230 includes a gate dielectric layer on the substrate 200 and a gate electrode layer on the gate dielectric layer.
In this embodiment, the gate structure 230 spans the fin 202, covering a portion of the sidewall surface and a portion of the top surface of the fin 202. The gate dielectric layer crosses over the fin 202 and is located on a portion of the surface of the isolation structure, a portion of the sidewall surface and a portion of the top surface of the fin 202.
The gate electrode layer is made of metal, such as copper or tungsten. The gate dielectric layer is made of a high-K (K is more than 3.9) dielectric material.
Specifically, a substrate 200 is provided; forming a dummy gate structure (not shown) on the substrate 200; forming source and drain doped regions (not shown) in the substrate 200 at two sides of the dummy gate structure; after forming the source-drain doped region, forming a first dielectric layer 220 covering the sidewall of the dummy gate structure on the substrate 200; after the first dielectric layer 220 is formed, the dummy gate structure is removed, and a gate opening (not shown) is formed in the first dielectric layer 220; forming a gate structure 230 in the gate opening, wherein a top surface of the gate structure 230 is lower than a top surface of the first dielectric layer 220; a first protective layer 240 is formed in the gate opening on the top surface of the gate structure 230.
The material of the first protection layer 240 is silicon nitride, silicon carbide, silicon oxynitride or titanium oxide.
The first dielectric layer 220 is also located on the source-drain doped region.
The dummy gate structure crosses the fin 202, covering a portion of the sidewall surface of the top surface of the fin 202. The dummy gate structure includes a dummy gate dielectric layer crossing the fin portion 202 and a dummy gate electrode layer on a surface of the dummy gate dielectric layer.
The material of the dummy gate electrode layer is polysilicon. In this embodiment, the dummy gate dielectric layer is made of silicon oxide.
In other embodiments, the dummy gate electrode layer is removed to form a gate opening, and then the dummy gate dielectric layer forms the gate dielectric layer after the gate opening is formed. In this case, the material of the dummy gate dielectric layer is a high-K dielectric material.
After the gate structure 230 is formed, the source and drain doped regions are respectively located in the substrate 200 at two sides of the gate structure 230, and specifically, the source and drain doped regions are respectively located in the fin portions 202 at two sides of the gate structure 230.
In this embodiment, the method further includes: in the process of forming the first dielectric layer 220, a bottom protective layer 210 is formed, the bottom protective layer 210 is located on the surface of the source-drain doped region, and the first dielectric layer 220 covers the bottom protective layer 210 on the surface of the source-drain doped region.
In this embodiment, the bottom passivation layer 210 is located on the surface of the source/drain doped region, the bottom passivation layer 210 is also located on the sidewall of the gate structure 230 and the sidewall of the first passivation layer 240, and the bottom passivation layer 210 exposes the top surface of the first passivation layer 240. Correspondingly, the first dielectric layer 220 covers the bottom protection layer 210 on the surface of the source-drain doped region, the first dielectric layer 220 also covers the sidewall of the bottom protection layer 210 on the sidewall of the gate structure 230, and the first dielectric layer 220 exposes the top surface of the bottom protection layer 210 on the sidewall of the gate structure 230.
The bottom passivation layer 210 is further disposed on the isolation structure, and correspondingly, the first dielectric layer 220 further covers the bottom passivation layer 210 on the isolation structure.
The material of the bottom protective layer 210 includes silicon nitride, silicon carbide, silicon oxynitride, or titanium oxide.
Specifically, the steps of forming the first dielectric layer 220 and the bottom protective layer 210 include: forming a bottom protective material layer on the dummy gate structure and the substrate 200, the bottom protective material layer also being on the isolation structure; forming a first dielectric material layer on the surface of the bottom layer protective material layer; and flattening the first dielectric material layer and the bottom protective material layer until the top surface of the dummy gate structure is exposed, so that the bottom protective material layer forms a bottom protective layer 210, and the first dielectric material layer forms a first dielectric layer 220.
The process for forming the first dielectric material layer is a deposition process, such as a fluid chemical vapor deposition process.
In other embodiments, no underlying protective layer is formed.
Referring to fig. 5, a resistive structure 250 is formed on a portion of the first dielectric layer 220, the resistive structure 250 including a stop layer 252 and a resistive core layer 253 on a top surface of the stop layer 252; a second dielectric layer 260 is formed on the resistive structure 250 and the first dielectric layer 220, and on the surface of the first protective layer 240.
The functions of the stop layer 252 include: the subsequent process of etching the resistive core layer 253 and the second dielectric layer 260 on the resistive core layer 253 can be stopped on the stop layer 252, so that the subsequent first etching process etches the resistive core layer 253 and the second dielectric layer 260 on the resistive core layer 253 in different regions more consistently, and the depths of the first openings in different regions are more consistently.
The choice of the material of the stop layer 252 and the material of the first protective layer 240 is such that: the etching rate of the first protection layer 240 by the subsequent first etching process is smaller than that of the second dielectric layer 260, and the etching rate of the first etching process to the stop layer 252 is smaller than that to the resistive core layer 253.
In this embodiment, the material of the stop layer 252 is the same as the material of the first protection layer 240. In other embodiments, the material of the stop layer and the material of the first protective layer are different.
The stop layer 252 is made of silicon nitride, silicon carbide, silicon oxynitride, or titanium oxide.
The method of forming the resistive structure 250 includes: forming resistance structure material layers on the surfaces of the first dielectric layer 220 and the first protective layer 240, wherein the resistance structure material layers comprise a stop material layer located on the first dielectric layer 220 and the first protective layer 240 and a resistance core material layer located on the surface of the stop material layer; the resistive structure material layer on the surface of the first passivation layer 240 and on the surface of a portion of the first dielectric layer 220 is removed by etching, so as to form a resistive structure 250.
The resistive core layer 253 corresponds to the resistive core material layer.
The stop layer 252 corresponds to the stop material layer.
In this embodiment, the resistive structure material layer is also located on the top surface of the bottom passivation layer 210. During the etching process to remove the resistive structure material layer on the surface of the first protection layer 240 and part of the surface of the first dielectric layer 220, the resistive structure material layer on the top surface of the bottom protection layer 210 is also removed.
The process for forming the resistance structure material layer is a deposition process, such as a plasma chemical vapor deposition process, a low-pressure chemical vapor deposition process, a sub-atmospheric pressure chemical vapor deposition process or an atomic layer deposition process.
In this embodiment, the resistor structure 250 further includes a second protective layer 254, the second protective layer 254 is located on the top surface of the resistor core layer 253, and the second dielectric layer 260 is further located on the second protective layer 254. Correspondingly, the resistance structure material layer further comprises a second protective material layer, and the second protective material layer is located on the surface of the resistance core material layer.
The second protective layer 254 corresponds to the second protective material layer.
The material selection of the second protective layer 254 is such that: in the subsequent process of etching the second dielectric layer 260 on the first protective layer 240, the resistive core layer 253, the second protective layer 254, and the second dielectric layer 260 on the second protective layer 254 by using the first etching process, the etching rate of the first etching process to the second protective layer 254 is greater than the etching rate to the stop layer 252.
The material of the second protective layer 254 includes silicon oxide.
The functions of the second protective layer 254 include: after forming resistive structure 250, and before forming second dielectric layer 260, second protective layer 254 serves to protect the top surface of resistive core layer 253.
The thickness of the second protective layer 254 is less than the thickness of the subsequent barrier layer.
Specifically, in one embodiment, the second protective layer 254 has a thickness of 10 to 200 angstroms. The thickness of the second protective layer 254 is selected in the sense that the range includes: if the thickness of the second protection layer 254 is greater than 200 angstroms, process waste may result; if the thickness of the second protective layer 254 is less than 10 angstroms, it is difficult to control the process, and the protective effect of the second protective layer 254 on the resistive core layer 253 is weak.
In other embodiments, the thickness of the second protective layer is greater than or equal to the thickness of the subsequent barrier layer.
In other embodiments, the second protective layer may not be formed.
In this embodiment, the resistor structure 250 further includes a barrier layer 251 located on a portion of the surface of the first dielectric layer 220, and the stop layer 252 is located on the top surface of the barrier layer 251. Correspondingly, the resistance structure material layer further includes a barrier material layer located on the surface of the first dielectric layer 220 and the surface of the first protection layer 240, and the stop material layer is located on the surface of the barrier material layer.
The barrier layer 251 corresponds to the barrier material layer.
The material of the barrier layer 251 includes silicon oxide.
In the process of removing the resistive structure material layer on the surface of the first protection layer 240 and part of the surface of the first dielectric layer 220 by etching, the etching rate of the etching process to the barrier material layer is less than the etching rate to the stop material layer, and the etching rate of the etching process to the barrier material layer is less than the etching rate to the first protection layer 240. Thus, in the process of forming the resistor structure 250, the first protection layer 240 can be protected, and etching damage to the first protection layer 240 is reduced, and secondly, the top surface of the bottom protection layer 210 can be protected, and etching damage to the top surface of the bottom protection layer 210 is reduced.
In other embodiments, the barrier layer 251 may not be formed.
The material of the second dielectric layer 260 includes silicon oxide.
In this embodiment, the second dielectric layer 260 is further located on the top surface of the bottom passivation layer 210.
The second dielectric layer 260 is formed by a deposition process, such as a plasma enhanced chemical vapor deposition process or a high density plasma chemical vapor deposition process.
In this embodiment, the density of the second dielectric layer 260 is greater than the density of the first dielectric layer 220.
Next, a first etching process is used to etch the second dielectric layer 260 on the first protective layer 240, the resistive core layer 253, and the second dielectric layer 260 on the resistive core layer 253 until the first protective layer 240 and the stop layer 252 are exposed, so as to form a first gate via and a first opening, the first gate via is located in the second dielectric layer 260 on the first protective layer 240, and the first opening penetrates through the resistive core layer 253 and the second dielectric layer 260.
In this embodiment, the method further includes: before the first etching process is performed, forming source and drain through holes penetrating through the second dielectric layer 260 and the first dielectric layer 220, where the source and drain through holes are located at two sides of the gate structure 230, respectively; forming a flat layer filled with the source-drain through holes; after a flat layer is formed, the first etching process is carried out; and removing the flat layer after the first etching process is carried out.
Referring to fig. 6, source-drain through holes 270 penetrating through the second dielectric layer 260 and the first dielectric layer 220 are formed, and the source-drain through holes 270 are respectively located at two sides of the gate structure 230.
The source drain via 270 is located on the source drain doped region.
In this embodiment, before forming the planarization layer, the source/drain via 270 exposes the bottom protection layer 210.
Referring to fig. 7, a planarization layer 280 filling the source and drain vias 270 (refer to fig. 6) is formed.
The material of the planarization layer 280 is a photoresist material, a bottom anti-reflection layer material or an organic polymer.
The process of forming the planarization layer 280 includes a spin-on process.
The planarization layer 280 provides a relatively flat surface for the subsequent formation of the first gate via in the second dielectric layer 260.
In this embodiment, the planarization layer 280 is further disposed on the second dielectric layer 260. In other embodiments, the planarization layer only fills the source drain vias.
In this embodiment, the planarization layer 280 is further disposed on the bottom passivation layer 210.
In this embodiment, a patterned mask layer 290 is further formed on the planarization layer 280 and the second dielectric layer 260, and the patterned mask layer 290 is used to define the positions of the first gate via and the first opening.
The material of the patterned masking layer 290 includes photoresist.
Referring to fig. 8, after the planarization layer 280 is formed, the second dielectric layer 260 on the first protective layer 240, the resistive core layer 253, and the second dielectric layer 260 on the resistive core layer 253 are etched by using a first etching process until the first protective layer 240 and the stop layer 252 are exposed, so as to form a first gate via 300 and a first opening 301, wherein the first gate via 300 is located in the second dielectric layer 260 on the first protective layer 240, and the first opening 301 penetrates through the resistive core layer 253 and the second dielectric layer 260.
Specifically, the patterned mask layer 290 is used as a mask to etch the second dielectric layer 260 on the first protective layer 240, and the resistive core layer 253 and the second dielectric layer 260 on the resistive core layer 253.
In this embodiment, the first etching process further etches the planarization layer 280 on the second dielectric layer 260, the first gate via 300 penetrates through the second dielectric layer 260 and the planarization layer 280 on the first protection layer 240, and the first opening 301 penetrates through the resistive core layer 253, the second dielectric layer 260 and the planarization layer 280.
In this embodiment, in the process of etching the second dielectric layer 260 on the first protective layer 240 by using the first etching process, the resistive core layer 253 and the second dielectric layer 260 on the resistive core layer 253 are etched, so that the first opening 301 is formed in the process of forming the first gate through hole 300, thereby simplifying the process.
The first etching process etches the first protection layer 240 at a rate less than that of the second dielectric layer 260, and the first etching process etches the stop layer 252 at a rate less than that of the resistive core layer 253.
In one embodiment, the first etching process is a dry etching process, and the parameters include: the gas used comprises C4F6、CHF3And O2，C4F6The flow rate of (1) is 10sccm to 200sccm, CHF3The flow rate of (1) is 30-500 sccm, O2The flow rate of the gas source is 100-2000 sccm, the source radio frequency power is 50-500W, the bias voltage is 30-300W, and the chamber pressure is 1-300 mtorr.
In this embodiment, the first etching process can be stopped on the stop layer 252, so that the etching degree of the resistive core layer 253 and the second dielectric layer 260 on the resistive core layer 253 are relatively consistent in different regions, and the depth of the first opening 301 is relatively consistent in different regions.
In this embodiment, the first etching process further etches the second protection layer 254, so that the first opening 301 further penetrates through the second protection layer 254.
The first etch process etches the second protective layer 254 at a greater rate than the stop layer 252.
The reason why the first gate through hole 300 and the source-drain through hole 270 are formed respectively is that: as the feature size of semiconductor devices continues to decrease, the distance between the center of the source and drain doped regions and the center of the gate structure 230 continues to decrease. Due to the limitation of the photolithography limit, it is difficult to simultaneously pattern the first dielectric layer 220 and the second dielectric layer 260 on the source-drain doped region and the second dielectric layer 260 on the first protective layer 240, and therefore, the first gate via 300 and the source-drain via 270 need to be formed respectively.
Since the first etching process can also be stopped on the surface of the first protection layer 240, in the process of performing the first etching process, the first protection layer 240 can protect the top surface of the gate structure 230, and the first etching process is prevented from generating etching loss on the gate structure 230. Thereby improving the performance of the semiconductor device.
Referring to fig. 9, after the first etching process is performed, the planarization layer 280 is removed.
The process of removing the planarization layer 280 is a dry etching process, and the gas adopted in the dry etching process is oxygen-containing gas.
In this embodiment, the oxygen-containing gas comprises O2. In other embodiments, the oxygen-containing gas comprises O2And CO2。
In the process of removing the planarization layer 280, the bottom protection layer 210 can protect the surface of the source/drain doped region, and prevent the surface of the source/drain doped region from being oxidized.
It should be noted that the patterned mask layer 290 is consumed in the first etching process; alternatively, the patterned mask layer 290 is completely removed during the first etching process and the removal of the planarization layer 280.
Referring to fig. 10, after the first etching process is performed, the first protection layer 240 at the bottom of the first gate via 300 and the stop layer 252 at the bottom of the first opening 301 are etched by the second etching process until the top surface of the gate structure 230 is exposed, a second gate via 302 is formed in the first protection layer 240 at the bottom of the first gate via 300, and a second opening 303 is formed in the stop layer 252 at the bottom of the first opening 301.
In this embodiment, the second opening 303 is formed during the formation of the second gate via hole 302, thereby simplifying the process.
In this embodiment, after the planarization layer 280 is removed, the second etching process is performed.
In this embodiment, the barrier layer 251 is further etched by the second etching process, so that the second opening 303 further penetrates through the barrier layer 251. In other embodiments, the second opening does not extend through the barrier layer.
In this embodiment, the second etching process further etches the bottom protection layer 210 until the surface of the source/drain doped region is exposed, thereby simplifying the process.
Next, referring to fig. 11, after a second etching process is performed, forming a source/drain plug 310 in the source/drain via 270 (refer to fig. 10); forming a gate plug 320 in the first gate via 300 (refer to fig. 10) and the second gate via 302 (refer to fig. 10); a resistive plug 330 is formed in the first opening 301 (refer to fig. 10) and the second opening 303 (refer to fig. 10).
The source drain plug 310 is electrically connected to the source drain doped region. The gate plug 320 is electrically connected to the gate structure 230. The resistive plugs 330 are electrically connected to the resistive core layer 253.
The material of the source drain plug 310, the gate plug 320 and the resistive plug 330 is metal, such as copper or tungsten.
For convenience of description, the first opening 301 and the second opening 303 are collectively referred to as an opening structure. The function of the open structure through the resistive core layer 253 includes: the depth difference of the open structure has less influence on the difference of the contact areas of the resistive plugs 330 and the resistive core layer 253; the contact area of resistive plugs 330 and resistive core layer 253 is related to the thickness of resistive core layer 253; since the thickness of the resistive core layer 253 can be more uniform in different regions, the contact areas of the resistive plugs 330 and the resistive core layer 253 can be more uniform in different regions.
Accordingly, the present embodiment further provides a semiconductor device formed by the above method, with reference to fig. 9, including: a substrate 200; a gate structure 230 on the substrate 200; a first protection layer 240 on the top surface of the gate structure 230; a first dielectric layer 220 covering sidewalls of the gate structure 230 and sidewalls of the first protection layer 240; a resistive structure 250 on a portion of first dielectric layer 220, resistive structure 250 comprising a stop layer 252 and a resistive core layer 253 on a top surface of stop layer 252; a second dielectric layer 260 on the resistive structure 250 and the first dielectric layer 220 and on the surface of the first protective layer 240; a first gate via 300 penetrating through the second dielectric layer 260 on the first protection layer 240, wherein the first gate via 300 exposes the surface of the first protection layer 240; a first opening 301 extends through the resistive core layer 253 and the second dielectric layer 260 on the resistive core layer 253, the first opening 301 exposing the surface of the stop layer 252.
The resistive core layer 253 is made of titanium nitride, thallium nitride or aluminum nitride.
The stop layer 252 is made of silicon nitride, silicon carbide, silicon oxynitride, or titanium oxide.
The resistive structure 250 further includes: a second protective layer 254, the second protective layer 254 being located on a top surface of the resistive core layer 253, the second dielectric layer 260 also being located on the second protective layer 254; the first opening 301 also penetrates the second protective layer 254.
The material of the second protective layer 254 includes silicon oxide.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (14)
1. A method of forming a semiconductor device, comprising:
providing a substrate, wherein the substrate is provided with a grid structure, a first protective layer and a first dielectric layer, the first protective layer is positioned on the top surface of the grid structure, and the first dielectric layer covers the side wall of the grid structure and the side wall of the first protective layer and exposes the top surface of the first protective layer;
forming a resistor structure on a part of the first dielectric layer, wherein the resistor structure comprises a stop layer and a resistor core layer positioned on the top surface of the stop layer; the resistor structure further comprises a second protective layer, the second protective layer is located on the top surface of the resistor core layer, the material of the second protective layer comprises silicon oxide, and the thickness of the second protective layer is 10-200 angstroms;
forming a second dielectric layer on the resistor structure, the first dielectric layer and the surface of the first protective layer;
etching the second dielectric layer on the first protective layer, the resistor core layer, the second dielectric layer on the resistor core layer and the second protective layer by adopting a first etching process until the first protective layer and the stop layer are exposed to form a first grid through hole and a first opening, wherein the first grid through hole is positioned in the second dielectric layer on the first protective layer, and the first opening penetrates through the resistor core layer, the second protective layer and the second dielectric layer; and the etching rate of the first etching process to the second protective layer is greater than that to the stop layer.
2. The method of claim 1, wherein after the first etching process, the first passivation layer at the bottom of the first gate via and the stop layer at the bottom of the first opening are etched by a second etching process until the top surface of the gate structure is exposed, the second gate via is formed in the first passivation layer at the bottom of the first gate via, and the second opening is formed in the stop layer at the bottom of the first opening.
3. The method for forming a semiconductor device according to claim 1, wherein a material of the stop layer and a material of the first protective layer are the same.
4. The method according to claim 3, wherein a material of the stop layer and a material of the first protective layer are silicon nitride, silicon carbide, silicon oxynitride, or titanium oxide.
5. The method of claim 1, wherein the resistive structure further comprises a barrier layer on a portion of the surface of the first dielectric layer, and the stop layer is on a top surface of the barrier layer; the method for forming the resistance structure comprises the following steps: forming resistance structure material layers on the surface of the first dielectric layer and the surface of the first protective layer, wherein the resistance structure material layers comprise a blocking material layer positioned on the surface of the first dielectric layer and the surface of the first protective layer, a stopping material layer positioned on the surface of the blocking material layer and a resistance core material layer positioned on the surface of the stopping material layer; and etching and removing the resistance structure material layer on the surface of the first protective layer and part of the surface of the first medium layer to form the resistance structure.
6. The method as claimed in claim 5, wherein during the etching process to remove the resistive structure material layer on the surface of the first passivation layer and part of the surface of the first dielectric layer, the etching rate of the barrier material layer by the etching process is less than the etching rate of the stop material layer, and the etching rate of the barrier material layer by the etching process is less than the etching rate of the first passivation layer.
7. The method according to claim 6, wherein a material of the barrier layer comprises silicon oxide.
8. The method for forming a semiconductor device according to claim 2, further comprising: forming gate plugs in the first and second gate vias; forming a resistive plug in the first opening and the second opening.
9. The method for forming a semiconductor device according to claim 2, further comprising: before the first etching process is carried out, forming source-drain through holes penetrating through the second dielectric layer and the first dielectric layer, wherein the source-drain through holes are respectively positioned at two sides of the grid structure; forming a flat layer filled with the source-drain through holes; after a flat layer is formed, the first etching process is carried out; removing the flat layer after the first etching process is carried out; and after the flat layer is removed, carrying out the second etching process.
10. The method for forming the semiconductor device according to claim 9, wherein a source-drain doped region is formed in the substrate on both sides of the gate structure; the first dielectric layer is also positioned on the source-drain doped region; the source drain through hole is positioned on the source drain doping region;
the method for forming the semiconductor device further comprises the following steps: before the resistor structure is formed, a bottom protection layer is formed, the bottom protection layer is located on the surface of the source-drain doped region, and the first dielectric layer covers the bottom protection layer on the surface of the source-drain doped region; before the flat layer is formed, the source drain through hole exposes the bottom protective layer; the second etching process also etches the bottom protection layer until the surface of the source-drain doped region is exposed.
11. The method for forming a semiconductor device according to claim 10, wherein a material of the bottom protective layer is silicon nitride, silicon carbide, silicon oxynitride, or titanium oxide.
12. The method according to claim 1, wherein a material of the resistive core layer is titanium nitride, thallium nitride, or aluminum nitride.
13. A semiconductor device, comprising:
a substrate;
a gate structure on the substrate;
the first protective layer is positioned on the top surface of the grid structure;
the first dielectric layer covers the side wall of the grid structure and the side wall of the first protective layer;
a resistive structure located on a portion of the first dielectric layer, the resistive structure including a stop layer and a resistive core layer located on a top surface of the stop layer; the resistance structure further includes: the second protective layer is positioned on the top surface of the resistor core layer, the material of the second protective layer comprises silicon oxide, and the thickness of the second protective layer is 10-200 angstroms;
the second dielectric layer is positioned on the resistance structure, the first dielectric layer and the surface of the first protective layer;
a first grid electrode through hole penetrating through the second dielectric layer on the first protective layer, wherein the first grid electrode through hole exposes out of the surface of the first protective layer;
and a first opening penetrating through the resistive core layer, the second protective layer on the resistive core layer and the second dielectric layer, wherein the first opening exposes the surface of the stop layer.
14. The semiconductor device according to claim 13, wherein a material of the resistive core layer is titanium nitride, thallium nitride, or aluminum nitride; the stop layer is made of silicon nitride, silicon carbide, silicon oxynitride or titanium oxide.
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| US20130277754A1 (en) * | 2012-04-20 | 2013-10-24 | Chia-Wen Liang | Semiconductor Integrated Structure |
| US9406770B2 (en) * | 2014-07-16 | 2016-08-02 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device having a resistor structure |
| CN106206271A (en) * | 2015-04-29 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| US20170084721A1 (en) * | 2015-09-23 | 2017-03-23 | United Microelectronics Corp. | Method for forming semiconductor device |
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| US20130277754A1 (en) * | 2012-04-20 | 2013-10-24 | Chia-Wen Liang | Semiconductor Integrated Structure |
| US9406770B2 (en) * | 2014-07-16 | 2016-08-02 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device having a resistor structure |
| CN106206271A (en) * | 2015-04-29 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| US20170084721A1 (en) * | 2015-09-23 | 2017-03-23 | United Microelectronics Corp. | Method for forming semiconductor device |
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