CN108923253B - VCSE L chip and manufacturing method - Google Patents
VCSE L chip and manufacturing method Download PDFInfo
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- CN108923253B CN108923253B CN201810731132.XA CN201810731132A CN108923253B CN 108923253 B CN108923253 B CN 108923253B CN 201810731132 A CN201810731132 A CN 201810731132A CN 108923253 B CN108923253 B CN 108923253B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
- H01S5/18361—Structure of the reflectors, e.g. hybrid mirrors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
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Abstract
The invention discloses a VCSE L chip and a manufacturing method thereof, wherein the manufacturing method comprises the steps of providing a substrate, dividing the substrate into a middle area and an edge area surrounding the middle area, growing a structural layer covering the middle area on the middle area, growing an oxide layer, covering the edge area, the side wall of the structural layer and the surface of the side, far away from the substrate, of the oxide layer, growing a first protective layer on the side, far away from the structural layer, of the oxide layer, partially covering the middle area, growing a second protective layer on the side, far away from the substrate, of the oxide layer, partially covering the edge area by the second protective layer, carrying out oxidation treatment on the oxide layer, removing the first protective layer, growing a P-type Bragg reflector layer on the side, far away from the structural layer, removing the second protective layer, and manufacturing an electrode structure.
Description
Technical Field
The invention relates to the technical field of VCSE L chips, in particular to a VCSE L chip and a manufacturing method thereof.
Background
With the continuous development of science and technology, various VCSE L chips have been widely used in daily life, work and industry of people, and bring great convenience to people's life.
Vertical Cavity Surface Emitting lasers (Vertical Cavity Surface Emitting L aser, VCSE L) are different from other light sources such as L ED (L light Emitting Diode) and L D (L laser Diode), have the advantages of small volume, circular output light spot, single longitudinal mode output, small threshold current, low price, easy integration of large-area arrays and the like, and are widely applied to the fields of optical communication, optical interconnection, optical storage and the like.
However, the difficulty of the current process for manufacturing the VCSE L chip is mainly shown in that after the epitaxial layer is subjected to ICP etching (Inductively coupled Plasma etching), oxidation treatment is performed in holes or steps of the ICP etching, so that the precision requirement of each process is high, the uniformity during the ICP etching and oxidation cannot be controlled, the uniformity and the oxidation uniformity of the ICP etching are poor, and the yield of the VCSE L chip is uneven.
Disclosure of Invention
In order to solve the problems, the invention provides the VCSE L chip and the manufacturing method, the manufacturing method is simple, and the process difficulty of the VCSE L chip is reduced.
In order to achieve the purpose, the invention provides the following technical scheme:
a method of fabricating a VCSE L chip, the method comprising:
providing a substrate, wherein the substrate is divided into a middle area and an edge area surrounding the middle area;
growing a structural layer on the middle region, wherein the structural layer completely covers the middle region, the structural layer sequentially comprises an N-type Bragg reflector layer and an MQW multi-quantum well layer in a first direction, the first direction is perpendicular to the substrate, and the substrate points to the P-type Bragg reflector layer;
growing an oxide layer, wherein the oxide layer covers the edge region and the side wall of the structural layer and the surface of one side, which is far away from the substrate;
growing a first protective layer on one side of the oxide layer, which is far away from the structural layer, wherein the first protective layer partially covers the middle area, and growing a second protective layer on one side of the oxide layer, which is far away from the substrate, wherein the second protective layer partially covers the edge area;
carrying out oxidation treatment on the oxide layer;
removing the first protective layer, and growing a P-type Bragg reflector layer on one side of the oxide layer, which is far away from the structural layer, wherein the P-type Bragg reflector layer completely covers the middle area;
and removing the second protective layer and manufacturing an electrode structure.
Preferably, in the above manufacturing method, the substrate is a GaAs substrate.
Preferably, in the above manufacturing method, growing a structural layer on the intermediate region, the structural layer completely covering the intermediate region, and the structural layer sequentially including an N-type bragg mirror layer and an MQW multiple quantum well layer in a first direction includes:
growing a third protective layer on the substrate;
carrying out graphical photoetching treatment on the third protective layer to expose the middle area of the substrate;
growing the structural layer on the intermediate region, the structural layer fully covering the intermediate region;
removing the third protective layer;
the structural layer sequentially comprises an N-type Bragg reflector layer and an MQW multi-quantum well layer in the first direction.
Preferably, in the above manufacturing method, growing a structural layer on the intermediate region, the structural layer completely covering the intermediate region, and the structural layer sequentially including an N-type bragg mirror layer and an MQW multiple quantum well layer in a first direction includes:
growing the structural layer on the substrate, wherein the structural layer completely covers the substrate;
etching the structural layer to expose the edge area of the substrate;
the structural layer sequentially comprises an N-type Bragg reflector layer and an MQW multi-quantum well layer in the first direction.
Preferably, in the above manufacturing method, the manufacturing of the electrode structure includes:
growing a P-type electrode on one side of the P-type Bragg reflector layer, which is far away from the oxide layer;
and growing an N-type electrode on one side of the oxide layer, which is far away from the substrate.
Preferably, in the above manufacturing method, the P-type electrode and the N-type electrode are made of the same material.
Preferably, in the above manufacturing method, a thickness of the oxide layer in the first direction is in a range of 8nm to 12nm, inclusive.
The invention also provides a VCSE L chip manufactured by the manufacturing method of any one of the above methods, wherein the VCSE L chip comprises:
a substrate divided into a middle region and an edge region surrounding the middle region;
the structural layer is arranged on the middle area, the structural layer completely covers the middle area, the structural layer sequentially comprises an N-type Bragg reflector layer and an MQW multi-quantum well layer in a first direction, the first direction is perpendicular to the substrate, and the substrate points to the P-type Bragg reflector layer;
an oxide layer covering the edge region and covering the side wall of the structural layer and the surface of the side away from the substrate;
the P-type Bragg reflector layer is arranged on one side, away from the structural layer, of the oxide layer, and the P-type Bragg reflector layer completely covers the middle area;
an electrode structure.
Preferably, in the above VCSE L chip, the electrode structure includes:
the P-type electrode is arranged on one side, away from the oxide layer, of the P-type Bragg reflector layer;
and the N-type electrode is arranged on one side of the oxide layer, which is far away from the substrate.
Preferably, in the VCSE L chip, the oxide layer covered by the P-type bragg mirror layer is partially an oxide layer subjected to oxidation treatment and partially an oxide layer not subjected to oxidation treatment;
the oxide layers covered by the N-type electrode are all oxide layers which are not subjected to oxidation treatment;
the exposed oxide layers are all the oxide layers after oxidation treatment.
According to the description, the manufacturing method of the VCSE L chip comprises the steps of providing a substrate, dividing the substrate into a middle area and an edge area surrounding the middle area, growing a structural layer on the middle area, wherein the structural layer completely covers the middle area, the structural layer sequentially comprises an N-type Bragg mirror layer and an MQW multi-quantum well layer in the first direction, the first direction is perpendicular to the substrate, the substrate points to the P-type Bragg mirror layer, an oxide layer is grown, the oxide layer covers the edge area, the side wall of the structural layer and the surface of the side, away from the substrate, of the structural layer, a first protective layer is grown on the side, away from the structural layer, of the oxide layer, partially covers the middle area, a second protective layer is grown on the side, away from the substrate, partially covers the edge area, oxidation treatment is conducted on the oxide layer, the first protective layer is removed, a P-type Bragg mirror layer is grown on the side, away from the oxide layer, the P-type Bragg mirror layer completely covers the middle area, and an electrode structure is removed.
The manufacturing method reduces the process difficulty of the VCSE L chip, enlarges the process window, carries out oxidation treatment on the exposed oxide layer in the oxidation treatment stage, then grows an additional epitaxial layer structure, is easy to control the oxidation uniformity, and greatly reduces ICP etching on the epitaxial layer.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a VCSE L chip according to an embodiment of the present invention;
fig. 2-13 are schematic views of process structures corresponding to the schematic flow diagram shown in fig. 1.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 1, fig. 1 is a schematic flow chart of a method for manufacturing a VCSE L chip according to an embodiment of the present invention, where the method includes:
s101: as shown in fig. 2, a substrate 11 is provided, and the substrate 11 is divided into a middle region 111 and an edge region 112 surrounding the middle region 111.
In particular, the substrate 11 includes, but is not limited to, a GaAs substrate for growing an epitaxial layer structure on its surface.
It should be noted that the division of the middle region 111 and the edge region 112 of the substrate 11 may be performed according to actual situations, and is not limited in the embodiments of the present invention, and is only described in an exemplary manner.
S102: as shown in fig. 6, a structural layer 13 is grown on the intermediate region 111, the structural layer 13 completely covers the intermediate region 111, and the structural layer 13 sequentially includes an N-type bragg mirror layer and an MQW multi-quantum well layer in a first direction, where the first direction is perpendicular to the substrate 11 and is directed to the P-type bragg mirror layer from the substrate 11.
Specifically, the growing of the structural layer 13 includes, but is not limited to, two modes disclosed in the present invention, which are as follows:
the first growth mode:
A1: as shown in fig. 3, a third protective layer 12 is grown on the substrate 11.
In particular, the third protectionLayer 12 includes, but is not limited to, SiO2A layer or SiN layer, etc.
B1: as shown in fig. 4, the third passivation layer 12 is patterned by photolithography to expose the middle region 111 of the substrate 11.
C1: as shown in fig. 5, the structural layer 13 is grown on the middle region 111, and the structural layer 13 completely covers the middle region 111.
Specifically, the structural layer 111 sequentially includes an N-type bragg mirror layer and an MQW multi-quantum well layer in the first direction.
D1: the third protective layer 12 is removed.
Specifically, the third protective layer 12 is removed by a method including, but not limited to, ultrasonic peeling, and after the third protective layer 12 is removed, a process for manufacturing a structural layer 13 on the substrate 11 is implemented, and a structural diagram of the process is shown in fig. 6.
The second growth mode is as follows:
A2: as shown in fig. 7, the structural layer 13 is grown on the substrate 11, and the structural layer 13 completely covers the substrate 11.
Specifically, an N-type bragg mirror layer is grown on the substrate 11, and then an MQW multiple quantum well layer is grown on a side of the N-type bragg mirror layer away from the substrate 11 to form the structural layer 13, wherein the structural layer 13 completely covers the substrate 11.
B2: the structural layer 13 is etched to expose an edge region 112 of the substrate 11.
Specifically, the structural layer 13 is subjected to ICP etching, the etching depth is the same as the thickness of the structural layer 13 in the first direction, and after the etching is completed, the edge region 112 of the substrate 11 is exposed, and the structure diagram is shown in fig. 6.
S103: as shown in fig. 8, an oxide layer 14 is grown, the oxide layer 14 covering the edge region 112 and covering the sidewalls of the structural layer 13 and the surface of the side facing away from the substrate 11.
Specifically, the oxide layer 14 surrounds the surface and the sidewalls of the structural layer 13, and covers the surface of the substrate 11 exposed at the edge region 112.
Optionally, the oxide layer 14 includes, but is not limited to, an AlGaAs oxide layer.
Optionally, the thickness of the oxide layer 14 in the first direction is in a range of 8nm to 12nm, inclusive, for example, the thickness of the oxide layer 14 is 9nm, or 10nm, or 11 nm. The thickness is relatively thin, and the subsequent oxidation treatment effect is excellent.
S104: as shown in fig. 9, a first protective layer 15 is grown on the side of the oxide layer 14 facing away from the structural layer 13, the first protective layer 15 partially covering the middle region 111, and a second protective layer 16 is grown on the side of the oxide layer 14 facing away from the substrate 11, the second protective layer 16 partially covering the edge region 112.
Specifically, the first protective layer 15 and the second protective layer 16 include, but are not limited to, SiO2A layer or SiN layer or the like for preventing the oxidation of the oxide layer 14 covered with the first protective layer 15 and the second protective layer 16.
S105: as shown in fig. 10, the oxidation layer 14 is subjected to oxidation treatment.
Specifically, reference numeral 141 denotes an oxidized layer after the oxidation treatment, and reference numeral 142 denotes an oxidized layer not subjected to the oxidation treatment for passing a current.
S106: as shown in fig. 11, the first protection layer 15 is removed, and a P-type bragg mirror layer 17 is grown on a side of the oxide layer 14 away from the structural layer 13, where the P-type bragg mirror layer 17 completely covers the middle region 111.
S107: and removing the second protective layer and manufacturing an electrode structure.
Specifically, as shown in fig. 12, the P-type bragg mirror layer cannot be deposited on the surface of the GaAs substrate due to lattice mismatch between the GaAs substrate and the epitaxial surface and large deposition defects of the second protective layer (SiO2 layer), and then the second protective layer 16 is removed.
As shown in fig. 13, a P-type electrode 18 is grown on the side of the P-type bragg mirror layer 17 away from the oxide layer 14; an N-type electrode 19 is grown on the side of the oxide layer 14 facing away from the substrate 11.
Optionally, the P-type electrode 18 and the N-type electrode 19 are metal electrodes, and the electrode materials are the same.
According to the manufacturing method, the process difficulty of the VCSE L chip is reduced, the process window is enlarged, an extra epitaxial layer structure is grown after the exposed oxide layer is oxidized in the oxidation treatment stage, the oxidation uniformity is easily controlled, ICP etching on the epitaxial layer is greatly reduced, the vertical structure is changed into the horizontal structure, and the heat dissipation of the VCSE L chip is facilitated.
Based on the above-mentioned manufacturing method of the VCSE L chip, in another embodiment of the present invention, there is further provided a VCSE L chip, as shown in fig. 13, where the VCSE L chip includes:
a substrate 11, the substrate 11 being divided into a middle region and an edge region surrounding the middle region;
a structural layer 13 disposed on the middle region, wherein the structural layer 13 covers the middle region completely, and the structural layer 13 sequentially includes an N-type bragg mirror layer and an MQW multi-quantum well layer in a first direction, the first direction is perpendicular to the substrate 11, and the substrate 11 points to the P-type bragg mirror layer;
an oxide layer 14, wherein the oxide layer 14 covers the edge region and covers the side wall of the structural layer 13 and the surface of the side facing away from the substrate 11;
the P-type Bragg reflector layer 17 is arranged on one side, away from the structural layer 13, of the oxide layer 14, and the P-type Bragg reflector layer 17 completely covers the middle area;
an electrode structure.
The oxide layer 14 covered by the P-type bragg mirror layer 17 is partially an oxide layer 141 subjected to oxidation treatment and partially an oxide layer 142 not subjected to oxidation treatment; the oxide layers 14 covered by the N-type electrodes 19 are all oxide layers 142 which are not subjected to oxidation treatment; the exposed oxide layer 14 is the oxide layer 141 after the oxidation treatment.
Further, the electrode structure includes:
the P-type electrode 18 is arranged on one side, away from the oxide layer 14, of the P-type Bragg reflector layer 17;
an N-type electrode 19 arranged on a side of the oxide layer 14 facing away from the substrate 11.
The yield of the VCSE L chip manufactured by the manufacturing method of the VCSE L chip is high, and the oxidation uniformity of the epitaxial layer of the VCSE L chip is good.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A method for manufacturing a VCSE L chip, the method comprising:
providing a substrate, wherein the substrate is divided into a middle area and an edge area surrounding the middle area;
growing a structural layer on the middle region, wherein the structural layer completely covers the middle region, the structural layer sequentially comprises an N-type Bragg reflector layer and an MQW multi-quantum well layer in a first direction, the first direction is perpendicular to the substrate, and the substrate points to the P-type Bragg reflector layer;
growing an oxide layer, wherein the oxide layer covers the edge region and the side wall of the structural layer and the surface of one side, which is far away from the substrate;
growing a first protective layer on one side of the oxide layer, which is far away from the structural layer, wherein the first protective layer partially covers the middle area, and growing a second protective layer on one side of the oxide layer, which is far away from the substrate, wherein the second protective layer partially covers the edge area;
carrying out oxidation treatment on the oxide layer;
removing the first protective layer, and growing a P-type Bragg reflector layer on one side of the oxide layer, which is far away from the structural layer, wherein the P-type Bragg reflector layer completely covers the middle area;
removing the second protective layer and manufacturing an electrode structure;
wherein, the electrode structure of said preparation includes:
growing a P-type electrode on one side of the P-type Bragg reflector layer, which is far away from the oxide layer;
and growing an N-type electrode on one side of the oxide layer, which is far away from the substrate.
2. The method of manufacturing according to claim 1, wherein the substrate is a GaAs substrate.
3. The method of claim 1, wherein growing a structural layer on the intermediate region, the structural layer completely covering the intermediate region, the structural layer sequentially comprising an N-type bragg mirror layer and an MQW multi-quantum well layer in a first direction comprises:
growing a third protective layer on the substrate;
carrying out graphical photoetching treatment on the third protective layer to expose the middle area of the substrate;
growing the structural layer on the intermediate region, the structural layer fully covering the intermediate region;
removing the third protective layer;
the structural layer sequentially comprises an N-type Bragg reflector layer and an MQW multi-quantum well layer in the first direction.
4. The method of claim 1, wherein growing a structural layer on the intermediate region, the structural layer completely covering the intermediate region, the structural layer sequentially comprising an N-type bragg mirror layer and an MQW multi-quantum well layer in a first direction comprises:
growing the structural layer on the substrate, wherein the structural layer completely covers the substrate;
etching the structural layer to expose the edge area of the substrate;
the structural layer sequentially comprises an N-type Bragg reflector layer and an MQW multi-quantum well layer in the first direction.
5. The method of claim 1, wherein the P-type electrode and the N-type electrode are made of the same material.
6. The method of claim 1, wherein the oxide layer has a thickness in the first direction in a range from 8nm to 12nm, inclusive.
7. A VCSE L chip fabricated by the method of any one of claims 1-6, wherein the VCSE L chip comprises:
a substrate divided into a middle region and an edge region surrounding the middle region;
the structural layer is arranged on the middle area, the structural layer completely covers the middle area, the structural layer sequentially comprises an N-type Bragg reflector layer and an MQW multi-quantum well layer in a first direction, the first direction is perpendicular to the substrate, and the substrate points to the P-type Bragg reflector layer;
an oxide layer covering the edge region and covering the side wall of the structural layer and the surface of the side away from the substrate;
the P-type Bragg reflector layer is arranged on one side, away from the structural layer, of the oxide layer, and the P-type Bragg reflector layer completely covers the middle area;
an electrode structure.
8. The VCSE L chip of claim 7, wherein the electrode structure comprises:
the P-type electrode is arranged on one side, away from the oxide layer, of the P-type Bragg reflector layer;
and the N-type electrode is arranged on one side of the oxide layer, which is far away from the substrate.
9. The VCSE L chip of claim 8, wherein the oxide layer covered by the P-bragg mirror layer is partially an oxide layer after oxidation and partially an oxide layer without oxidation;
the oxide layers covered by the N-type electrode are all oxide layers which are not subjected to oxidation treatment;
the exposed oxide layers are all the oxide layers after oxidation treatment.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6515308B1 (en) * | 2001-12-21 | 2003-02-04 | Xerox Corporation | Nitride-based VCSEL or light emitting diode with p-n tunnel junction current injection |
| CN105337166A (en) * | 2015-11-30 | 2016-02-17 | 武汉电信器件有限公司 | Molecular beam epitaxy growing method of high-speed vertical-cavity surface-emitting laser |
| CN106848838A (en) * | 2017-04-06 | 2017-06-13 | 中国科学院半导体研究所 | GaN base VCSEL chips and preparation method based on porous DBR |
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| WO2002084829A1 (en) * | 2001-04-11 | 2002-10-24 | Cielo Communications, Inc. | Long wavelength vertical cavity surface emitting laser |
| US8355421B2 (en) * | 2009-09-16 | 2013-01-15 | Furukawa Electric Co., Ltd | Vertical-cavity surface emitting laser |
| US9335262B2 (en) * | 2011-08-25 | 2016-05-10 | Palo Alto Research Center Incorporated | Gap distributed Bragg reflectors |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6515308B1 (en) * | 2001-12-21 | 2003-02-04 | Xerox Corporation | Nitride-based VCSEL or light emitting diode with p-n tunnel junction current injection |
| CN105337166A (en) * | 2015-11-30 | 2016-02-17 | 武汉电信器件有限公司 | Molecular beam epitaxy growing method of high-speed vertical-cavity surface-emitting laser |
| CN106848838A (en) * | 2017-04-06 | 2017-06-13 | 中国科学院半导体研究所 | GaN base VCSEL chips and preparation method based on porous DBR |
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