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CN1088945C - Signal conditioning device with stable output - Google Patents

Signal conditioning device with stable output Download PDF

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CN1088945C
CN1088945C CN 97116957 CN97116957A CN1088945C CN 1088945 C CN1088945 C CN 1088945C CN 97116957 CN97116957 CN 97116957 CN 97116957 A CN97116957 A CN 97116957A CN 1088945 C CN1088945 C CN 1088945C
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signal
digital
analog
output
comparator
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CN1213227A (en
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郑文平
王明坤
郭芳钿
许绩贺
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Holtek Semiconductor Inc
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Abstract

A signal modulation device with stable output mainly comprises a comparator, an inverter, a digital/analog converter and an up/down counter, wherein the up/down signal output by the comparator is fed back and connected to the digital/analog converter by the connection mode of the inverter, so that the oscillation phenomenon generated by the output signal of the comparator when the output signal of the digital/analog converter is close to the level of the analog input signal of the comparator is avoided, namely the oscillation phenomenon of the up/down signal is eliminated, the accuracy of signal conversion can be improved, and the occurrence of signal errors is reduced.

Description

具有稳定输出的讯号调变装置Signal conditioning device with stable output

本发明涉及一种具有稳定输出的讯号调变装置,特别是一种运用于计数式模拟/数字转换器或轨迹式模拟/数字转换器中,使输出讯号稳定而不发生振荡的讯号调变装置。The present invention relates to a signal modulation device with stable output, especially a signal modulation device used in counting analog/digital converters or track analog/digital converters to stabilize the output signal without oscillation .

一般在使用模拟/数字转换器的讯号调变装置时,特别是对计数式或轨迹式的模拟/数字转换器而言,该转换器内部大多设有一比较器及一数字/模似转换器。图1所示为一常用的模拟/数字转换器,主要包括一比较器1、一上/下计数器2及一数字/模拟转换器3等,其中该比较器1的非反向输入端连接一输入模拟讯号(VIN),而反向输入端则连接该数字/模拟转换器3所输出的模拟讯号(VDAC),之后该比较器1再输出一上升/下降讯号(VCMP)而连接于上/下计数器2,该上/下计数器2另连接有时钟讯号(clock),可将上升/下降讯号(VCMP)加以计数而产生数字讯号输出,该数字讯号输出经D0、D1、D2、D3再与数字/模拟转换器3相连接。关于数字/模拟转换器3的电路请参阅图2,图2为常用阶梯式数字/模拟转换器,为一般计数式及轨迹式模拟/数字转换器中所广泛使用,该阶梯式数字/模拟转换器借由电阻R,2R所构成的电路,可将一数字讯号转换为模拟讯号(VDAC)输出,然而当该模拟讯号(VDAC)与比较器1的非反向输入端所连接的输入模拟讯号(VIN)的电平相接近时,则该上升/下降讯号(VCMP)会产生振荡现象,请参阅图3a与图3b,其所示为常用模拟讯号(VDAC)与输入模拟讯号(VIN)电平比较的讯号振荡示意图,图3a所示为模拟讯号(VDAC)于高电平时,而输入模拟讯号(VIN)系由低电平变为高电平的状态,如图3a与图3b中T1至T2时间区段,即表示由于输入模拟讯号(VIN)的高电平与模拟讯号(VDAC)的高电平相接近时(一般为±5mv-20mv范围内),使用得上升/下降讯号(VCMP)产生不稳定振荡输出现象。另图3b所示为模拟讯号(VDAC)于低电平时,而输入模拟讯号(VIN)系由高电平转变为低电平,由于该输入模拟讯号(VIN)的低电平与模拟讯号(VDAC)的低电平相接近(一般为±5mv-20mv范围内),使得上升/下降讯号(VCMP)产生不稳定的振荡现象。此二种讯号的振荡结果将造成讯号严重错误,使得上/下计数器无法计数,进而破坏整体电路的讯号转换,对转换器的电路影响极其深远。Generally, when a signal modulating device of an analog/digital converter is used, especially for a counting type or a track type analog/digital converter, a comparator and a digital/analog converter are mostly provided inside the converter. Figure 1 shows a commonly used analog/digital converter, which mainly includes a comparator 1, an up/down counter 2 and a digital/analog converter 3, etc., wherein the non-inverting input of the comparator 1 is connected to a Input an analog signal (V IN ), and the inverting input terminal is connected to the analog signal (V DAC ) output by the digital/analog converter 3, and then the comparator 1 outputs a rising/falling signal (V CMP ) to connect In the up/down counter 2, the up/down counter 2 is also connected with a clock signal (clock), which can count the rising/falling signal (V CMP ) to generate a digital signal output, and the digital signal output is passed through D0, D1, D2 , D3 is connected with the digital/analog converter 3 again. Please refer to Figure 2 for the circuit of the digital/analog converter 3. Figure 2 is a commonly used ladder digital/analog converter, which is widely used in general counting and track analog/digital converters. The ladder digital/analog conversion A circuit composed of resistors R and 2R can convert a digital signal into an analog signal (V DAC ) for output. However, when the analog signal (V DAC ) is connected to the non-inverting input of comparator 1 When the level of the analog signal (V IN ) is close, the rising/falling signal (V CMP ) will oscillate, please refer to Figure 3a and Figure 3b, which shows the common analog signal (V DAC ) and the input analog The signal oscillation schematic diagram of signal (V IN ) level comparison, Figure 3a shows that when the analog signal (V DAC ) is at high level, and the input analog signal (V IN ) changes from low level to high level, The period from T 1 to T 2 in Figure 3a and Figure 3b means that when the high level of the input analog signal (V IN ) is close to the high level of the analog signal (V DAC ) (generally ±5mv- In the range of 20mv), the use of rising/falling signal (V CMP ) produces unstable oscillation output phenomenon. Figure 3b also shows that when the analog signal (V DAC ) is at low level, the input analog signal (V IN ) changes from high level to low level, because the low level of the input analog signal (V IN ) and The low level of the analog signal (V DAC ) is close (generally within the range of ±5mv-20mv), which makes the rising/falling signal (V CMP ) produce unstable oscillation. The oscillation result of these two kinds of signals will cause a serious signal error, making the up/down counter unable to count, and then destroying the signal conversion of the whole circuit, which has a profound impact on the circuit of the converter.

有鉴于上述缺陷,本发明人乃以多年之研究经验加以潜心研究实验,提出一构思合理、创意极佳且能有效改善上述缺陷的本发明。进而言之,本发明的主要目的在于提供一种能消除输出振荡杂讯且具有稳定输出讯号的讯号调变装置,借由改变电路的反馈技术而达到稳定输出、提高讯号可靠度,以避免讯号振荡现象发生。In view of the above-mentioned defects, the present inventor has devoted himself to research and experiments based on many years of research experience, and proposed an invention with reasonable conception, excellent creativity and can effectively improve the above-mentioned defects. Furthermore, the main purpose of the present invention is to provide a signal modulation device capable of eliminating output oscillating noise and having a stable output signal, by changing the feedback technology of the circuit to achieve stable output and improve signal reliability, so as to avoid signal Oscillation occurs.

为使对本发明的目的、特征及功效有更进一步的了解,现结合附图对本发明的技术方案详细说明如后:In order to have a further understanding of the purpose, features and effects of the present invention, now in conjunction with the accompanying drawings the technical solutions of the present invention are described in detail as follows:

图1为常用的模拟/数字转换电路图。Figure 1 is a commonly used analog / digital conversion circuit diagram.

图2为常用的阶梯式数字/模拟转换器电路图。Figure 2 is a commonly used ladder digital / analog converter circuit diagram.

图3a、图3b为常用模拟讯号与输入模拟讯号的电平相比较时比较器输出讯号振荡示意图。3a and 3b are schematic diagrams of the output signal oscillation of the comparator when the common analog signal is compared with the level of the input analog signal.

图4为本发明实施例的电路图。Fig. 4 is a circuit diagram of an embodiment of the present invention.

图5a、图5b为本发明实施例比较讯号动作时对照图3a与图3b的输出讯号示意图。FIG. 5a and FIG. 5b are schematic diagrams of the output signal compared with FIG. 3a and FIG. 3b when comparing the signal operation according to the embodiment of the present invention.

请参阅图4,图4为本发明实施例的电路图,主要为一讯号调变装置10,该装置包括一比较器11、一反向器12、一数字/模拟转换器13及一上/下计数器14,其中该比较器11的非反向输入端连接一输入模拟讯号(VIN),而反向输入端则连接该数字/模拟转换器13所输出的模拟讯号(VDAC),该比较器11将两模拟讯号加以比较而产生一上升/下降讯号(VCMP),该上升/下降讯号(VCMP)为一状态讯号输出,可显示出下一个模拟讯号输入与上一个模拟讯号输入相互比较为增加或减少。该上升/下降讯号(VCMP)连接于上/下计数器14并配合时钟讯号加以计数而产生数字讯号输出,该数字讯号输出再连接于数字/模拟转换器13,该转换器主要为一阶梯式的数字/模拟转换器13,用以将数字讯号转变为模拟讯号(VDAC)而输出连接于比较器11的反向输入端。另一方面,该上升/下降讯号连接于该反向器12,该反向器12再连接于阶梯式数字/模拟转换器13中的阶梯式电路末端而为一电路反馈的连接方式,借由此电路的反馈方式即可消除上升/下降讯号(VCMP)的讯号振荡现象,意即当模拟讯号(VDAC)于高电平状态,而输入模拟讯号(VIN)系由低电平转换为高电平且两讯号之高电平相接近时,由于该上升/下降讯号(VCMP)经由反向器12将上升/下降讯号(VCMP)加以反向而反馈连接于数字/模拟转换器13的阶梯电路中之末端做讯号补偿,而可确保比较器11所输出的上升/下降讯号(VCMP)为一稳定值,避免讯号振荡现象发生。Please refer to Fig. 4, Fig. 4 is the circuit diagram of the embodiment of the present invention, mainly is a signal modulation device 10, and this device comprises a comparator 11, an inverter 12, a digital/analog converter 13 and an up/down Counter 14, wherein the non-inverting input terminal of the comparator 11 is connected to an input analog signal (V IN ), and the inverting input terminal is connected to the analog signal (V DAC ) output by the digital/analog converter 13, the comparator The device 11 compares the two analog signals to generate a rising/falling signal (V CMP ), which is a status signal output, which can show the relationship between the next analog signal input and the previous analog signal input. Compare as increase or decrease. The rising/falling signal (V CMP ) is connected to the up/down counter 14 and counted with the clock signal to generate a digital signal output, and the digital signal output is then connected to the digital/analog converter 13, which is mainly a ladder The digital/analog converter 13 is used to convert the digital signal into an analog signal (V DAC ), and the output is connected to the inverting input terminal of the comparator 11 . On the other hand, the rising/falling signal is connected to the inverter 12, and the inverter 12 is connected to the end of the ladder circuit in the ladder digital/analog converter 13 to be a circuit feedback connection mode, by The feedback method of this circuit can eliminate the signal oscillation phenomenon of the rising/falling signal (V CMP ), that is, when the analog signal (V DAC ) is in a high state, and the input analog signal (V IN ) is switched from a low level When the high level is high and the high levels of the two signals are close to each other, since the rising/falling signal (V CMP ) reverses the rising/falling signal (V CMP ) through the inverter 12, the feedback is connected to the digital/analog conversion Signal compensation is performed at the end of the ladder circuit of the comparator 13 to ensure that the rising/falling signal (V CMP ) output by the comparator 11 is a stable value and avoid signal oscillation.

请参阅图5a与图5b,其为本发明实施例比较讯号动作时对照图3的输出讯号示意图,其中图5a为上升/下降讯号(VCMP)由高电平转变为低电平,而模拟讯号(VDAC)的高电平与输入模拟讯号(VIN)相接近时,借由本发明的实施,使得该模拟讯号(VDAC)产生一向下之位移电压(Vof),可避免该上升/下降讯号(VCMP)产生振荡而不稳定。图5b为上升/下降讯号(VCMP)由低电平转变为高电平,而模拟讯号(VDAC)之高电平与输入模拟讯号(VIN)相接近时,可由本发明之实施,使得该模拟讯号(VDAC)产生一向上之位移电压(Vof),可避免该上升/下降讯号(VCMP)发生振荡而不稳定。Please refer to Fig. 5a and Fig. 5b, which are the schematic diagrams of the output signal compared with Fig. 3 when comparing the signal action of the embodiment of the present invention, wherein Fig. 5a shows that the rise/fall signal (V CMP ) changes from high level to low level, and the analog When the high level of the signal (V DAC ) is close to the input analog signal (V IN ), the implementation of the present invention makes the analog signal (V DAC ) generate a downward displacement voltage (V of ), which can avoid the rise The /falling signal (V CMP ) oscillates and becomes unstable. Figure 5b shows that the rise/fall signal (V CMP ) changes from low level to high level, and the high level of the analog signal (V DAC ) is close to the input analog signal (V IN ), which can be implemented by the present invention. Making the analog signal (V DAC ) generate an upward displacement voltage (V of ), which can prevent the rising/falling signal (V CMP ) from oscillating and becoming unstable.

本发明的实施例经由改变电路反馈的方式而能有效地解决一般讯号调变装置会产生讯号振荡的现象,尤其当使用计数式模拟/数字转换器亦或轨迹式模拟/数字转换器等,更能显示出本发明的实施例改善常用装置的缺陷之功效。比较图3a、图3b与图5a、图5b,可明显观察出本发明已有效避免比较器输出讯号的不稳定状态,本发明讯号调变装置的实施例不仅能消除讯号振荡现象,且电路所增加的成本不多,并不会造成因电路改变而成本大量增加的负担。The embodiments of the present invention can effectively solve the phenomenon of signal oscillation in general signal modulation devices by changing the way of circuit feedback, especially when using counting analog/digital converters or track analog/digital converters, etc. It can be shown that embodiments of the present invention ameliorate the disadvantages of conventional devices. Comparing Fig. 3a, Fig. 3b with Fig. 5a, Fig. 5b, it can be clearly observed that the present invention has effectively avoided the unstable state of the output signal of the comparator, and the embodiment of the signal modulation device of the present invention can not only eliminate the signal oscillation phenomenon, but also The increased cost is not much, and does not cause the burden of a large cost increase due to circuit changes.

综上所述,本发明的电路设计不复杂、繁琐,而整体电路运作设想却深富实施的具体性,为目前市面上所未见。To sum up, the circuit design of the present invention is not complicated and cumbersome, but the overall circuit operation concept is rich in implementation specificity, which is unprecedented in the market.

Claims (3)

1. one kind has the stable signal changing device of exporting, and this device includes:
One staged digital/analog converter;
One comparator, its non-inverting input connect analog signal input, and reverse input end then connects the analog signal that described digital/analog converter is exported, and two signals are compared to produce a rising/decline signal;
One reverser, its input are connected in this rising/decline signal, and output then is connected in the end of stairing circuit in this digital/analog converter, in order to will rise/the decline signal is reverse;
On one/and following counter, its input has rising/decline signal and clock signal, output digital signal and connect this digital/analog converter after counting.
2. the signal changing device that has stable output according to claim 1, wherein this rising/decline signal is the output of state signal.
3. have the signal changing device of stable output according to claim 1, wherein this signal changing device is a path type analog/digital converter.
CN 97116957 1997-09-29 1997-09-29 Signal conditioning device with stable output Expired - Fee Related CN1088945C (en)

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CN 97116957 CN1088945C (en) 1997-09-29 1997-09-29 Signal conditioning device with stable output

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CN 97116957 CN1088945C (en) 1997-09-29 1997-09-29 Signal conditioning device with stable output

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CN1088945C true CN1088945C (en) 2002-08-07

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