CN108877868A - Parallel apparatus for testing chip and test method - Google Patents
Parallel apparatus for testing chip and test method Download PDFInfo
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- CN108877868A CN108877868A CN201810716922.0A CN201810716922A CN108877868A CN 108877868 A CN108877868 A CN 108877868A CN 201810716922 A CN201810716922 A CN 201810716922A CN 108877868 A CN108877868 A CN 108877868A
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- 238000012360 testing method Methods 0.000 title claims abstract description 120
- 238000010998 test method Methods 0.000 title abstract description 6
- 238000000034 method Methods 0.000 claims description 13
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 4
- 238000011161 development Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000003362 replicative effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- Tests Of Electronic Circuits (AREA)
Abstract
The present invention relates to parallel apparatus for testing chip and test method, which includes SOM module and several FPGA modules, several FPGA modules are connect with SOM module, is connected with each other between several FPGA modules；FPGA module is connect with the test daughter board being equipped with.Several FPGA modules that the present invention is arranged by setting array, FPGA module is controlled by SOM module, and test information is issued to FPGA module by SOM module, FPGA module is converted to required logic for information is tested, and is copied to other FPGA modules and test daughter board, and logic is distributed to the test daughter board being attached thereto, realize the concurrent testing of chip, to improve testing efficiency, meet the testing requirement of multi-chip, reduces testing cost.
Description
Technical field
The present invention relates to apparatus for testing chip, more specifically refer to parallel apparatus for testing chip and test method.
Background technique
With the development of technology, demand of the people to electronic product is increasing, as mobile phone, computer and recently rise
Artificial intelligence product etc..Not only there is the basic storage chip of NAND Flash, has also emerged and encapsulated together with controller
EMMC, the chips such as UFS.Storage capacity requirement is increasing, and size is also smaller and smaller, how to reduce the testing cost of chip with
And testing efficiency is improved, become the problem of tester studies always.
Standardization, opening are the targets that each device manufacturer pursues.Advanced test equipment quotient in the world, such as love moral
Ten thousand, Teradyne etc. is all proposed medium-to-high grade automatic test equipment for the chip of mainstream, but faces the continuous renewal of chip,
Test equipment can not also accomplish exhaustive.For NAND Flash manufacturer, purchase Automatic Test Equipment is most common
Selection, but buying expenses are very big expenditures, or with the diversification and complication of product, single equipment can not
Meet the testing requirement of multi-chip, and by multimeter, the manual tests such as oscillograph and signal generator do not require nothing more than tester
Member has higher professional standing and experience, and test period is long, cannot exclude human error factor, is less able to achieve high-volume
Automatic test demand.
Therefore, it is necessary to design a kind of device, the testing requirement for meeting multi-chip is realized, and improve testing efficiency, reduce
Testing cost.
Summary of the invention
It is an object of the invention to overcome the deficiencies of existing technologies, parallel apparatus for testing chip and test method are provided.
To achieve the above object, the present invention uses following technical scheme：Parallel apparatus for testing chip includes SOM module
And several FPGA modules, several FPGA modules connect with the SOM module, mutually interconnect between several FPGA modules
It connects；The FPGA module is connect with the test daughter board being equipped with.
Its further technical solution is：The FPGA module is connect by connector with the test daughter board.
Its further technical solution is：The test daughter board is equipped with several pedestals connecting with objective chip.
The present invention also provides parallel chip detecting methods, include：
SOM module is set；
FPGA module obtains bus timing logic；
FPGA module reproducting bus sequential logic；
Bus timing logic is distributed to the objective chip on test daughter board by FPGA module；
The information of objective chip on feedback test daughter board is to SOM module.
Its further technical solution is：The FPGA module obtains the step of bus timing logic, including walks in detail below
Suddenly：
FPGA module obtains test information from SOM module；
Test information is converted into bus timing logic.
Its further technical solution is：In the step of FPGA module obtains test information from SOM module, the test
Information includes control instruction and data information.
Its further technical solution is：The step of information of objective chip on the feedback test daughter board to SOM module
Before, further include：
The objective chip on each test daughter board is tested using bus timing logic.
Its further technical solution is：After the step of FPGA module reproducting bus sequential logic, further include：
The bus timing logic of duplication is distributed to remaining FPGA module.
Compared with the prior art, the invention has the advantages that：Parallel apparatus for testing chip of the invention, by the way that battle array is arranged
Several FPGA modules for arranging arrangement control FPGA module by SOM module, and issue test information to FPGA mould by SOM module
Block, FPGA module are converted to required logic for information is tested, and are copied to other FPGA modules and test daughter board, by logic
It is distributed to the test daughter board being attached thereto, realizes the concurrent testing of chip, to improve testing efficiency, meets the test need of multi-chip
It asks, reduces testing cost.
The invention will be further described in the following with reference to the drawings and specific embodiments.
Detailed description of the invention
Fig. 1 is the structural block diagram for the parallel apparatus for testing chip that the specific embodiment of the invention provides；
Fig. 2 is the schematic flow diagram for the parallel chip detecting method that the specific embodiment of the invention provides；
Fig. 3 is the sub-step schematic flow diagram for the parallel chip detecting method that the specific embodiment of the invention provides.
Specific embodiment
In order to more fully understand technology contents of the invention, combined with specific embodiments below to technical solution of the present invention into
One step introduction and explanation, but not limited to this.
It should be appreciated that ought use in this specification and in the appended claims, term " includes " and "comprising" instruction
Described feature, entirety, step, operation, the presence of element and/or component, but one or more of the other feature, whole is not precluded
Body, step, operation, the presence or addition of element, component and/or its set.
It is also understood that mesh of the term used in this present specification merely for the sake of description specific embodiment
And be not intended to limit the application.As present specification and it is used in the attached claims, unless on
Other situations are hereafter clearly indicated, otherwise " one " of singular, "one" and "the" are intended to include plural form.
It will be further appreciated that the term "and/or" used in present specification and the appended claims is
Refer to any combination and all possible combinations of one or more of associated item listed, and including these combinations.
Specific embodiment as shown in Figures 1 to 3, parallel apparatus for testing chip provided in this embodiment and test method, fortune
For realizing the testing requirement for meeting multi-chip, and improve test in integrated circuit testing and the test process of solid state hard disk
Efficiency reduces testing cost.
Fig. 1 is please referred to, Fig. 1 is the structural block diagram for the parallel apparatus for testing chip that specific embodiment provides, as shown in Figure 1,
Parallel apparatus for testing chip, includes SOM module 1 and several FPGA modules 2, several FPGA modules 2 and SOM module 1
It connects, is connected with each other between several FPGA modules 2；FPGA module 2 is connect with the test daughter board 3 being equipped with.
It by several FPGA modules 2 by the way of array, connect with SOM module 1, is controlled by SOM module 1 respectively, and
Several FPGA modules 2 are connected with each other, and test information can be transmitted mutually, realize the concurrent testing to chip., and increase test
The quantity of plate 3 and pedestal 5 improves testing efficiency and reduces development cost.Meanwhile FPGA module 2 can be with external different type
Test daughter board 3, greatly improve the flexibility of test.
Further, above-mentioned FPGA module 2 is connect by connector 4 with test daughter board 3.
Certainly, FPGA module 2 can directly be connect with test daughter board 3, tested and arranged pedestal 5 on daughter board 3, objective chip is connected
It connects on pedestal 5, the test of objective chip can be carried out, it is easy to operate.
In addition, in one embodiment, above-mentioned test daughter board 3 is equipped with several pedestals 5 connecting with objective chip.It can
To be equipped with multiple pedestals 5 on test daughter board 3, the bus timing logic of FPGA module 2 is got by test daughter board 3, carries out mesh
Chip parallel test is marked, to improve testing efficiency, meets the testing requirement of multi-chip, reduces testing cost.
In one embodiment, above-mentioned test device supports network interface or SD card electrifying startup, it can be achieved that specified FPGA
The power on configuration of module 2.
In one embodiment, the type of above-mentioned test daughter board 3 can support eMMC, TF card, SSD test.
In one embodiment, above-mentioned connector 4 is FMC connector 4.
In one embodiment, above-mentioned FPGA module 2, FMC connector 4, test daughter board 3 and pedestal 5 quantity at least
It is respectively one.
Above-mentioned parallel apparatus for testing chip, several FPGA modules 2 arranged by setting array, is controlled by SOM module 1
FPGA module 2 processed, and issue test information to FPGA module 2 by SOM module 1, FPGA module 2 will test needed for information is converted to
Logic, and be copied to other FPGA modules 2 and test daughter board 3, logic be distributed to the test daughter board 3 being attached thereto, it is real
The concurrent testing of existing chip meets the testing requirement of multi-chip to improve testing efficiency, reduces testing cost.
Referring to Fig. 2, Fig. 2 is the schematic flow diagram for the parallel chip detecting method that specific embodiment provides, such as Fig. 2 institute
Show, parallel chip detecting method, includes step S101~S107.
S101, setting SOM module 1.
Specifically, host computer 6 is programmed SOM module 1 by high-level programming language and crossstool chain, makes it
Have storage test information and the function for 2 gathering information of FPGA module.
S102, FPGA module 2 obtain bus timing logic.
In one embodiment, above-mentioned S102 may include having S1021~S1022：
S1021, FPGA module 2 obtain test information from SOM module 1；
S1022, test information is converted into bus timing logic.
Above-mentioned test information includes control instruction and data information.
S103,2 reproducting bus sequential logic of FPGA module；
Bus timing logic is distributed to the objective chip on test daughter board 3 by S104, FPGA module 2.
FPGA module 2 is distributed to the objective chip on test daughter board 3 by FMC connector 4 after replicating more parts, surveyed
Examination.
S105, the bus timing logic of duplication is distributed to remaining FPGA module 2.
In addition, the bus timing logic of duplication can also be distributed to remaining FPGA module 2 by above-mentioned FPGA module 2, with
Improve testing efficiency.
S106, the objective chip on each test daughter board 3 is tested using bus timing logic.
S107, objective chip on feedback test daughter board 3 information to SOM module 1.
Specifically, FPGA module 2 obtains the test result of objective chip on test daughter board 3, and the result is fed back to SOM
Module 1, to complete the measurement to certain chip；
Specifically being integrated, and feed back to SOM mould after the status information of objective chip and returned data are collected
Block 1 completes the measurement to certain chip.
In one embodiment, above-mentioned S105 synchronous can be carried out with S104.
Above-mentioned parallel chip detecting method, by issuing test information to FPGA module 2, FPGA module by SOM module 1
2 by test information be converted to required logic, and be copied to other FPGA modules 2 and test daughter board 3, by logic be distributed to
Connection test daughter board 3, realize the concurrent testing of chip, to improve testing efficiency, meet the testing requirement of multi-chip, reduce
Testing cost.
It is above-mentioned that technology contents of the invention are only further illustrated with embodiment, in order to which reader is easier to understand, but not
It represents embodiments of the present invention and is only limitted to this, any technology done according to the present invention extends or recreation, by of the invention
Protection.Protection scope of the present invention is subject to claims.
Claims (8)
1. parallel apparatus for testing chip, which is characterized in that include SOM module and several FPGA modules, several FPGA
Module is connect with the SOM module, is connected with each other between several FPGA modules；The FPGA module and the test daughter board being equipped with
Connection.
2. parallel apparatus for testing chip according to claim 1, which is characterized in that the FPGA module by connector with
The test daughter board connection.
3. parallel apparatus for testing chip according to claim 2, which is characterized in that the test daughter board is equipped with several
The testing base being connect with objective chip.
4. parallel chip detecting method, which is characterized in that include：
SOM module is set；
FPGA module obtains bus timing logic；
FPGA module reproducting bus sequential logic；
Bus timing logic is distributed to the objective chip on test daughter board by FPGA module；
The information of objective chip on feedback test daughter board is to SOM module.
5. parallel chip detecting method according to claim 4, which is characterized in that the FPGA module obtains bus timing
The step of logic, including step in detail below：
FPGA module obtains test information from SOM module；
Test information is converted into bus timing logic.
6. parallel chip detecting method according to claim 5, which is characterized in that the FPGA module is obtained from SOM module
In the step of taking test information, the test information includes control instruction and data information.
7. parallel chip detecting method according to claim 5, which is characterized in that the target on the feedback test daughter board
Before the step of information of chip to SOM module, further include：
The objective chip on each test daughter board is tested using bus timing logic.
8. parallel chip detecting method according to claim 4, which is characterized in that the FPGA module reproducting bus timing
After the step of logic, further include：
The bus timing logic of duplication is distributed to remaining FPGA module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201810716922.0A CN108877868A (en) | 2018-07-03 | 2018-07-03 | Parallel apparatus for testing chip and test method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810716922.0A CN108877868A (en) | 2018-07-03 | 2018-07-03 | Parallel apparatus for testing chip and test method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110161401A (en) * | 2019-06-05 | 2019-08-23 | 中国科学院理化技术研究所 | A kind of superconduction chip low temperature test device |
| CN111487524A (en) * | 2020-05-15 | 2020-08-04 | 上海华力微电子有限公司 | Universal chip test system, test method and storage medium |
| CN111722097A (en) * | 2020-07-01 | 2020-09-29 | 无锡中微亿芯有限公司 | Multi-die FPGA with interconnection test function |
| CN113035267A (en) * | 2021-03-25 | 2021-06-25 | 长江存储科技有限责任公司 | Semiconductor testing device, data processing method, equipment and storage medium |
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| CN103149468A (en) * | 2012-12-28 | 2013-06-12 | 中国空间技术研究院 | Electron component parameter testing device |
| CN103558543A (en) * | 2013-11-20 | 2014-02-05 | 太仓思比科微电子技术有限公司 | Mass production testing method of CIS chip |
| CN205176829U (en) * | 2013-07-25 | 2016-04-20 | 中国航天科工集团第三研究院第八三五七研究所 | Multiple communications protocol's of test configuration system on a chip's test system |
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2018
- 2018-07-03 CN CN201810716922.0A patent/CN108877868A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103149468A (en) * | 2012-12-28 | 2013-06-12 | 中国空间技术研究院 | Electron component parameter testing device |
| CN205176829U (en) * | 2013-07-25 | 2016-04-20 | 中国航天科工集团第三研究院第八三五七研究所 | Multiple communications protocol's of test configuration system on a chip's test system |
| CN103558543A (en) * | 2013-11-20 | 2014-02-05 | 太仓思比科微电子技术有限公司 | Mass production testing method of CIS chip |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110161401A (en) * | 2019-06-05 | 2019-08-23 | 中国科学院理化技术研究所 | A kind of superconduction chip low temperature test device |
| CN111487524A (en) * | 2020-05-15 | 2020-08-04 | 上海华力微电子有限公司 | Universal chip test system, test method and storage medium |
| CN111487524B (en) * | 2020-05-15 | 2022-03-11 | 上海华力微电子有限公司 | Universal chip test system, test method and storage medium |
| CN111722097A (en) * | 2020-07-01 | 2020-09-29 | 无锡中微亿芯有限公司 | Multi-die FPGA with interconnection test function |
| CN111722097B (en) * | 2020-07-01 | 2022-02-18 | 无锡中微亿芯有限公司 | Multi-die FPGA with interconnection test function |
| CN113035267A (en) * | 2021-03-25 | 2021-06-25 | 长江存储科技有限责任公司 | Semiconductor testing device, data processing method, equipment and storage medium |
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