CN108874442A - A kind of implementation method of the Domestic Platform system simulation based on QEMU - Google Patents
A kind of implementation method of the Domestic Platform system simulation based on QEMU Download PDFInfo
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- CN108874442A CN108874442A CN201810585235.XA CN201810585235A CN108874442A CN 108874442 A CN108874442 A CN 108874442A CN 201810585235 A CN201810585235 A CN 201810585235A CN 108874442 A CN108874442 A CN 108874442A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/70—Software maintenance or management
- G06F8/76—Adapting program code to run in a different environment; Porting
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F8/40—Transformation of program code
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Abstract
The present invention provides a kind of implementation method of Domestic Platform system simulation based on QEMU, belong to code migrating technical field, host operating system of the present invention operates on Domestic Platform, and X86, which is applied, to be translated and executed to instruction by the QEMU subscriber board virtual machine of operation on the host computer system.The User space environment for simulating x86 by transplanting QEMU on Domestic Platform, realizes the translation of x86 program instruction to domestic processor instruction.
Description
Technical field
The present invention relates to code migrating technology more particularly to a kind of implementation methods of the Domestic Platform system simulation based on QEMU.
Background technique
At present, x86 processor occupies leading position in the application.Because the multipad of x86 framework is more more
Sample, many business softwares are all based on x86 framework, so the microprocessor of RISC framework is wanted to be widely used, it must
It must first realize compatible with x86 framework.Therefore, code migrating becomes a key factor of software and hardware coordinated development.Two into
Interpretation method processed comes into being, it helps to run in the software transplanting in original architecture to new architecture.
The hardware simulator project that QEMU increases income as one, other than supporting x86 architectural framework, also support ARM,
The multiple hardwares framework such as MIPS, PowerPC, IA64.The method that QEMU uses modularized design, it is thus possible to support a variety of more
The peripheral hardware hardware of sample, and can easily be expanded.There are two types of main operating modes by QEMU：User mode simulation model,
It also is user mode.QEMU can start the Linux program that those are the compiling of different central processing units.And Windows is its master
Want target.System mode simulation model, is also system model.QEMU can simulate entire computer system, including central processing
Device and other peripheral equipments.It to carry out test for the cross-platform program write and except mistake work becomes easy.It can also be used
Carry out the virtual several different virtual computers on a host.
Summary of the invention
In order to solve the above technical problems, the realization for the Domestic Platform system simulation that the invention proposes a kind of based on QEMU
Method.
Host operating system of the invention operates on Domestic Platform, and X86 is applied by running on the host computer system
QEMU subscriber board virtual machine is translated and is executed to instruction.QEMU introduces a set of code generation mechanism, referred to as TCG
(Tiny CodeGenerator) .TCG introduces a kind of intermediate command, and source machine instruction is first translated intermediate command, then
It is translated target instruction target word, source and target architecture has logically been isolated.Intermediate command has RISC feature, instruction
Number is less, therefore, reduces the difficulty of transplanting.Sourse instruction may use a plurality of intermediate command to emulate, but not all source
Machine instruction will be translated into intermediate command, those are the source machine instruction that can determine its movement in the translating phase, such as handle
Device pattern switching instructs, and without being translated into intermediate command, is realized using C function (referred to as helper function),
Serve as interpreter to when the instruction of this kind of source machine, what is actually generated is the call instruction to helper function.
The transplanting and compiling that the invention mainly comprises QEMU virtual machines under Domestic Platform.Implementation：
QEMU to the groundwork that Domestic Platform is transplanted be for domestic processor realize code generator TCG rear end, i.e., in
Between instruction arrive domestic processor target instruction target word conversion.The basic process of conversion is：Sequential scan intermediate command sequence, by every
Intermediate command is converted to one or several target instruction target words.The instruction dynamic translation in this stage must first solve destination register
Scheduling problem, as operand (distributor) the reasonable distribution register (destination register) of intermediate command.Target
Register scheduling problem is actually considered as a part that intermediate command is converted to target instruction target word, it is determined that the behaviour of target instruction target word
It counts (destination register), and generates some relevant target instruction target words and carry out necessary data duplication.Finally according to operand
Generate the operation code of target instruction target word.Qemu source code is modified, inserts domestic processor code generator TCG's
Rear end, so as to complete intermediate command to the translation of domestic processor instruction.According to domestic processor instruction system format,
The process that intermediate command translates the domestic processor instruction of target mainly passes through minor function such as and realizes.Tcg_out_mov is one
Content in register is transferred in another register；Tcg_out_movi_fixl is by one 64 immediate parameters
It is put into a register Ra, function will generate the instruction sequence of regular length；Tcg_out_movi is by one 64
Immediate parameter is put into a register Ra, and function will generate the instruction sequence of variable-length；Tcg_out_ld is disp
Register Ra Nei Rong Gui adds in deposit register Ra, is commonly used in integer load for generating address；tcg_out_
St is in the corresponding address space of data deposit register Rb and disp added value in register Ra；tgen_
Arithi posts instruction for generating fortune, and one of input value is immediate form；Tcg_out_addi is for generating addition
ADDQ instruction, one of input value are immediate form；Tcg_out_push is for generating into stack instruction, by register
Content stacking；Stack top data is deposited into register by tcg_out_pop for generating pull instruction.
The beneficial effects of the invention are as follows
Using the User space environment for transplanting QEMU simulation x86 on Domestic Platform, realize that x86 program instruction refers to domestic processor
The translation of order.Test result shows to can be realized operation of the x86 application program on Domestic Platform using the present invention, have very
High actual use value.
Detailed description of the invention
Fig. 1 is QEMU instruction translation architecture diagram；
Fig. 2 is binary instruction translation technology mechanism figure.
Specific embodiment
More detailed elaboration is carried out to the contents of the present invention below：
As shown in Figure 1, host operating system operates on Domestic Platform, X86 is applied by operating in master overall framework of the present invention
QEMU subscriber board virtual machine in machine system is translated and is executed to instruction.QEMU introduces a set of code generation mechanism, claims
For TCG (Tiny CodeGenerator), as shown in Figure 2.TCG introduces a kind of intermediate command, and source machine instructs first quilt
Intermediate command is translated, then is translated target instruction target word, source and target architecture has logically been isolated.Intermediate command has
RISC feature, number of instructions is less, therefore, reduces the difficulty of transplanting.Sourse instruction may use a plurality of intermediate command to emulate,
But not all source machine instruction will be translated into intermediate command, those are the source that can determine its movement in the translating phase
Machine instruction, as processor mode switching command utilizes C function (referred to as helper without being translated into intermediate command
Function) it realizes, serve as interpreter to when the instruction of this kind of source machine, what is actually generated is the call instruction to helper function.
The transplanting and compiling that the invention mainly comprises QEMU virtual machines under Domestic Platform.Implementation：
QEMU to the groundwork that Domestic Platform is transplanted be for domestic processor realize code generator TCG rear end, i.e., in
Between instruction arrive domestic processor target instruction target word conversion.
The basic process of conversion is：Every intermediate command is converted to one or several by sequential scan intermediate command sequence
Target instruction target word.The instruction dynamic translation in this stage must first solve the scheduling problem of destination register, as intermediate command
Operand (distributor) reasonable distribution register (destination register).Destination register scheduling problem can actually be seen
Work is a part that intermediate command is converted to target instruction target word, it is determined that the operand (destination register) of target instruction target word, and generate
Some relevant target instruction target words carry out necessary data duplication.The operation code of target instruction target word is finally generated according to operand.It is right
Qemu source code is modified, and is inserted the rear end of domestic processor code generator TCG, is arrived so as to complete intermediate command
The translation of domestic processor instruction.
According to domestic processor instruction system format, the process that intermediate command translates the domestic processor instruction of target is main
It is realized by such as minor function.Tcg_out_mov is transferred to the content in a register in another register；tcg_
One 64 immediate parameters are put into a register Ra by out_movi_fixl, and function will generate regular length
Instruction sequence；One 64 immediate parameters are put into a register Ra by tcg_out_movi, and function will produce
The instruction sequence of raw variable-length；Tcg_out_ld adds disp register Ra Nei Rong Gui in deposit register Ra, and one
As be used in integer load for generating address；Tcg_out_st in register Ra data deposit register Rb and
In the corresponding address space of disp added value；Tgen_arithi posts instruction for generating fortune, and one of input value is immediately
Number form formula；Tcg_out_addi is immediate form for generating addition ADDQ instruction, one of input value；tcg_
Out_push is for generating into stack instruction, by the content stacking of register；Tcg_out_pop, will for generating pull instruction
Stack top data is deposited into register.
Operating procedure is：
1）, in file tcg-target.c register allocation order is defined according to destination register scheduling；
2）, according to Alpha instruction system format, modify the rear end tcg intermediate command and translate the domestic processor instruction of target
Power function；
3）, use instruction ./configure -- enable-kvm -- enable-debug -- enable-vnc -- enable-
Werror -- target-list=" x86_64-softmmu " then uses make-j4；Make install compiling installation
The User space program of x86 framework；
4）, use qemu-x86_64x86_app run x86 framework program x86_app.
Claims (4)
1. a kind of implementation method of the Domestic Platform system simulation based on QEMU, which is characterized in that
Host operating system operates on Domestic Platform, and X86 applies virtual by the QEMU subscriber board of operation on the host computer system
Machine is translated and is executed to instruction；QEMU introduces a set of code generation mechanism, referred to as TCG, and TCG introduces a kind of centre
Instruction, source machine instruction is first translated intermediate command, then is translated target instruction target word, and source and target body has logically been isolated
Architecture；
Sourse instruction may use several intermediate commands to emulate, but not all source machine instruction will be translated into centre
Instruction, those are the source machine instruction that can determine its movement in the translating phase, without being translated into intermediate command, utilize C letter
Number is realized, is served as interpreter to when the instruction of this kind of source machine, what is actually generated is the call instruction to helper function.
2. the method according to claim 1, wherein
It mainly include transplanting and compiling of the QEMU virtual machine under Domestic Platform：
QEMU to the groundwork that Domestic Platform is transplanted be for domestic processor realize code generator TCG rear end, i.e., in
Between instruction arrive domestic processor target instruction target word conversion；The basic process of conversion is：Sequential scan intermediate command sequence, by every
Intermediate command is converted to one or several target instruction target words；
The instruction dynamic translation in this stage must first solve the scheduling problem of destination register, the as operand of intermediate command
Reasonable distribution register；Destination register scheduling problem is actually considered as one that intermediate command is converted to target instruction target word
Point, it is determined that the operand of target instruction target word, and generate relevant target instruction target word and carry out necessary data duplication；Finally according to behaviour
It counts and generates the operation code of target instruction target word；Qemu source code is modified, domestic processor code generator TCG is inserted
Rear end, so as to complete intermediate command to the translation of domestic processor instruction.
3. according to the method described in claim 2, it is characterized in that,
According to domestic processor instruction system format, the process that intermediate command translates the domestic processor instruction of target mainly passes through
As minor function is realized：
Tcg_out_mov is transferred to the content in a register in another register；Tcg_out_movi_fixl is by one
A 64 immediate parameters are put into a register Ra, and function will generate the instruction sequence of regular length；
One 64 immediate parameters are put into a register Ra by tcg_out_movi, and function will generate variable length
The instruction sequence of degree；
Tcg_out_ld adds disp register Ra Nei Rong Gui in deposit register Ra, is used for used in integer load
Generate address；
Tcg_out_st is the corresponding address space of data deposit register Rb and disp added value in register Ra
In；
Tgen_arithi posts instruction for generating fortune, and one of input value is immediate form；Tcg_out_addi is used for
Addition ADDQ instruction is generated, one of input value is immediate form；
Tcg_out_push is for generating into stack instruction, by the content stacking of register；Tcg_out_pop pops for generating
Instruction, stack top data is deposited into register.
4. according to the method described in claim 3, it is characterized in that,
Operating procedure is：
1）, in file tcg-target.c register allocation order is defined according to destination register scheduling；
2）, according to Alpha instruction system format, modify the rear end tcg intermediate command and translate the domestic processor instruction of target
Power function；
3）, use instruction ./configure -- enable-kvm -- enable-debug -- enable-vnc -- enable-
Werror -- target-list=" x86_64-softmmu " then uses make-j4；Make install compiling installation
The User space program of x86 framework；
4）, use qemu-x86_64x86_app run x86 framework program x86_app.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111552512A (en) * | 2020-03-23 | 2020-08-18 | 中国人民解放军战略支援部队信息工程大学 | Disk array configuration software cross-platform migration method and device |
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Application publication date: 20181123 |